OpenCores
URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 82 to Rev 83
    ↔ Reverse comparison
  •

Rev 82 → Rev 83

/sdhc-sc-core/trunk/src/grpSd/pkgSd/src/Sd-p.vhdl
41,6 → 41,13
endbit : std_ulogic; --cSdEndBit
end record aSdCmdToken;
 
constant cDefaultSdCmdToken : aSdCmdToken := (
startbit => cActivated,
transbit => cActivated,
content => cDefaultSdCmdContent,
crc7 => (others => '0'),
endbit => cInactivated);
 
-- SD Card Regs
subtype aVoltageWindow is std_ulogic_vector(23 downto 15);
constant cVoltageWindow : aVoltageWindow := (others => '1');
80,12 → 87,12
constant cCIDLength : natural := 127;
 
constant cDefaultSdRegCID : aSdRegCID := (
mid => (others => '0'),
oid => (others => '0'),
name => (others => '0'),
revision => (others => '0'),
mid => (others => '0'),
oid => (others => '0'),
name => (others => '0'),
revision => (others => '0'),
serialnumber => (others => '0'),
date => (others => '0'));
date => (others => '0'));
 
function UpdateCID(icid : in aSdRegCID; data : in std_ulogic; pos : in
natural) return aSdRegCID;
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/wave.do
1,9 → 1,17
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /Testbed/CmdInterface/Clk
add wave -noupdate -format Logic /Testbed/CmdInterface/nResetAsync
add wave -noupdate -format Logic /Testbed/CmdInterface/Cmd
add wave -noupdate -divider Controller
add wave -noupdate -format Logic /Testbed/top/iclk
add wave -noupdate -format Logic /Testbed/top/inresetasync
add wave -noupdate -format Logic /Testbed/top/iocmd
add wave -noupdate -format Logic /Testbed/top/osclk
add wave -noupdate -format Literal /Testbed/top/iodata
add wave -noupdate -format Literal /Testbed/top/oledbank
add wave -noupdate -format Literal /Testbed/top/tocontroller
add wave -noupdate -format Literal /Testbed/top/fromcontroller
add wave -noupdate -divider controller
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/oledbank
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/reg
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/nextreg
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/state
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/nextstate
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/osdcmd
10,33 → 18,21
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/isdcmd
add wave -noupdate -format Logic /Testbed/top/sdcontroller_inst/inresetasync
add wave -noupdate -format Logic /Testbed/top/sdcontroller_inst/iclk
add wave -noupdate -divider Cmd
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/state
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/nextstate
add wave -noupdate -divider cmd
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/iclk
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/inresetasync
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/ifromcontroller
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/otocontroller
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/iocmd
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/serialcrc
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/crccorrect
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/counter
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/nextcounter
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/output
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/iocmd
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/otocontroller
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/ifromcontroller
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/inresetasync
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/iclk
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/receivedtoken
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/nextreceivedtoken
add wave -noupdate -divider Crc
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/crc7_inst/iclk
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/crc7_inst/inresetasync
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/crc7_inst/iclear
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/crc7_inst/idatain
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/crc7_inst/idata
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/crc7_inst/oiscorrect
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/crc7_inst/oserial
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/crc7_inst/oparallel
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/crc7_inst/regs
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/crcout
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/r
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/nextr
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/o
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/nexto
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2937 ns} 0}
WaveRestoreCursors {{Cursor 1} {1940 ns} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
51,4 → 47,4
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {1133 ns} {3046 ns}
WaveRestoreZoom {0 ns} {17105 ns}
/sdhc-sc-core/trunk/src/grpSd/unitSdCmd/src/SdCmd-Rtl-ea.vhdl
29,231 → 29,248
 
architecture Rtl of SdCmd is
 
type aSdCmdState is (idle, startbit, transbit, cmdid, arg, crc, endbit,
recvtransbit, recvcmdid, recvarg, recvcid, recvcrc, recvendbit, recvcrcerror);
type aSdCmdState is (idle, sending, receiving);
type aRegion is (startbit, transbit, cmdid, arg, cid, crc, endbit);
subtype aCounter is unsigned(integer(log2(real(128))) - 1 downto 0);
 
type aRegSet is record
State : aSdCmdState;
Region : aRegion;
Counter : aCounter;
ReceivedToken : aSdCmdToken;
Cid : aSdRegCID;
end record aRegSet;
 
constant cDefaultRegSet : aRegSet := (
State => idle,
Region => startbit,
Counter => to_unsigned(0, aCounter'length),
ReceivedToken => cDefaultSdCmdToken,
Cid => cDefaultSdRegCID);
 
type aOutputRegSet is record
Controller : aSdCmdToController;
Cmd : std_ulogic;
En : std_ulogic;
end record aOutputRegSet;
 
constant cDefaultOutputRegSet : aOutputRegSet := (
Controller => cDefaultSdCmdToController,
Cmd => '0',
En => '0');
 
type aCrcOut is record
Clear : std_ulogic;
Clear : std_ulogic;
DataIn : std_ulogic;
Data : std_ulogic;
Data : std_ulogic;
end record aCrcOut;
 
constant cDefaultCrcOut : aCrcOut := (
Clear => cInactivated,
Clear => cInactivated,
DataIn => cInactivated,
Data => cInactivated);
Data => cInactivated);
 
type aSdCmdOut is record
Crc : aCrcOut;
Controller : aSdCmdToController;
Cmd : std_ulogic;
En : std_ulogic;
end record aSdCmdOut;
 
constant cDefaultOut : aSdCmdOut := (
Crc => cDefaultCrcOut,
Controller => cDefaultSdCmdToController,
Cmd => '0', En => '0');
 
 
signal State, NextState : aSdCmdState;
signal SerialCrc, CrcCorrect : std_ulogic;
signal Counter, NextCounter : unsigned(integer(log2(real(128))) - 1 downto 0);
signal Output : aSdCmdOut;
signal CrcOut : aCrcOut;
 
signal ReceivedToken, NextReceivedToken : aSdCmdToken;
signal Cid, NextCid : aSdRegCID;
signal R, NextR : aRegSet;
signal O, NextO : aOutputRegSet;
 
type aReg is record
Cmd : std_ulogic;
En : std_ulogic;
end record aReg;
 
signal Reg : aReg;
 
begin
 
ioCmd <= Reg.Cmd when Reg.En = cActivated else 'Z';
ioCmd <= O.Cmd when O.En = cActivated else 'Z';
oToController <= O.Controller;
 
oToController <= Output.Controller;
 
-- State register
CmdStateReg : process (iClk, inResetAsync)
begin
if inResetAsync = cInactivated then
State <= idle;
Counter <= to_unsigned(0, Counter'length);
Reg.Cmd <= cInactivated;
Reg.En <= cInactivated;
R <= cDefaultRegSet;
O <= cDefaultOutputRegSet;
 
elsif iClk'event and iClk = cActivated then
State <= NextState;
Counter <= NextCounter;
ReceivedToken <= NextReceivedToken;
Cid <= NextCid;
Reg.Cmd <= Output.Cmd;
Reg.En <= Output.En;
R <= NextR;
O <= NextO;
 
end if;
end process CmdStateReg;
 
-- Comb. process
NextStateAndOutput : process (iFromController, ioCmd, SerialCrc, CrcCorrect,
State, Counter, ReceivedToken, Cid)
R)
 
procedure NextStateWhenAllSent (constant nextlength : in natural; constant toState : in aSdCmdState) is
procedure NextStateWhenAllSent (constant nextlength : in natural; constant toRegion : in aRegion) is
begin
if (Counter > 0) then
NextCounter <= Counter - 1;
if (R.Counter > 0) then
NextR.Counter <= R.Counter - 1;
else
NextCounter <= to_unsigned(nextlength, NextCounter'length);
NextState <= toState;
NextR.Counter <= to_unsigned(nextlength, NextR.Counter'length);
NextR.Region <= toRegion;
end if;
end procedure NextStateWhenAllSent;
 
procedure ShiftIntoCrc(constant data : in std_ulogic) is
begin
Output.Crc.DataIn <= cActivated;
Output.Crc.Data <= data;
CrcOut.DataIn <= cActivated;
CrcOut.Data <= data;
end procedure;
 
procedure SendBitsAndCalcCrc (signal container : in std_ulogic_vector;
constant toState : in aSdCmdState; constant nextlength : in natural) is
procedure SendBitsAndCalcCrc (signal container : in std_ulogic_vector; constant toRegion : in aRegion; constant nextlength : in natural) is
begin
Output.En <= cActivated;
Output.Cmd <= container(to_integer(Counter));
ShiftIntoCrc(container(to_integer(Counter)));
NextStateWhenAllSent(nextlength, toState);
NextO.En <= cActivated;
NextO.Cmd <= container(to_integer(R.Counter));
 
ShiftIntoCrc(container(to_integer(R.Counter)));
NextStateWhenAllSent(nextlength, toRegion);
end procedure SendBitsAndCalcCrc;
 
procedure RecvBitsAndCalcCrc (signal container : out std_ulogic_vector;
constant toState : in aSdCmdState; constant nextlength : in natural) is
procedure RecvBitsAndCalcCrc (signal container : out std_ulogic_vector; constant toRegion : in aRegion; constant nextlength : in natural) is
begin
container(to_integer(Counter)) <= ioCmd;
container(to_integer(R.Counter)) <= ioCmd;
ShiftIntoCrc(ioCmd);
NextStateWhenAllSent(nextlength, toState);
NextStateWhenAllSent(nextlength, toRegion);
end procedure RecvBitsAndCalcCrc;
 
 
begin
-- defaults
NextState <= State;
NextCounter <= Counter;
NextReceivedToken <= ReceivedToken;
NextCid <= Cid;
Output <= cDefaultOut;
Output.Controller.Content <= ReceivedToken.content;
Output.Controller.Cid <= Cid;
NextR <= R;
NextO <= cDefaultOutputRegSet;
NextO.Controller.Content <= R.ReceivedToken.content;
NextO.Controller.Cid <= R.Cid;
CrcOut <= cDefaultCrcOut;
 
case State is
case R.State is
when idle =>
-- Start receiving or start transmitting
if (ioCmd = cSdStartBit) then
ShiftIntoCrc(ioCmd);
NextReceivedToken.startbit <= ioCmd;
NextState <= recvtransbit;
NextR.ReceivedToken.startbit <= ioCmd;
NextR.State <= receiving;
NextR.Region <= transbit;
elsif (iFromController.Valid = cActivated) then
NextState <= startbit;
NextR.State <= sending;
NextR.Region <= startbit;
end if;
 
when startbit =>
Output.En <= cActivated;
Output.Cmd <= cSdStartBit;
ShiftIntoCrc(cSdStartBit);
NextState <= transbit;
when sending =>
NextO.En <= cActivated;
 
when transbit =>
Output.En <= cActivated;
Output.Cmd <= cSdTransBitHost;
ShiftIntoCrc(cSdTransBitHost);
NextCounter <= to_unsigned(iFromController.Content.id'high,
NextCounter'length);
NextState <= cmdid;
case R.Region is
when startbit =>
NextO.Cmd <= cSdStartBit;
NextR.Region <= transbit;
ShiftIntoCrc(cSdStartBit);
 
when cmdid =>
SendBitsAndCalcCrc(iFromController.Content.id, arg,
iFromController.Content.arg'high);
when transbit =>
NextO.Cmd <= cSdTransBitHost;
NextR.Counter <= to_unsigned(iFromController.Content.id'high, aCounter'length);
NextR.Region <= cmdid;
ShiftIntoCrc(cSdTransBitHost);
 
when arg =>
SendBitsAndCalcCrc(iFromController.Content.arg, crc, crc7'high-1);
when cmdid =>
SendBitsAndCalcCrc(iFromController.Content.id, arg,
iFromController.Content.arg'high);
 
when crc =>
Output.En <= cActivated;
Output.Cmd <= SerialCrc;
if (Counter > 0) then
NextCounter <= Counter - 1;
else
NextState <= endbit;
Output.Controller.Ack <= cActivated;
end if;
when arg =>
SendBitsAndCalcCrc(iFromController.Content.arg, crc, crc7'high-1);
 
when endbit =>
Output.Cmd <= cSdEndBit;
Output.En <= cActivated;
NextState <= idle; -- todo: receive response
when crc =>
NextO.Cmd <= SerialCrc;
 
when recvtransbit =>
Output.Controller.Receiving <= cActivated;
ShiftIntoCrc(ioCmd);
NextReceivedToken.transbit <= ioCmd;
NextCounter <= to_unsigned(NextReceivedToken.Content.id'high,
NextCounter'length);
NextState <= recvcmdid;
if (R.Counter > 0) then
NextR.Counter <= R.Counter - 1;
 
when recvcmdid =>
Output.Controller.Receiving <= cActivated;
if (iFromController.ExpectCID = cInactivated) then
RecvBitsAndCalcCrc(NextReceivedToken.Content.id, recvarg,
NextReceivedToken.Content.arg'high);
elsif (iFromController.ExpectCID = cActivated) then
RecvBitsAndCalcCrc(NextReceivedToken.Content.id, recvcid,
cCIDLength-8);
Output.Crc.Clear <= cActivated;
end if;
else
NextR.Region <= endbit;
NextO.Controller.Ack <= cActivated;
end if;
 
when recvarg =>
Output.Controller.Receiving <= cActivated;
RecvBitsAndCalcCrc(NextReceivedToken.Content.arg, recvcrc,
crc7'high-1);
when endbit =>
NextO.Cmd <= cSdEndBit;
NextR.State <= idle;
NextR.Region <= startbit;
 
when recvcid =>
Output.Controller.Receiving <= cActivated;
NextCid <= UpdateCID(cid, ioCmd, to_integer(Counter)+8);
ShiftIntoCrc(ioCmd);
NextStateWhenAllSent(crc7'high-1, recvcrc);
when others =>
report "SdCmd: Region not handled" severity error;
 
when recvcrc =>
NextReceivedToken.crc7(to_integer(Counter)) <= ioCmd;
ShiftIntoCrc(ioCmd);
end case;
 
if (Counter > 0) then
NextCounter <= Counter - 1;
else
NextState <= recvendbit;
end if;
when receiving =>
NextO.Controller.Receiving <= cActivated;
 
when recvendbit =>
NextReceivedToken.endbit <= ioCmd;
case R.Region is
when transbit =>
NextR.ReceivedToken.transbit <= ioCmd;
NextR.Counter <= to_unsigned(NextR.ReceivedToken.Content.id'high, NextR.Counter'length);
NextR.Region <= cmdid;
ShiftIntoCrc(ioCmd);
 
-- check
if (CrcCorrect = cActivated and ReceivedToken.transbit = cSdTransBitSlave) then
Output.Controller.Valid <= cActivated;
else
Output.Controller.Err <= cActivated;
end if;
NextState <= idle;
when cmdid =>
if (iFromController.ExpectCID = cInactivated) then
RecvBitsAndCalcCrc(NextR.ReceivedToken.Content.id, arg, NextR.ReceivedToken.Content.arg'high);
 
when others =>
elsif (iFromController.ExpectCID = cActivated) then
RecvBitsAndCalcCrc(NextR.ReceivedToken.Content.id, cid, cCIDLength-8);
CrcOut.Clear <= cActivated;
 
end if;
 
when arg =>
RecvBitsAndCalcCrc(NextR.ReceivedToken.Content.arg, crc, crc7'high-1);
 
when cid =>
NextR.Cid <= UpdateCID(R.Cid, ioCmd, to_integer(R.Counter)+8);
ShiftIntoCrc(ioCmd);
NextStateWhenAllSent(crc7'high-1, crc);
 
when crc =>
NextR.ReceivedToken.crc7(to_integer(R.Counter)) <= ioCmd;
ShiftIntoCrc(ioCmd);
 
if (R.Counter > 0) then
NextR.Counter <= R.Counter - 1;
else
NextR.Region <= endbit;
end if;
 
when endbit =>
NextR.ReceivedToken.endbit <= ioCmd;
 
-- check
if (CrcCorrect = cActivated and R.ReceivedToken.transbit = cSdTransBitSlave) then
NextO.Controller.Valid <= cActivated;
 
else
NextO.Controller.Err <= cActivated;
 
end if;
NextR.State <= idle;
NextR.Region <= startbit;
 
when others =>
report "SdCmd : Region not handled" severity error;
 
end case;
 
when others =>
report "SdCmd: State not handled" severity error;
 
end case;
 
end process NextStateAndOutput;
 
CRC7_inst: entity work.Crc
generic map(gPolynom => crc7)
port map(iClk => iClk,
inResetAsync => inResetAsync,
iClear => Output.Crc.Clear,
iDataIn => Output.Crc.DataIn,
iData => Output.Crc.Data,
oIsCorrect => CrcCorrect,
oSerial => SerialCrc);
generic map(
gPolynom => crc7)
port map(
iClk => iClk,
inResetAsync => inResetAsync,
iClear => CrcOut.Clear,
iDataIn => CrcOut.DataIn,
iData => CrcOut.Data,
oIsCorrect => CrcCorrect,
oSerial => SerialCrc);
 
end architecture Rtl;
/sdhc-sc-core/trunk/src/grpSd/unitSdCmd/src/tbSdCmd-Bhv-ea.vhdl
19,7 → 19,7
 
signal Clk : std_ulogic := cInactivated;
signal Finished : std_ulogic := cInactivated;
signal nResetAsync : std_ulogic;
signal nResetAsync : std_ulogic := cnActivated;
signal ToCmd : aSdCmdFromController;
signal FromCmd : aSdCmdToController;
signal Cmd : std_logic;
/sdhc-sc-core/trunk/src/grpSd/unitSdCmd/sim/wave.do
1,33 → 1,30
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tbsdcmd/dut/iclk
add wave -noupdate -format Logic /tbsdcmd/dut/inresetasync
add wave -noupdate -format Literal /tbsdcmd/dut/ifromcontroller
add wave -noupdate -format Literal /tbsdcmd/dut/otocontroller
add wave -noupdate -format Logic /tbsdcmd/dut/iocmd
add wave -noupdate -format Logic /tbsdcmd/dut/serialcrc
add wave -noupdate -format Logic /tbsdcmd/dut/crccorrect
add wave -noupdate -format Literal /tbsdcmd/dut/crcout
add wave -noupdate -format Literal /tbsdcmd/dut/r
add wave -noupdate -format Literal /tbsdcmd/dut/nextr
add wave -noupdate -format Literal /tbsdcmd/dut/o
add wave -noupdate -format Literal /tbsdcmd/dut/nexto
add wave -noupdate -divider tb
add wave -noupdate -format Literal /tbsdcmd/gclkperiod
add wave -noupdate -format Logic /tbsdcmd/clk
add wave -noupdate -format Logic /tbsdcmd/finished
add wave -noupdate -format Logic /tbsdcmd/nresetasync
add wave -noupdate -format Literal /tbsdcmd/tocmd
add wave -noupdate -format Literal /tbsdcmd/fromcmd
add wave -noupdate -format Logic /tbsdcmd/cmd
add wave -noupdate -format Literal /tbsdcmd/sentcmd
add wave -noupdate -format Literal /tbsdcmd/counter
add wave -noupdate -format Logic /tbsdcmd/save
add wave -noupdate -format Literal /tbsdcmd/dut/state
add wave -noupdate -format Literal /tbsdcmd/dut/nextstate
add wave -noupdate -format Logic /tbsdcmd/dut/serialcrc
add wave -noupdate -format Literal /tbsdcmd/dut/counter
add wave -noupdate -format Literal /tbsdcmd/dut/nextcounter
add wave -noupdate -format Literal /tbsdcmd/dut/output
add wave -noupdate -format Logic /tbsdcmd/dut/iocmd
add wave -noupdate -format Literal /tbsdcmd/dut/ifromcontroller
add wave -noupdate -format Logic /tbsdcmd/dut/inresetasync
add wave -noupdate -format Logic /tbsdcmd/dut/iclk
add wave -noupdate -format Logic /tbsdcmd/dut/crc7_inst/iclk
add wave -noupdate -format Logic /tbsdcmd/dut/crc7_inst/inresetasync
add wave -noupdate -format Logic /tbsdcmd/dut/crc7_inst/iclear
add wave -noupdate -format Logic /tbsdcmd/dut/crc7_inst/idatain
add wave -noupdate -format Logic /tbsdcmd/dut/crc7_inst/idata
add wave -noupdate -format Logic /tbsdcmd/dut/crc7_inst/oserial
add wave -noupdate -format Literal /tbsdcmd/dut/crc7_inst/oparallel
add wave -noupdate -format Literal /tbsdcmd/dut/crc7_inst/regs
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {242 ns} 0}
WaveRestoreCursors {{Cursor 1} {540 ns} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left

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