URL
https://opencores.org/ocsvn/v586/v586/trunk
Subversion Repositories v586
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- from Rev 82 to Rev 83
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Rev 82 → Rev 83
/v586/trunk/uart16750/uart16750_latest.tar.gz
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v586/trunk/uart16750/uart16750_latest.tar.gz
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Index: v586/trunk/README
===================================================================
--- v586/trunk/README (revision 82)
+++ v586/trunk/README (revision 83)
@@ -4,9 +4,6 @@
TOP_SYS.v put the processor with a wishbone interface , an sram inteface
and rom for boot.
-ucf:
-constraint file for ISE and nexys4
-
xdc:
constraint file for Vivado and nexys4
@@ -16,17 +13,16 @@
mcs map:
0x0: fpga bit file
0x400000: vmlinux uncompressed
-0x800000: iniramfs compressed
+0x800000: iniramfs compressed built with buildroot 2016.02
bin:
-contains binary files that have been used to build mcs file
+contains binary files that have been used to build mcs fil withe impact
-config:
-.config file used for configure vmlinux.bin kernel in v3.17 kernel version
+patch:
+patch file to be applied to linux 3.19 , also provides the .config
-
boot:
-contains assembly source of the internal rom boot
+contains assembly source of the internal rom boot and also hex files used for axi_rom
tb:
run scripts for simulation : run_verilator_simu.sourceme
@@ -38,7 +34,3 @@
note: mem models for boot are necessary for ise compilation for the internal rom
the script run_sw.scr builds mem files.
-uart16750:
-just recopy tar file from opencores of the rtl/vhdl sources that are used for the serial interface.
-In fact inside fpga or simulation the model used is a mapped netlist from this vhdl and the netlist is inside the rtl directory, it is uart_16750.v.
-