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URL https://opencores.org/ocsvn/amber/amber/trunk

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  • This comparison shows the changes necessary to convert path
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    from Rev 83 to Rev 84
    Reverse comparison

Rev 83 → Rev 84

/amber/trunk/hw/vlog/system/wishbone_arbiter.v
173,8 → 173,6
 
reg m0_wb_hold_r = 'd0;
reg m1_wb_hold_r = 'd0;
// wire m0_in_cycle;
// wire m1_in_cycle;
wire current_master;
reg current_master_r = 'd0;
wire next_master;
277,17 → 275,17
assign o_s5_wb_adr = master_adr;
assign o_s5_wb_dat = master_wdat;
assign o_s5_wb_sel = master_sel;
assign o_s5_wb_we = current_slave == 5'd5 ? master_we : 1'd0;
assign o_s5_wb_cyc = current_slave == 5'd5 ? master_cyc : 1'd0;
assign o_s5_wb_stb = current_slave == 5'd5 ? master_stb : 1'd0;
assign o_s5_wb_we = current_slave == 4'd5 ? master_we : 1'd0;
assign o_s5_wb_cyc = current_slave == 4'd5 ? master_cyc : 1'd0;
assign o_s5_wb_stb = current_slave == 4'd5 ? master_stb : 1'd0;
 
// Timers Outputs
assign o_s6_wb_adr = master_adr;
assign o_s6_wb_dat = master_wdat;
assign o_s6_wb_sel = master_sel;
assign o_s6_wb_we = current_slave == 6'd6 ? master_we : 1'd0;
assign o_s6_wb_cyc = current_slave == 6'd6 ? master_cyc : 1'd0;
assign o_s6_wb_stb = current_slave == 6'd6 ? master_stb : 1'd0;
assign o_s6_wb_we = current_slave == 4'd6 ? master_we : 1'd0;
assign o_s6_wb_cyc = current_slave == 4'd6 ? master_cyc : 1'd0;
assign o_s6_wb_stb = current_slave == 4'd6 ? master_stb : 1'd0;
 
// Interrupt Controller
assign o_s7_wb_adr = master_adr;
/amber/trunk/hw/vlog/amber23/a23_cache.v
220,7 → 220,7
always @ ( posedge i_clk )
if ( i_cache_flush )
begin
c_state <= C_INIT;
c_state <= CS_INIT;
source_sel <= 1'd1 << C_INIT;
init_count <= 'd0;
`ifdef A23_CACHE_DEBUG

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