OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 83 to Rev 84
    ↔ Reverse comparison
  •

Rev 83 → Rev 84

/ion/trunk/src/bin2hdl.py
24,6 → 24,7
print "(note the flash and xram info are used in simulation only)"
print ""
print "Additionally, any of these arguments can be given:"
print "{t|log_trigger} <number> Fetch address that triggers file logging"
print "{s|sim_len} <number> Length of simulation in clock cycles"
print "{d|data} <filename> Data binary image file name or 'empty'"
print "{h|help} Display some help text and exit"
185,6 → 186,7
code_table_size = -1 # size of VHDL table
data_table_size = -1 # size of VHDL table
flash_table_size = 32; # default size of flash table in 32-bit words
log_trigger_addr = "X\"FFFFFFFF\"" # default log trigger address
flash = ['\0']*4*flash_table_size # default simulated flash
bin_words = 0 # size of binary file in 32-bit words
simulation_length = 22000 # length of logic simulation in clock cycles
192,9 → 194,9
#
 
try:
opts, args = getopt.getopt(argv, "hc:d:v:a:e:o:i:s:f:",
opts, args = getopt.getopt(argv, "hc:d:v:a:e:o:i:s:f:t:",
["help", "code=", "data=", "vhdl=", "architecture=",
"entity=", "output=", "indent=", "sim_len=", "flash=",
"entity=", "output=", "indent=", "sim_len=", "flash=", "log_trigger=",
"code_size=", "data_size=", "flash_size="])
except getopt.GetoptError, err:
print ""
224,6 → 226,8
entity_name = arg
elif opt in ("-i", "--indent"):
indent = int(arg)
elif opt in ("-t", "--log_trigger"):
log_trigger_addr = "X\"%08X\"" % (int(arg,16))
elif opt in ("-s", "--sim_len"):
simulation_length = int(arg)
elif opt == "--code_size":
240,8 → 244,8
usage()
sys.exit(2)
 
# Open binary code and data input files and read them into buffers
#---------------------------------------------------------------------------
# Read BRAM initialization file, if any
try:
fin = open(code_filename, "rb")
code = fin.read()
249,6 → 253,19
except IOError:
print "Binary File %s not found" % code_filename
 
# Make sure the code and data will fit in the tables
bin_words = len(code) / 4
if bin_words > code_table_size:
print "Code does not fit table: " + str(bin_words) + " words,",
print str(code_table_size) + " table entries"
sys.exit(1)
 
# Build the VHDL strings for each slice of the BRAM tables
vhdl_code_strings = build_vhdl_tables(code, code_table_size, indent)
 
#---------------------------------------------------------------------------
# Read XRAM initialization file, if any.
if data_filename != "":
if data_filename == "empty":
data = []
259,7 → 276,26
fin.close()
except IOError:
print "Binary File %s not found" % data_filename
# FIXME We're not checking for BSS size here, only .data (?)
bin_words = len(data) / 4
if bin_words > data_table_size:
print "Data does not fit table: " + str(bin_words) + " words,",
print str(data_table_size) + " table entries"
sys.exit(1)
 
vhdl_data_strings = build_vhdl_tables(data, data_table_size, indent)
else:
# In case we didn't get a data binary, we will initialize any XRAM in
# the template with zeros
vhdl_data_strings = (["(others => X\"00\")"]*4) + \
(["(others => X\"00\")"]*2) + \
(["(others => X\"00000000\")"])
#---------------------------------------------------------------------------
# Read FLASH initialization file, if any
if flash_filename != "":
if flash_filename == "empty":
flash = [0]*flash_table_size
270,25 → 306,8
fin.close()
except IOError:
print "Binary File %s not found" % flash_filename
#print "Read " + str(len(code)) + " bytes."
# Make sure the code and data will fit in the tables
bin_words = len(code) / 4
if bin_words > code_table_size:
print "Code does not fit table: " + str(bin_words) + " words,",
print str(code_table_size) + " table entries"
sys.exit(1)
if data_filename != "":
# FIXME We're not checking for BSS size here, only .data (?)
bin_words = len(data) / 4
if bin_words > data_table_size:
print "Data does not fit table: " + str(bin_words) + " words,",
print str(data_table_size) + " table entries"
sys.exit(1)
if flash_filename != "":
 
# make sure file will fit simulated FLASH size
bin_words = len(flash) / 4
if bin_words > flash_table_size:
print "Flash data does not fit table: " + str(bin_words) + " words,",
296,19 → 315,14
sys.exit(1)
 
 
# Build the VHDL strings for each slice of both code and data tables
vhdl_code_strings = build_vhdl_tables(code, code_table_size, indent)
if data_filename != "":
vhdl_data_strings = build_vhdl_tables(data, data_table_size, indent)
else:
# In case we didn't get a data binary, we want the vhdl compilation
# to fail when @data@ tags are used, just to catch the error
vhdl_data_strings = ["error: missing data binary file"]*6
# Build the VHDL strings for the simulated FLASH
vhdl_flash_string = build_vhdl_flash_table(flash, flash_table_size, indent)
# Now start scanning the VHDL template, inserting data where needed
#===========================================================================
# OK, we just read all binary files and built all VHDL memory initialization
# strings. Now start scanning the VHDL template, inserting data where needed
# Read template file...
fin = open(vhdl_filename, "r")
vhdl_lines = fin.readlines()
327,7 → 341,8
"@xram_size@",
"@code_table_size@","@code_addr_size@",
"@data_table_size@","@data_addr_size@",
"@prom_size@"];
"@prom_size@",
"@log_trigger_addr@"];
replacement = vhdl_code_strings + vhdl_data_strings + \
[vhdl_flash_string,
entity_name, arch_name,
337,7 → 352,8
str(int(math.floor(math.log(code_table_size,2)))),
str(data_table_size),
str(int(math.floor(math.log(data_table_size,2)))),
str(flash_table_size)]
str(flash_table_size),
log_trigger_addr]
# Now traverse the template lines replacing any keywords with the proper
# vhdl stuff we just built above.
/ion/trunk/vhdl/tb/mips_tb_pkg.vhdl
82,6 → 82,11
read_pending : boolean;
write_pending : boolean;
-- Log trigger --------------------------------------------------
-- Enable logging after fetching from a given address -----------
log_trigger_address : t_word;
log_triggered : boolean;
end record t_log_info;
 
procedure log_cpu_activity(
91,6 → 96,7
entity_name : string;
signal info : inout t_log_info;
signal_name : string;
trigger_addr : in t_word;
file l_file : TEXT);
 
 
99,7 → 105,7
package body mips_tb_pkg is
 
procedure log_cpu_status(
signal info : inout t_log_info;
signal info : inout t_log_info;
file l_file : TEXT) is
variable i : integer;
variable ri : std_logic_vector(7 downto 0);
107,6 → 113,16
variable k : integer := 2;
begin
-- Trigger logging if the CPU fetches from trigger address
if (info.log_trigger_address(31 downto 2) = info.present_code_rd_addr) and
info.code_rd_vma='1' then
info.log_triggered <= true;
assert 1=0
report "Log triggered by fetch from address 0x"& hstr(info.log_trigger_address)
severity note;
end if;
-- This is the address of the opcode that triggered the changed we're
-- about to log
full_pc := info.pc_m(k);
119,9 → 135,11
ri := X"00";
for i in 0 to 31 loop
if info.prev_rbank(i)/=info.rbank(i)
and info.prev_rbank(i)(0)/='U' then
print(l_file, "("& hstr(full_pc)& ") "&
"["& hstr(ri)& "]="& hstr(info.rbank(i)));
and info.prev_rbank(i)(0)/='U' then
if info.log_triggered then
print(l_file, "("& hstr(full_pc)& ") "&
"["& hstr(ri)& "]="& hstr(info.rbank(i)));
end if;
end if;
ri := ri + 1;
end loop;
143,10 → 161,12
if info.pending_data_wr_we(0)='0' then
temp := temp and X"ffffff00";
end if;
print(l_file, "("& hstr(info.pending_data_wr_pc) &") ["&
hstr(info.pending_data_wr_addr) &"] |"&
hstr(ri)& "|="&
hstr(temp)& " WR" );
if info.log_triggered then
print(l_file, "("& hstr(info.pending_data_wr_pc) &") ["&
hstr(info.pending_data_wr_addr) &"] |"&
hstr(ri)& "|="&
hstr(temp)& " WR" );
end if;
info.write_pending <= false;
end if;
 
153,10 → 173,12
 
-- Log memory reads ------------------------------------------
if info.read_pending and info.load='1' then
print(l_file, "("& hstr(info.pc_m(1)) &") ["&
hstr(info.pending_data_rd_addr) &"] <"&
"**"& ">="&
hstr(info.word_loaded)& " RD" ); -- FIXME
if info.log_triggered then
print(l_file, "("& hstr(info.pc_m(1)) &") ["&
hstr(info.pending_data_rd_addr) &"] <"&
"**"& ">="&
hstr(info.word_loaded)& " RD" ); -- FIXME
end if;
info.read_pending <= false;
end if;
177,9 → 199,13
-- negate reg_lo before displaying
temp := not info.reg_lo;
temp := temp + 1;
print(l_file, "("& hstr(temp2)& ") [LO]="& hstr(temp));
if info.log_triggered then
print(l_file, "("& hstr(temp2)& ") [LO]="& hstr(temp));
end if;
else
print(l_file, "("& hstr(temp2)& ") [LO]="& hstr(info.reg_lo));
if info.log_triggered then
print(l_file, "("& hstr(temp2)& ") [LO]="& hstr(info.reg_lo));
end if;
end if;
end if;
if info.prev_hi /= info.reg_hi and info.prev_hi(0)/='U' then
190,13 → 216,17
else
temp2 := info.pc_m(k-1);
end if;
 
print(l_file, "("& hstr(temp2)& ") [HI]="& hstr(info.reg_hi));
if info.log_triggered then
print(l_file, "("& hstr(temp2)& ") [HI]="& hstr(info.reg_hi));
end if;
end if;
if info.prev_epc /= info.cp0_epc and info.cp0_epc(31)/='U' then
temp := info.cp0_epc & "00";
print(l_file, "("& hstr(info.pc_m(k-1))& ") [EP]="& hstr(temp));
if info.log_triggered then
print(l_file, "("& hstr(info.pc_m(k-1))& ") [EP]="& hstr(temp));
end if;
info.prev_epc <= info.cp0_epc;
end if;
 
242,6 → 272,7
entity_name : string;
signal info : inout t_log_info;
signal_name : string;
trigger_addr : in t_word;
file l_file : TEXT) is
begin
init_signal_spy("/"&entity_name&"/p1_rbank", signal_name&".rbank", 0, -1);
265,6 → 296,12
if reset='1' then
-- FIXME should use real reset vector here
info.pc_m <= (others => X"00000000");
-- By default logging is DISABLED by triggering with an impossible
-- fetch address. Logging must be enabled from outside by
-- setting log_trigger_address to a suitable value.
info.log_trigger_address <= trigger_addr;
info.log_triggered <= false;
else
log_cpu_status(info, l_file);
end if;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.