OpenCores
URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 84 to Rev 85
    Reverse comparison

Rev 84 → Rev 85

/funbase_ip_library/trunk/TUT/ip.hwp.interface/altera_de2_pll_25/ip-xact/altera_de2_pll_25.1.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 11:03:01 pe marras 11 2011-->
<spirit:component kts_firmtype="HW" kts_producthier="IP" kts_reuselevel="Block">
<!--Created by Kactus 2 document generator 13:28:26 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.misc</spirit:library>
<spirit:name>altera_de2_pll_25</spirit:name>
66,11 → 66,27
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>rtl</spirit:name>
<spirit:envIdentifier>vhdl::</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>HDLsources</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>c0</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
77,6 → 93,13
<spirit:name>inclk0</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
90,6 → 113,7
<spirit:name>../vhd/ALTPLL_for_DE2_50to25.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
<spirit:logicalName spirit:default="false">work</spirit:logicalName>
<spirit:buildCommand>
<spirit:replaceDefaultFlags>false</spirit:replaceDefaultFlags>
</spirit:buildCommand>
97,4 → 121,12
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>25 MHz Altera ALTPLL instantiation for Cyclone II FPGA's with input clk of 50 MHz (mul = 1, div = 2)</spirit:description>
<spirit:vendorExtensions>
<kactus2:extensions>
<kactus2:kts_attributes>
<kactus2:kts_productHier>Global</kactus2:kts_productHier>
<kactus2:kts_firmness>Mutable</kactus2:kts_firmness>
</kactus2:kts_attributes>
</kactus2:extensions>
</spirit:vendorExtensions>
</spirit:component>
/funbase_ip_library/trunk/TUT/ip.hwp.interface/udp_ip/1.0/ip-xact/udp_ip_dm9000a.1.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 11:06:26 pe marras 11 2011-->
<spirit:component kts_firmtype="HW" kts_producthier="IP" kts_reuselevel="Block">
<!--Created by Kactus 2 document generator 13:27:30 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.interface</spirit:library>
<spirit:name>udp_ip_dm9000a</spirit:name>
601,6 → 601,15
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>rtl</spirit:name>
<spirit:envIdentifier>vhdl::</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>HDLsources</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>clk</spirit:name>
610,6 → 619,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
620,6 → 636,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
630,6 → 653,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
640,6 → 670,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
650,6 → 687,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
660,6 → 704,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
670,6 → 721,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
680,6 → 738,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
690,6 → 755,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
700,6 → 772,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
710,6 → 789,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
720,6 → 806,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
730,6 → 823,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
740,6 → 840,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
750,6 → 857,13
<spirit:left>47</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:driver>
763,6 → 877,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
773,6 → 894,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
783,6 → 911,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
793,6 → 928,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
799,6 → 941,13
<spirit:name>rx_error_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
809,6 → 958,13
<spirit:left>10</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
819,6 → 975,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
829,6 → 992,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
839,6 → 1009,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
849,6 → 1026,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
859,6 → 1043,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
869,6 → 1060,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
879,6 → 1077,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
889,6 → 1094,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
899,6 → 1111,13
<spirit:left>10</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
909,6 → 1128,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
1051,4 → 1277,12
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>DM9000A controller and UDP/IP.</spirit:description>
<spirit:vendorExtensions>
<kactus2:extensions>
<kactus2:kts_attributes>
<kactus2:kts_productHier>Global</kactus2:kts_productHier>
<kactus2:kts_firmness>Mutable</kactus2:kts_firmness>
</kactus2:kts_attributes>
</kactus2:extensions>
</spirit:vendorExtensions>
</spirit:component>
/funbase_ip_library/trunk/TUT/ip.hwp.interface/udp_ip/1.0/ip-xact/udp_ip_lan91c111.1.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 11:07:05 pe marras 11 2011-->
<spirit:component kts_firmtype="HW" kts_producthier="IP" kts_reuselevel="Block">
<!--Created by Kactus 2 document generator 13:27:53 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.interface</spirit:library>
<spirit:name>udp_ip_lan91c111</spirit:name>
601,6 → 601,15
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>rtl</spirit:name>
<spirit:envIdentifier>vhdl::</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>HDLsources</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>clk</spirit:name>
610,6 → 619,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
620,6 → 636,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
630,6 → 653,13
<spirit:left>14</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
640,6 → 670,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
650,6 → 687,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
660,6 → 704,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
670,6 → 721,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
680,6 → 738,13
<spirit:left>3</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
690,6 → 755,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
700,6 → 772,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
710,6 → 789,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
720,6 → 806,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
730,6 → 823,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
740,6 → 840,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
750,6 → 857,13
<spirit:left>47</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:driver>
763,6 → 877,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
773,6 → 894,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
783,6 → 911,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
793,6 → 928,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
799,6 → 941,13
<spirit:name>rx_error_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
809,6 → 958,13
<spirit:left>10</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
819,6 → 975,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
829,6 → 992,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
839,6 → 1009,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
849,6 → 1026,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
859,6 → 1043,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
869,6 → 1060,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
879,6 → 1077,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
889,6 → 1094,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
899,6 → 1111,13
<spirit:left>10</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
909,6 → 1128,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
1051,4 → 1277,12
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>UDP/IP and LAN91C111 controller.</spirit:description>
<spirit:vendorExtensions>
<kactus2:extensions>
<kactus2:kts_attributes>
<kactus2:kts_productHier>Global</kactus2:kts_productHier>
<kactus2:kts_firmness>Mutable</kactus2:kts_firmness>
</kactus2:kts_attributes>
</kactus2:extensions>
</spirit:vendorExtensions>
</spirit:component>
/funbase_ip_library/trunk/TUT/ip.hwp.interface/udp_ip/1.0/ip-xact/simple_udp_flood_example.1.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 11:05:01 pe marras 11 2011-->
<spirit:component kts_firmtype="HW" kts_producthier="IP" kts_reuselevel="Block">
<!--Created by Kactus 2 document generator 13:26:21 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.interface</spirit:library>
<spirit:name>simple_udp_flood_example</spirit:name>
489,11 → 489,27
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>rtl</spirit:name>
<spirit:envIdentifier>vhdl::</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>HDLsources</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>clk</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
504,6 → 520,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
510,6 → 533,13
<spirit:name>fatal_error_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
516,6 → 546,13
<spirit:name>link_up_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
522,6 → 559,13
<spirit:name>link_up_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
528,6 → 572,13
<spirit:name>new_rx_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
534,6 → 585,13
<spirit:name>new_tx_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
544,6 → 602,13
<spirit:left>47</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
550,6 → 615,13
<spirit:name>rst_n</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
560,6 → 632,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
566,6 → 645,13
<spirit:name>rx_data_valid_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
572,6 → 658,13
<spirit:name>rx_erroneous_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
578,6 → 671,13
<spirit:name>rx_error_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
588,6 → 688,13
<spirit:left>10</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
594,6 → 701,13
<spirit:name>rx_re_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
604,6 → 718,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
614,6 → 735,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
624,6 → 752,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
634,6 → 769,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
644,6 → 786,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
654,6 → 803,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
660,6 → 816,13
<spirit:name>tx_data_valid_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
670,6 → 833,13
<spirit:left>10</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
676,6 → 846,13
<spirit:name>tx_re_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
726,4 → 903,12
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>Connect to UDP/IP controller. Creates TX operations as quickly as possible. Destination and packet size are configurable by using generics.</spirit:description>
<spirit:vendorExtensions>
<kactus2:extensions>
<kactus2:kts_attributes>
<kactus2:kts_productHier>Global</kactus2:kts_productHier>
<kactus2:kts_firmness>Mutable</kactus2:kts_firmness>
</kactus2:kts_attributes>
</kactus2:extensions>
</spirit:vendorExtensions>
</spirit:component>
/funbase_ip_library/trunk/TUT/ip.hwp.interface/udp_ip/1.0/ip-xact/simple_udp_receiver_example.1.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 11:05:47 pe marras 11 2011-->
<spirit:component kts_firmtype="HW" kts_producthier="IP" kts_reuselevel="Block">
<!--Created by Kactus 2 document generator 13:26:45 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.interface</spirit:library>
<spirit:name>simple_udp_receiver_example</spirit:name>
518,6 → 518,15
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>rtl</spirit:name>
<spirit:envIdentifier>vhdl::</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>HDLsources</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>clk</spirit:name>
527,6 → 536,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
537,6 → 553,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
547,6 → 570,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
553,6 → 583,13
<spirit:name>led_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
563,6 → 600,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
569,6 → 613,13
<spirit:name>link_up_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
579,6 → 630,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
589,6 → 647,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
599,6 → 664,13
<spirit:left>47</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
609,6 → 681,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
619,6 → 698,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
629,6 → 715,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
639,6 → 732,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
649,6 → 749,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
659,6 → 766,13
<spirit:left>10</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
669,6 → 783,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
679,6 → 800,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
689,6 → 817,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
699,6 → 834,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
709,6 → 851,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
719,6 → 868,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
729,6 → 885,13
<spirit:left>15</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
739,6 → 902,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
749,6 → 919,13
<spirit:left>10</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
759,6 → 936,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
781,4 → 965,12
<spirit:description>Connect to UDP/IP controller. Receives all packets and blinks a LED as packets are received. Our own IP and MAC addresses are defined in udp_ip_pkg.
 
If you decide to disable ARP, you have to manually add the FPGA MAC address to your PC's ARP table.</spirit:description>
<spirit:vendorExtensions>
<kactus2:extensions>
<kactus2:kts_attributes>
<kactus2:kts_productHier>Global</kactus2:kts_productHier>
<kactus2:kts_firmness>Mutable</kactus2:kts_firmness>
</kactus2:kts_attributes>
</kactus2:extensions>
</spirit:vendorExtensions>
</spirit:component>
/funbase_ip_library/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi_4x/1.0/pcie_to_hibi_4x.1.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 10:49:24 ti marras 8 2011-->
<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<!--Created by Kactus 2 document generator 13:25:41 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.interface</spirit:library>
<spirit:name>pcie_to_hibi_4x</spirit:name>
254,7 → 254,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
267,7 → 267,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
280,7 → 280,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
297,7 → 297,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
314,7 → 314,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
331,7 → 331,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
348,7 → 348,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
361,7 → 361,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
374,7 → 374,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
387,7 → 387,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
400,7 → 400,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
413,7 → 413,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
426,7 → 426,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
439,7 → 439,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
452,7 → 452,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
469,7 → 469,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
486,7 → 486,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
499,7 → 499,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
/funbase_ip_library/trunk/TUT/ip.hwp.interface/sdram2hibi/1.0/sdram2hibi.1.0.xml
1,5 → 1,5
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 17:17:30 30.11.2011-->
<!--Created by Kactus 2 document generator 13:25:59 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.interface</spirit:library>
396,7 → 396,7
<spirit:views>
<spirit:view>
<spirit:name>rtl</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:envIdentifier>vhdl::</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>HDLsources</spirit:localName>
</spirit:fileSetRef>
/funbase_ip_library/trunk/TUT/ip.hwp.interface/altera_statix2_pll_25/ip-xact/altera_statix2_pll_25.1.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 11:04:03 pe marras 11 2011-->
<spirit:component kts_firmtype="HW" kts_producthier="IP" kts_reuselevel="Block">
<!--Created by Kactus 2 document generator 13:28:53 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.misc</spirit:library>
<spirit:name>altera_stratix2_pll_25</spirit:name>
66,6 → 66,15
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>rtl</spirit:name>
<spirit:envIdentifier>vhdl::</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>HDLsources</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>c0</spirit:name>
97,4 → 106,12
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>25 MHz Altera ALTPLL instantiation for Stratix II FPGA's with input clk of 100 MHz (mul = 1, div = 4)</spirit:description>
<spirit:vendorExtensions>
<kactus2:extensions>
<kactus2:kts_attributes>
<kactus2:kts_productHier>Global</kactus2:kts_productHier>
<kactus2:kts_firmness>Mutable</kactus2:kts_firmness>
</kactus2:kts_attributes>
</kactus2:extensions>
</spirit:vendorExtensions>
</spirit:component>
/funbase_ip_library/trunk/TUT/ip.hwp.interface/udp2hibi/1.0/udp2hibi.1.0.xml
1,5 → 1,5
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 16:40:24 30.11.2011-->
<!--Created by Kactus 2 document generator 13:28:03 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.interface</spirit:library>
/funbase_ip_library/trunk/TUT/ip.hwp.accelerator/picture_manip/1.0/picture_manip.1.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 10:33:12 ke marras 9 2011-->
<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<!--Created by Kactus 2 document generator 13:20:20 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.accelerator</spirit:library>
<spirit:name>picture_manip</spirit:name>
288,7 → 288,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
301,7 → 302,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
318,7 → 320,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
335,7 → 338,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
348,7 → 352,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
361,7 → 366,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
374,7 → 380,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
387,7 → 394,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
400,7 → 408,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
417,7 → 426,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
434,7 → 444,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
447,7 → 458,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
460,7 → 472,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
473,7 → 486,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
512,7 → 526,7
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>Simple picture manipulator IP to rotate 8-bit grayscale picture 90 degrees clockwise.</spirit:description>
<spirit:description>Simple picture manipulator IP to rotate 8-bit grayscale picture 90 degrees clockwise. </spirit:description>
<spirit:vendorExtensions>
<kactus2:extensions>
<kactus2:kts_attributes>
/funbase_ip_library/trunk/TUT/ip.hwp.accelerator/video_gen/1.0/video_gen.1.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 13:52:13 ma marras 7 2011-->
<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<!--Created by Kactus 2 document generator 13:22:19 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.accelerator</spirit:library>
<spirit:name>video_gen</spirit:name>
153,11 → 153,27
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>rtl</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>source-code</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>clk_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
164,6 → 180,13
<spirit:name>hibi_av_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
170,6 → 193,13
<spirit:name>hibi_av_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
180,6 → 210,13
<spirit:left>4</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
190,6 → 227,13
<spirit:left>4</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
200,6 → 244,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
210,6 → 261,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
216,6 → 274,13
<spirit:name>hibi_empty_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
222,6 → 287,13
<spirit:name>hibi_full_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
228,6 → 300,13
<spirit:name>hibi_one_d_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
234,6 → 313,13
<spirit:name>hibi_one_p_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
240,6 → 326,13
<spirit:name>hibi_re_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
246,6 → 339,13
<spirit:name>hibi_we_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
252,6 → 352,13
<spirit:name>rst_n</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
/funbase_ip_library/trunk/TUT/ip.hwp.storage/de2_sdram/1.0/ip-xact/de2_sdram_tester.1.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 16:17:54 ke marras 9 2011-->
<spirit:component>
<!--Created by Kactus 2 document generator 13:30:04 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.storage</spirit:library>
<spirit:name>de2_sdram_tester</spirit:name>
403,6 → 403,15
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>rtl</spirit:name>
<spirit:envIdentifier>vhdl::</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>HDLsources</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>LEDG</spirit:name>
416,7 → 425,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
433,7 → 442,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
450,7 → 459,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
467,7 → 476,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
480,7 → 489,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
497,7 → 506,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
514,7 → 523,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
531,7 → 540,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
548,7 → 557,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
565,7 → 574,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
582,7 → 591,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
595,7 → 604,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
608,7 → 617,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
621,7 → 630,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
634,7 → 643,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
647,7 → 656,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
660,7 → 669,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
673,7 → 682,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
686,7 → 695,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
/funbase_ip_library/trunk/TUT/ip.hwp.storage/de2_sdram/1.0/ip-xact/de2_sdram.1.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 16:17:31 ke marras 9 2011-->
<spirit:component>
<!--Created by Kactus 2 document generator 13:29:46 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.storage</spirit:library>
<spirit:name>de2_sdram</spirit:name>
442,6 → 442,15
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>rtl</spirit:name>
<spirit:envIdentifier>vhdl::</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>HDLsources</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>address_in</spirit:name>
455,7 → 464,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
468,7 → 477,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
485,7 → 494,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
498,7 → 507,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
515,7 → 524,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
532,7 → 541,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
549,7 → 558,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
566,7 → 575,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
579,7 → 588,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
592,7 → 601,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
605,7 → 614,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
618,7 → 627,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
631,7 → 640,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
644,7 → 653,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
661,7 → 670,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
678,7 → 687,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
691,7 → 700,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
704,7 → 713,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
717,7 → 726,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
734,7 → 743,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
751,7 → 760,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
764,7 → 773,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
777,7 → 786,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
790,7 → 799,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
/funbase_ip_library/trunk/TUT/ip.hwp.storage/ddrx/a2_ddr_dimm_1GB_full_mem_model.comp/1.0/ddr2_mem_model.comp.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 13:53:04 ma marras 7 2011-->
<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<!--Created by Kactus 2 document generator 13:29:19 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.storage</spirit:library>
<spirit:name>a2_ddr_dimm_1GB_full_mem_model</spirit:name>
131,6 → 131,15
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>rtl</spirit:name>
<spirit:envIdentifier>vhdl::</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>hdlSources</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>mem_addr</spirit:name>
140,6 → 149,13
<spirit:left>13</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
150,6 → 166,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
156,6 → 179,13
<spirit:name>mem_cas_n</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
162,6 → 192,13
<spirit:name>mem_cke</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
172,6 → 209,13
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
182,6 → 226,13
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
188,6 → 239,13
<spirit:name>mem_cs_n</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
198,6 → 256,13
<spirit:left>7</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
208,6 → 273,13
<spirit:left>63</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
218,6 → 290,13
<spirit:left>7</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
228,6 → 307,13
<spirit:left>7</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
234,6 → 320,13
<spirit:name>mem_odt</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
240,6 → 333,13
<spirit:name>mem_ras_n</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
246,6 → 346,13
<spirit:name>mem_we_n</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
/funbase_ip_library/trunk/TUT/ip.hwp.storage/ddrx/hibi_mem_dma.comp/2.0/hibi_mem_dma.comp.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 16:11:23 ti marras 8 2011-->
<spirit:component kts_producthier="Global" kts_reuselevel="Block" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<!--Created by Kactus 2 document generator 13:30:13 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.storage</spirit:library>
<spirit:name>hibi_mem_dma</spirit:name>
436,7 → 436,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
453,7 → 454,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
470,7 → 472,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
483,7 → 486,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
500,7 → 504,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
517,7 → 522,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
534,7 → 540,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
551,7 → 558,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
564,7 → 572,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
577,7 → 586,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
594,7 → 604,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
607,7 → 618,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
624,7 → 636,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
641,7 → 654,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
658,7 → 672,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
675,7 → 690,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
688,7 → 704,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
701,7 → 718,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
714,7 → 732,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
727,7 → 746,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
740,7 → 760,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
757,7 → 778,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
774,7 → 796,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
791,7 → 814,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
804,7 → 828,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
821,7 → 846,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
834,7 → 860,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
847,7 → 874,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
864,7 → 892,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
877,7 → 906,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
890,7 → 920,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
907,7 → 938,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
924,7 → 956,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
937,7 → 970,8
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>kts_sw_ref</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
/funbase_ip_library/trunk/TUT/ip.hwp.storage/ddrx/a2_ddr2_dimm_1GB.comp/2.0/alt_ddr2_a2.comp.1.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 10:31:36 ke marras 9 2011-->
<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<!--Created by Kactus 2 document generator 13:29:29 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.storage</spirit:library>
<spirit:name>a2_ddr2_dimm_1GB</spirit:name>
412,7 → 412,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
425,7 → 425,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
438,7 → 438,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
455,7 → 455,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
468,7 → 468,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
485,7 → 485,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
502,7 → 502,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
515,7 → 515,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
528,7 → 528,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
545,7 → 545,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
558,7 → 558,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
571,7 → 571,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
584,7 → 584,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
597,7 → 597,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
614,7 → 614,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
631,7 → 631,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
644,7 → 644,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
661,7 → 661,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
678,7 → 678,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
691,7 → 691,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
704,7 → 704,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
721,7 → 721,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
738,7 → 738,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
751,7 → 751,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
768,7 → 768,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
785,7 → 785,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
802,7 → 802,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
819,7 → 819,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
832,7 → 832,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
845,7 → 845,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
858,7 → 858,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
871,7 → 871,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
884,7 → 884,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
897,7 → 897,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
910,7 → 910,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
923,9 → 923,12
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>'1'</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
</spirit:ports>
/funbase_ip_library/trunk/TUT/ip.hwp.communication/ase_mesh1/ase_mesh1_top4/1.0/ase_mesh1_top4.1.0.xml
1,4 → 1,4
<?xml version="1.0" encoding="UTF-8"?>
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 15:21:04 01.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
/funbase_ip_library/trunk/TUT/ip.hwp.communication/hibi/hibi_segment_small/2.0/hibi_segment_small.2.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 13:46:35 ma marras 7 2011-->
<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<!--Created by Kactus 2 document generator 13:23:37 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.communication</spirit:library>
<spirit:name>hibi_segment_small</spirit:name>
481,6 → 481,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
491,6 → 498,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
501,6 → 515,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
511,6 → 532,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
521,6 → 549,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
531,6 → 566,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
541,6 → 583,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
551,6 → 600,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
561,6 → 617,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
571,6 → 634,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
581,6 → 651,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
591,6 → 668,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
601,6 → 685,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
611,6 → 702,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
621,6 → 719,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
631,6 → 736,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
641,6 → 753,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
651,6 → 770,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
661,6 → 787,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
671,6 → 804,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
681,6 → 821,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
691,6 → 838,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
701,6 → 855,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
711,6 → 872,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
721,6 → 889,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
731,6 → 906,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
741,6 → 923,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
751,6 → 940,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
761,6 → 957,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
771,6 → 974,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
781,6 → 991,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
791,6 → 1008,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
801,6 → 1025,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
811,6 → 1042,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
821,6 → 1059,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
831,6 → 1076,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
841,6 → 1093,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
851,6 → 1110,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
861,6 → 1127,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
871,6 → 1144,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
881,6 → 1161,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
891,6 → 1178,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
901,6 → 1195,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
911,6 → 1212,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
921,6 → 1229,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
931,6 → 1246,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
941,6 → 1263,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
951,6 → 1280,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
961,6 → 1297,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
971,6 → 1314,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
981,6 → 1331,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
991,6 → 1348,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1001,6 → 1365,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1011,6 → 1382,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1021,6 → 1399,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1031,6 → 1416,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1041,6 → 1433,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1051,6 → 1450,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1061,6 → 1467,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1071,6 → 1484,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1081,6 → 1501,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1091,6 → 1518,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1101,6 → 1535,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1111,6 → 1552,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1121,6 → 1569,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1131,6 → 1586,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1141,6 → 1603,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1151,6 → 1620,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1161,6 → 1637,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1171,6 → 1654,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1181,6 → 1671,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1191,6 → 1688,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1201,6 → 1705,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1211,6 → 1722,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1221,6 → 1739,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1231,6 → 1756,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1241,6 → 1773,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1251,6 → 1790,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1261,6 → 1807,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1271,6 → 1824,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1281,6 → 1841,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1291,6 → 1858,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1301,6 → 1875,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1311,6 → 1892,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1321,6 → 1909,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1331,6 → 1926,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1341,6 → 1943,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1351,6 → 1960,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1361,6 → 1977,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1371,6 → 1994,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1381,6 → 2011,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1391,6 → 2028,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1401,6 → 2045,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1411,6 → 2062,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1421,6 → 2079,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1431,6 → 2096,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1441,6 → 2113,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1451,6 → 2130,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1461,6 → 2147,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1471,6 → 2164,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1481,6 → 2181,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1491,6 → 2198,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1501,6 → 2215,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1511,6 → 2232,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1521,6 → 2249,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1531,6 → 2266,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1541,6 → 2283,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1551,6 → 2300,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1561,6 → 2317,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1571,6 → 2334,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1581,6 → 2351,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1591,6 → 2368,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1601,6 → 2385,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1611,6 → 2402,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1621,6 → 2419,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1631,6 → 2436,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1641,6 → 2453,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1651,6 → 2470,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1661,6 → 2487,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1671,6 → 2504,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
/funbase_ip_library/trunk/TUT/ip.hwp.communication/hibi/hibi_segment_small/3.0/hibi_segment_small.3.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 18:03:06 pe syys 30 2011-->
<spirit:component kts_producthier="Global" kts_reuselevel="Block" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<!--Created by Kactus 2 document generator 13:24:00 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.communication</spirit:library>
<spirit:name>hibi_segment_small</spirit:name>
563,6 → 563,15
</spirit:channel>
</spirit:channels>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>rtl</spirit:name>
<spirit:envIdentifier>vhdl::</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>hdlSources</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>agent_addr_in_17</spirit:name>
572,6 → 581,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
582,6 → 598,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
592,6 → 615,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
602,6 → 632,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
612,6 → 649,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
622,6 → 666,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
632,6 → 683,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
642,6 → 700,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
652,6 → 717,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
662,6 → 734,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
672,6 → 751,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
682,6 → 768,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
692,6 → 785,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
702,6 → 802,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
712,6 → 819,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
722,6 → 836,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
732,6 → 853,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
742,6 → 870,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
752,6 → 887,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
762,6 → 904,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
772,6 → 921,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
782,6 → 938,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
792,6 → 955,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
802,6 → 972,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
812,6 → 989,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
822,6 → 1006,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
832,6 → 1023,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
842,6 → 1040,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
852,6 → 1057,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
862,6 → 1074,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
872,6 → 1091,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
882,6 → 1108,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
892,6 → 1125,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
902,6 → 1142,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
912,6 → 1159,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
922,6 → 1176,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
932,6 → 1193,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
942,6 → 1210,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
952,6 → 1227,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
962,6 → 1244,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
972,6 → 1261,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
982,6 → 1278,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
992,6 → 1295,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1002,6 → 1312,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1012,6 → 1329,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1022,6 → 1346,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1032,6 → 1363,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1042,6 → 1380,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1052,6 → 1397,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1062,6 → 1414,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1072,6 → 1431,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1082,6 → 1448,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1092,6 → 1465,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1102,6 → 1482,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1112,6 → 1499,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1122,6 → 1516,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1132,6 → 1533,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1142,6 → 1550,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1152,6 → 1567,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1162,6 → 1584,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1172,6 → 1601,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1182,6 → 1618,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1192,6 → 1635,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1202,6 → 1652,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1212,6 → 1669,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1222,6 → 1686,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1232,6 → 1703,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1242,6 → 1720,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1252,6 → 1737,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1262,6 → 1754,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1272,6 → 1771,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1282,6 → 1788,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1292,6 → 1805,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1302,6 → 1822,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1312,6 → 1839,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1322,6 → 1856,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1332,6 → 1873,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1342,6 → 1890,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1352,6 → 1907,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1362,6 → 1924,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1372,6 → 1941,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1382,6 → 1958,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1392,6 → 1975,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1402,6 → 1992,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1412,6 → 2009,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1422,6 → 2026,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1432,6 → 2043,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1442,6 → 2060,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1452,6 → 2077,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1462,6 → 2094,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1472,6 → 2111,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1482,6 → 2128,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1492,6 → 2145,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1502,6 → 2162,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1512,6 → 2179,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1522,6 → 2196,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1532,6 → 2213,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1542,6 → 2230,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1552,6 → 2247,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1562,6 → 2264,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1572,6 → 2281,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1582,6 → 2298,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1592,6 → 2315,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1602,6 → 2332,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1612,6 → 2349,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1622,6 → 2366,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1632,6 → 2383,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1642,6 → 2400,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1652,6 → 2417,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1662,6 → 2434,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1672,6 → 2451,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1682,6 → 2468,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1692,6 → 2485,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1702,6 → 2502,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1712,6 → 2519,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1722,6 → 2536,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1732,6 → 2553,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1742,6 → 2570,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1752,6 → 2587,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1762,6 → 2604,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
/funbase_ip_library/trunk/TUT/ip.hwp.communication/hibi/hibi_segment_large/2.0/hibi_segment_large.2.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 14:24:28 to marras 17 2011-->
<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<!--Created by Kactus 2 document generator 13:22:59 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.communication</spirit:library>
<spirit:name>hibi_segment_large</spirit:name>
2943,6 → 2943,15
</spirit:channel>
</spirit:channels>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>rtl</spirit:name>
<spirit:envIdentifier>vhdl::</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>hdlSources</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>agent_addr_in_17</spirit:name>
2952,6 → 2961,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2962,6 → 2978,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2972,6 → 2995,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2982,6 → 3012,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2992,6 → 3029,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3002,6 → 3046,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3012,6 → 3063,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3022,6 → 3080,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3032,6 → 3097,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3042,6 → 3114,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3052,6 → 3131,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3062,6 → 3148,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3072,6 → 3165,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3082,6 → 3182,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3092,6 → 3199,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3102,6 → 3216,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3112,6 → 3233,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3122,6 → 3250,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3132,6 → 3267,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3142,6 → 3284,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3152,6 → 3301,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3162,6 → 3318,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3172,6 → 3335,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3182,6 → 3352,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3192,6 → 3369,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3202,6 → 3386,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3212,6 → 3403,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3222,6 → 3420,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3232,6 → 3437,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3242,6 → 3454,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3252,6 → 3471,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3262,6 → 3488,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3272,6 → 3505,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3282,6 → 3522,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3292,6 → 3539,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3302,6 → 3556,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3312,6 → 3573,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3322,6 → 3590,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3332,6 → 3607,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3342,6 → 3624,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3352,6 → 3641,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3362,6 → 3658,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3372,6 → 3675,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3382,6 → 3692,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3392,6 → 3709,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3402,6 → 3726,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3412,6 → 3743,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3422,6 → 3760,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3432,6 → 3777,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3442,6 → 3794,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3452,6 → 3811,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3462,6 → 3828,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3472,6 → 3845,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3482,6 → 3862,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3492,6 → 3879,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3502,6 → 3896,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3512,6 → 3913,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3522,6 → 3930,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3532,6 → 3947,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3542,6 → 3964,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3552,6 → 3981,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3562,6 → 3998,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3572,6 → 4015,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3582,6 → 4032,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3592,6 → 4049,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3602,6 → 4066,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3612,6 → 4083,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3622,6 → 4100,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3632,6 → 4117,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3642,6 → 4134,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3652,6 → 4151,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3662,6 → 4168,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3672,6 → 4185,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3682,6 → 4202,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3692,6 → 4219,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3702,6 → 4236,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3712,6 → 4253,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3722,6 → 4270,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3732,6 → 4287,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3742,6 → 4304,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3752,6 → 4321,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3762,6 → 4338,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3772,6 → 4355,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3782,6 → 4372,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3792,6 → 4389,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3802,6 → 4406,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3812,6 → 4423,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3822,6 → 4440,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3832,6 → 4457,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3842,6 → 4474,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3852,6 → 4491,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3862,6 → 4508,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3872,6 → 4525,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3882,6 → 4542,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3892,6 → 4559,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3902,6 → 4576,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3912,6 → 4593,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3922,6 → 4610,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3932,6 → 4627,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3942,6 → 4644,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3952,6 → 4661,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3962,6 → 4678,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3972,6 → 4695,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3982,6 → 4712,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
3992,6 → 4729,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4002,6 → 4746,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4012,6 → 4763,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4022,6 → 4780,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4032,6 → 4797,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4042,6 → 4814,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4052,6 → 4831,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4062,6 → 4848,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4072,6 → 4865,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4082,6 → 4882,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4092,6 → 4899,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4102,6 → 4916,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4112,6 → 4933,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4122,6 → 4950,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4132,6 → 4967,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4142,6 → 4984,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4152,6 → 5001,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4162,6 → 5018,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4172,6 → 5035,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4182,6 → 5052,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4192,6 → 5069,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4202,6 → 5086,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4212,6 → 5103,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4222,6 → 5120,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4232,6 → 5137,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4242,6 → 5154,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4252,6 → 5171,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4262,6 → 5188,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4272,6 → 5205,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4282,6 → 5222,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4292,6 → 5239,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4302,6 → 5256,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4312,6 → 5273,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4322,6 → 5290,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4332,6 → 5307,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4342,6 → 5324,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4352,6 → 5341,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4362,6 → 5358,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4372,6 → 5375,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4382,6 → 5392,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4392,6 → 5409,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4402,6 → 5426,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4412,6 → 5443,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4422,6 → 5460,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4432,6 → 5477,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4442,6 → 5494,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4452,6 → 5511,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4462,6 → 5528,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4472,6 → 5545,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4482,6 → 5562,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4492,6 → 5579,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4502,6 → 5596,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4512,6 → 5613,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4522,6 → 5630,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4532,6 → 5647,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4542,6 → 5664,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4552,6 → 5681,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4562,6 → 5698,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4572,6 → 5715,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4582,6 → 5732,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4592,6 → 5749,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4602,6 → 5766,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4612,6 → 5783,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4622,6 → 5800,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4632,6 → 5817,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4642,6 → 5834,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4652,6 → 5851,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4662,6 → 5868,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4672,6 → 5885,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4682,6 → 5902,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4692,6 → 5919,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4702,6 → 5936,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4712,6 → 5953,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4722,6 → 5970,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4732,6 → 5987,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4742,6 → 6004,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4752,6 → 6021,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4762,6 → 6038,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4772,6 → 6055,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4782,6 → 6072,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4792,6 → 6089,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4802,6 → 6106,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4812,6 → 6123,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4822,6 → 6140,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4832,6 → 6157,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4842,6 → 6174,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4852,6 → 6191,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4862,6 → 6208,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4872,6 → 6225,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4882,6 → 6242,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4892,6 → 6259,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4902,6 → 6276,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4912,6 → 6293,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4922,6 → 6310,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4932,6 → 6327,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4942,6 → 6344,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4952,6 → 6361,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4962,6 → 6378,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4972,6 → 6395,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4982,6 → 6412,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
4992,6 → 6429,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
5002,6 → 6446,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
5012,6 → 6463,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
5022,6 → 6480,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
5032,6 → 6497,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
5042,6 → 6514,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
5052,6 → 6531,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
5062,6 → 6548,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
5072,6 → 6565,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
5082,6 → 6582,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
5092,6 → 6599,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
/funbase_ip_library/trunk/TUT/ip.hwp.communication/hibi/hibi_segment_medium/2.0/hibi_segment_medium.2.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 18:03:20 pe syys 30 2011-->
<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<!--Created by Kactus 2 document generator 13:23:25 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.communication</spirit:library>
<spirit:name>hibi_segment_medium</spirit:name>
1091,6 → 1091,15
</spirit:channel>
</spirit:channels>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>rtl</spirit:name>
<spirit:envIdentifier>vhdl::</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>hdlSources</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>agent_addr_in_17</spirit:name>
1100,6 → 1109,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1110,6 → 1126,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1120,6 → 1143,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1130,6 → 1160,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1140,6 → 1177,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1150,6 → 1194,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1160,6 → 1211,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1170,6 → 1228,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1180,6 → 1245,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1190,6 → 1262,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1200,6 → 1279,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1210,6 → 1296,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1220,6 → 1313,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1230,6 → 1330,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1240,6 → 1347,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1250,6 → 1364,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1260,6 → 1381,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1270,6 → 1398,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1280,6 → 1415,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1290,6 → 1432,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1300,6 → 1449,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1310,6 → 1466,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1320,6 → 1483,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1330,6 → 1500,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1340,6 → 1517,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1350,6 → 1534,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1360,6 → 1551,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1370,6 → 1568,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1380,6 → 1585,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1390,6 → 1602,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1400,6 → 1619,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1410,6 → 1636,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1420,6 → 1653,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1430,6 → 1670,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1440,6 → 1687,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1450,6 → 1704,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1460,6 → 1721,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1470,6 → 1738,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1480,6 → 1755,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1490,6 → 1772,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1500,6 → 1789,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1510,6 → 1806,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1520,6 → 1823,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1530,6 → 1840,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1540,6 → 1857,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1550,6 → 1874,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1560,6 → 1891,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1570,6 → 1908,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1580,6 → 1925,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1590,6 → 1942,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1600,6 → 1959,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1610,6 → 1976,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1620,6 → 1993,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1630,6 → 2010,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1640,6 → 2027,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1650,6 → 2044,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1660,6 → 2061,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1670,6 → 2078,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1680,6 → 2095,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1690,6 → 2112,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1700,6 → 2129,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1710,6 → 2146,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1720,6 → 2163,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1730,6 → 2180,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1740,6 → 2197,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1750,6 → 2214,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1760,6 → 2231,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1770,6 → 2248,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1780,6 → 2265,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1790,6 → 2282,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1800,6 → 2299,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1810,6 → 2316,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1820,6 → 2333,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1830,6 → 2350,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1840,6 → 2367,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1850,6 → 2384,13
<spirit:left>2</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1860,6 → 2401,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1870,6 → 2418,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1880,6 → 2435,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1890,6 → 2452,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1900,6 → 2469,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1910,6 → 2486,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1920,6 → 2503,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1930,6 → 2520,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1940,6 → 2537,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1950,6 → 2554,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1960,6 → 2571,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1970,6 → 2588,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1980,6 → 2605,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
1990,6 → 2622,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2000,6 → 2639,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2010,6 → 2656,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2020,6 → 2673,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2030,6 → 2690,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2040,6 → 2707,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2050,6 → 2724,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2060,6 → 2741,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2070,6 → 2758,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2080,6 → 2775,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2090,6 → 2792,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2100,6 → 2809,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2110,6 → 2826,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2120,6 → 2843,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2130,6 → 2860,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2140,6 → 2877,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2150,6 → 2894,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2160,6 → 2911,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2170,6 → 2928,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2180,6 → 2945,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2190,6 → 2962,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2200,6 → 2979,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2210,6 → 2996,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2220,6 → 3013,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2230,6 → 3030,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2240,6 → 3047,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2250,6 → 3064,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2260,6 → 3081,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2270,6 → 3098,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2280,6 → 3115,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
2290,6 → 3132,13
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
/funbase_ip_library/trunk/TUT/ip.hwp.cpu/nios_ii/nios_ii_a2gx_onchip/1.0/nios_ii_a2gx_onchip.1.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 17:18:26 ti marras 8 2011-->
<spirit:component>
<!--Created by Kactus 2 document generator 13:25:07 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.cpu</spirit:library>
<spirit:name>nios_ii_a2gx_onchip</spirit:name>
116,6 → 116,15
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>rtl</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>hdlSources</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>clk_clk</spirit:name>
125,7 → 134,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
142,7 → 151,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
159,7 → 168,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
172,7 → 181,7
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
/funbase_ip_library/trunk/TUT/ip.hwp.cpu/nios_ii/1.0/nios_ii.1.0.xml
1,6 → 1,6
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 14:46:03 ti marras 8 2011-->
<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<!--Created by Kactus 2 document generator 13:24:37 02.12.2011-->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.cpu</spirit:library>
<spirit:name>nios_ii</spirit:name>
148,11 → 148,24
</spirit:addressSpace>
</spirit:addressSpaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>rtl</spirit:name>
<spirit:envIdentifier>vhdl::</spirit:envIdentifier>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>clk</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
159,6 → 172,13
<spirit:name>hibi_av_in_to_the_hpd</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
165,6 → 185,13
<spirit:name>hibi_av_out_from_the_hpd</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
175,6 → 202,13
<spirit:left>4</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
185,6 → 219,13
<spirit:left>4</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
195,6 → 236,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
205,6 → 253,13
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
211,6 → 266,13
<spirit:name>hibi_empty_in_to_the_hpd</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
217,6 → 279,13
<spirit:name>hibi_full_in_to_the_hpd</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
223,6 → 292,13
<spirit:name>hibi_re_out_from_the_hpd</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
229,6 → 305,13
<spirit:name>hibi_we_out_from_the_hpd</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
235,6 → 318,13
<spirit:name>rst_n</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>

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