Subversion Repositories minsoc

/minsoc/trunk/backend/spartan3a_dsp_kit/configure

/minsoc/trunk/backend/std/configure

/minsoc/trunk/backend/spartan3e_starter_kit/configure

/minsoc/trunk/backend/spartan3e_starter_kit_eth/configure

/minsoc/trunk/sim/bin/minsoc_verilog_files.txt File deleted

minsoc/trunk/sim/bin/minsoc_verilog_files.txt Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: minsoc/trunk/sim/run/generate_bench =================================================================== --- minsoc/trunk/sim/run/generate_bench (revision 84) +++ minsoc/trunk/sim/run/generate_bench (revision 85) @@ -1,2 +1,2 @@ #!/bin/sh -iverilog -c ../bin/minsoc_verilog_files.txt -o minsoc_bench +iverilog -c ../../prj/sim/minsoc.src -o minsoc_bench Index: minsoc/trunk/sim/modelsim/compile_design.bat =================================================================== --- minsoc/trunk/sim/modelsim/compile_design.bat (revision 84) +++ minsoc/trunk/sim/modelsim/compile_design.bat (revision 85) @@ -1,4 +1,4 @@ @echo off -vlog -incr -work minsoc -f ../bin/minsoc_verilog_files.txt +vlog -incr -work minsoc -f ../../prj/sim/minsoc.src echo Finished... -set /p exit=Press ENTER to close this window... \ No newline at end of file +set /p exit=Press ENTER to close this window... Index: minsoc/trunk/sim/modelsim/compile_design.sh =================================================================== --- minsoc/trunk/sim/modelsim/compile_design.sh (revision 84) +++ minsoc/trunk/sim/modelsim/compile_design.sh (revision 85) @@ -1,3 +1,3 @@ #!/bin/bash -vlog -incr -work minsoc -f ../bin/minsoc_verilog_files.txt \ No newline at end of file +vlog -incr -work minsoc -f ../../prj/sim/minsoc.src

/minsoc/trunk/syn/src/uart_top.xst File deleted \ No newline at end of file

/minsoc/trunk/syn/src/adbg_top.xst File deleted \ No newline at end of file

/minsoc/trunk/syn/src/Makefile File deleted

/minsoc/trunk/syn/src/eth_top.xst File deleted \ No newline at end of file

/minsoc/trunk/syn/src/or1200_top.xst File deleted \ No newline at end of file

/minsoc/trunk/syn/src/minsoc_top.xst File deleted \ No newline at end of file

/minsoc/trunk/syn/blackboxes/uart_top.v File deleted

/minsoc/trunk/syn/blackboxes/adbg_top.v File deleted

/minsoc/trunk/syn/blackboxes/eth_top.v File deleted

/minsoc/trunk/syn/blackboxes/or1200_top.v File deleted

/minsoc/trunk/syn/xilinx/Makefile

/minsoc/trunk/syn/buildSupport/eth_top.prj File deleted \ No newline at end of file

/minsoc/trunk/syn/buildSupport/minsoc_top.prj File deleted \ No newline at end of file

/minsoc/trunk/syn/buildSupport/or1200_top.prj File deleted \ No newline at end of file

/minsoc/trunk/syn/buildSupport/uart_top.prj File deleted

/minsoc/trunk/syn/buildSupport/adbg_top.prj File deleted \ No newline at end of file

/minsoc/trunk/prj/scripts/xilinxprj.sh

minsoc/trunk/prj/scripts/xilinxprj.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc/trunk/prj/scripts/xilinxxst.sh =================================================================== --- minsoc/trunk/prj/scripts/xilinxxst.sh (nonexistent) +++ minsoc/trunk/prj/scripts/xilinxxst.sh (revision 85) @@ -0,0 +1,52 @@ +#!/bin/bash + +#system workings +MINSOC_DIR=`pwd`/.. + +PROJECT=$1 +DIR_OUTPUT=$2 +PROJECT_FILE=$3 +TOP_MODULE_NAME=$4 +TOP_MODULE=$5 + +if [ ! -f $PROJECT ] +then + echo "Unexistent project file." + exit 1 +fi + +if [ -z "$DIR_OUTPUT" ] +then + echo "Second argument should be the destintion file for the directory inclusions." + exit 1 +fi + +source $PROJECT + +echo "set -tmpdir "./xst"" >> $DIR_OUTPUT +echo "run" >> $DIR_OUTPUT + +DIR_PATH="-vlgincdir {" + +for dir in "${PROJECT_DIR[@]}" +do + DIR_PATH="$DIR_PATH \"$MINSOC_DIR/$dir\" " +done + +DIR_PATH="$DIR_PATH }" +echo $DIR_PATH >> $DIR_OUTPUT + +echo "-ifn $MINSOC_DIR/prj/${PROJECT_FILE}" >> $DIR_OUTPUT +echo "-ifmt Verilog" >> $DIR_OUTPUT +echo "-ofn ${TOP_MODULE_NAME}" >> $DIR_OUTPUT +echo "-ofmt NGC" >> $DIR_OUTPUT +echo "-p DEVICE_PART" >> $DIR_OUTPUT +echo "-top ${TOP_MODULE_NAME}" >> $DIR_OUTPUT +echo "-opt_mode Speed" >> $DIR_OUTPUT +echo "-opt_level 1" >> $DIR_OUTPUT +if [ -n "$TOP_MODULE" ] +then + echo "-iobuf yes" >> $DIR_OUTPUT +else + echo "-iobuf no" >> $DIR_OUTPUT +fi

minsoc/trunk/prj/scripts/xilinxxst.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc/trunk/prj/scripts/simprj.sh =================================================================== --- minsoc/trunk/prj/scripts/simprj.sh (nonexistent) +++ minsoc/trunk/prj/scripts/simprj.sh (revision 85) @@ -0,0 +1,46 @@ +#!/bin/bash + +#system workings +MINSOC_DIR=`pwd`/.. + +PROJECT=$1 +OUTPUT=$2 + +if [ ! -f $PROJECT ] +then + echo "Unexistent project file." + exit 1 +fi + +if [ -z "$OUTPUT" ] +then + echo "Second argument should be the destintion file for the file and directory inclusions." + exit 1 +fi + +source $PROJECT + +for dir in "${PROJECT_DIR[@]}" +do + echo "+incdir+$MINSOC_DIR/$dir" >> $OUTPUT +done + +for file in "${PROJECT_SRC[@]}" +do + FOUND=0 + + for dir in "${PROJECT_DIR[@]}" + do + if [ -f $MINSOC_DIR/$dir/$file ] + then + echo "$MINSOC_DIR/$dir/$file" >> $OUTPUT + FOUND=1 + fi + done + + if [ $FOUND != 1 ] + then + echo "FILE NOT FOUND" + exit 1 + fi +done

minsoc/trunk/prj/scripts/simprj.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc/trunk/prj/src/or1200_top.prj =================================================================== --- minsoc/trunk/prj/src/or1200_top.prj (nonexistent) +++ minsoc/trunk/prj/src/or1200_top.prj (revision 85) @@ -0,0 +1,64 @@ +PROJECT_DIR=rtl/verilog/or1200/rtl/verilog +PROJECT_SRC=(or1200_spram_512x20.v +or1200_spram_64x24.v +or1200_du.v +or1200_spram_2048x32_bw.v +or1200_rf.v +or1200_alu.v +or1200_dmmu_top.v +or1200_lsu.v +or1200_spram_1024x32.v +or1200_dc_top.v +or1200_cpu.v +or1200_gmultp2_32x32.v +or1200_immu_top.v +or1200_dpram_256x32.v +or1200_tt.v +or1200_iwb_biu.v +or1200_rfram_generic.v +or1200_dc_tag.v +or1200_spram_2048x8.v +or1200_immu_tlb.v +or1200_ic_tag.v +or1200_spram_64x14.v +or1200_spram_32x24.v +or1200_dpram_32x32.v +or1200_xcv_ram32x8d.v +or1200_spram_1024x8.v +or1200_mem2reg.v +or1200_pm.v +or1200_spram_256x21.v +or1200_operandmuxes.v +or1200_pic.v +or1200_cfgr.v +or1200_if.v +or1200_qmem_top.v +or1200_genpc.v +or1200_defines.v +or1200_wbmux.v +or1200_ic_ram.v +or1200_dmmu_tlb.v +or1200_sb_fifo.v +or1200_sprs.v +or1200_tpram_32x32.v +or1200_ctrl.v +or1200_sb.v +or1200_mult_mac.v +or1200_ic_fsm.v +or1200_amultp2_32x32.v +or1200_reg2mem.v +or1200_spram_2048x32.v +or1200_except.v +or1200_top.v +or1200_ic_top.v +or1200_dc_ram.v +or1200_spram_1024x32_bw.v +or1200_freeze.v +or1200_spram_128x32.v +or1200_dc_fsm.v +or1200_wb_biu.v +or1200_spram_64x22.v +or1200_fpu.v +or1200_spram.v +or1200_spram_32_bw.v +or1200_dpram.v) Index: minsoc/trunk/prj/src/jtag_top.prj =================================================================== --- minsoc/trunk/prj/src/jtag_top.prj (nonexistent) +++ minsoc/trunk/prj/src/jtag_top.prj (revision 85) @@ -0,0 +1,3 @@ +PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog +PROJECT_SRC=(tap_top.v +tap_defines.v) Index: minsoc/trunk/prj/src/minsoc_top.prj =================================================================== --- minsoc/trunk/prj/src/minsoc_top.prj (nonexistent) +++ minsoc/trunk/prj/src/minsoc_top.prj (revision 85) @@ -0,0 +1,18 @@ +PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog rtl/verilog/minsoc_startup) +PROJECT_SRC=(minsoc_defines.v +minsoc_bench_defines.v +minsoc_bench.v +minsoc_memory_model.v +dbg_comm_vpi.v +fpga_memory_primitives.v +timescale.v +minsoc_top.v +spi_top.v +spi_defines.v +spi_shift.v +spi_clgen.v +OR1K_startup_generic.v +minsoc_tc_top.v +minsoc_onchip_ram.v +minsoc_clock_manager.v +minsoc_onchip_ram_top.v) Index: minsoc/trunk/prj/src/uart_top.prj =================================================================== --- minsoc/trunk/prj/src/uart_top.prj (nonexistent) +++ minsoc/trunk/prj/src/uart_top.prj (revision 85) @@ -0,0 +1,12 @@ +PROJECT_DIR=rtl/verilog/uart16550/rtl/verilog +PROJECT_SRC=(uart_top.v +uart_sync_flops.v +uart_transmitter.v +uart_debug_if.v +uart_wb.v +uart_receiver.v +uart_tfifo.v +uart_regs.v +uart_rfifo.v +uart_defines.v +raminfr.v) Index: minsoc/trunk/prj/src/adbg_top.prj =================================================================== --- minsoc/trunk/prj/src/adbg_top.prj (nonexistent) +++ minsoc/trunk/prj/src/adbg_top.prj (revision 85) @@ -0,0 +1,11 @@ +PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog +PROJECT_SRC=(adbg_wb_biu.v +adbg_wb_module.v +adbg_or1k_module.v +adbg_wb_defines.v +adbg_defines.v +adbg_crc32.v +adbg_or1k_biu.v +adbg_or1k_defines.v +adbg_or1k_status_reg.v +adbg_top.v) Index: minsoc/trunk/prj/src/ethmac.prj =================================================================== --- minsoc/trunk/prj/src/ethmac.prj (nonexistent) +++ minsoc/trunk/prj/src/ethmac.prj (revision 85) @@ -0,0 +1,26 @@ +PROJECT_DIR=rtl/verilog/ethmac/rtl/verilog +PROJECT_SRC=(eth_cop.v +eth_registers.v +eth_rxethmac.v +eth_miim.v +ethmac.v +eth_rxaddrcheck.v +eth_outputcontrol.v +eth_rxstatem.v +eth_txethmac.v +eth_wishbone.v +eth_maccontrol.v +eth_txstatem.v +ethmac_defines.v +eth_spram_256x32.v +eth_shiftreg.v +eth_clockgen.v +eth_crc.v +eth_rxcounters.v +eth_macstatus.v +eth_random.v +eth_register.v +eth_fifo.v +eth_receivecontrol.v +eth_transmitcontrol.v +eth_txcounters.v) Index: minsoc/trunk/prj/src/blackboxes/ethmac.v =================================================================== --- minsoc/trunk/prj/src/blackboxes/ethmac.v (nonexistent) +++ minsoc/trunk/prj/src/blackboxes/ethmac.v (revision 85) @@ -0,0 +1,113 @@ + + +`include "ethmac_defines.v" + +module ethmac +( + // WISHBONE common + wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, + + // WISHBONE slave + wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o, + + // WISHBONE master + m_wb_adr_o, m_wb_sel_o, m_wb_we_o, + m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o, + m_wb_stb_o, m_wb_ack_i, m_wb_err_i, + +`ifdef ETH_WISHBONE_B3 + m_wb_cti_o, m_wb_bte_o, +`endif + + //TX + mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o, + + //RX + mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i, + + // MIIM + mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o, + + int_o + + // Bist +`ifdef ETH_BIST + , + // debug chain signals + mbist_si_i, // bist scan serial in + mbist_so_o, // bist scan serial out + mbist_ctrl_i // bist chain shift control +`endif + +); + + +parameter Tp = 1; + + +// WISHBONE common +input wb_clk_i; // WISHBONE clock +input wb_rst_i; // WISHBONE reset +input [31:0] wb_dat_i; // WISHBONE data input +output [31:0] wb_dat_o; // WISHBONE data output +output wb_err_o; // WISHBONE error output + +// WISHBONE slave +input [11:2] wb_adr_i; // WISHBONE address input +input [3:0] wb_sel_i; // WISHBONE byte select input +input wb_we_i; // WISHBONE write enable input +input wb_cyc_i; // WISHBONE cycle input +input wb_stb_i; // WISHBONE strobe input +output wb_ack_o; // WISHBONE acknowledge output + +// WISHBONE master +output [31:0] m_wb_adr_o; +output [3:0] m_wb_sel_o; +output m_wb_we_o; +input [31:0] m_wb_dat_i; +output [31:0] m_wb_dat_o; +output m_wb_cyc_o; +output m_wb_stb_o; +input m_wb_ack_i; +input m_wb_err_i; + +wire [29:0] m_wb_adr_tmp; + +`ifdef ETH_WISHBONE_B3 +output [2:0] m_wb_cti_o; // Cycle Type Identifier +output [1:0] m_wb_bte_o; // Burst Type Extension +`endif + +// Tx +input mtx_clk_pad_i; // Transmit clock (from PHY) +output [3:0] mtxd_pad_o; // Transmit nibble (to PHY) +output mtxen_pad_o; // Transmit enable (to PHY) +output mtxerr_pad_o; // Transmit error (to PHY) + +// Rx +input mrx_clk_pad_i; // Receive clock (from PHY) +input [3:0] mrxd_pad_i; // Receive nibble (from PHY) +input mrxdv_pad_i; // Receive data valid (from PHY) +input mrxerr_pad_i; // Receive data error (from PHY) + +// Common Tx and Rx +input mcoll_pad_i; // Collision (from PHY) +input mcrs_pad_i; // Carrier sense (from PHY) + +// MII Management interface +input md_pad_i; // MII data input (from I/O cell) +output mdc_pad_o; // MII Management data clock (to PHY) +output md_pad_o; // MII data output (to I/O cell) +output md_padoe_o; // MII data output enable (to I/O cell) + +output int_o; // Interrupt output + +// Bist +`ifdef ETH_BIST +input mbist_si_i; // bist scan serial in +output mbist_so_o; // bist scan serial out +input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control +`endif + + +endmodule Index: minsoc/trunk/prj/src/blackboxes/uart_top.v =================================================================== --- minsoc/trunk/prj/src/blackboxes/uart_top.v (nonexistent) +++ minsoc/trunk/prj/src/blackboxes/uart_top.v (revision 85) @@ -0,0 +1,58 @@ + + +`include "uart_defines.v" + +module uart_top ( + wb_clk_i, + + // Wishbone signals + wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i, + int_o, // interrupt request + + // UART signals + // serial input/output + stx_pad_o, srx_pad_i, + + // modem signals + rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i +`ifdef UART_HAS_BAUDRATE_OUTPUT + , baud_o +`endif + ); + +parameter uart_data_width = `UART_DATA_WIDTH; +parameter uart_addr_width = `UART_ADDR_WIDTH; + +input wb_clk_i; + +// WISHBONE interface +input wb_rst_i; +input [uart_addr_width-1:0] wb_adr_i; +input [uart_data_width-1:0] wb_dat_i; +output [uart_data_width-1:0] wb_dat_o; +input wb_we_i; +input wb_stb_i; +input wb_cyc_i; +input [3:0] wb_sel_i; +output wb_ack_o; +output int_o; + +// UART signals +input srx_pad_i; +output stx_pad_o; +output rts_pad_o; +input cts_pad_i; +output dtr_pad_o; +input dsr_pad_i; +input ri_pad_i; +input dcd_pad_i; + +// optional baudrate output +`ifdef UART_HAS_BAUDRATE_OUTPUT +output baud_o; +`endif + + +endmodule + + Index: minsoc/trunk/prj/src/blackboxes/adbg_top.v =================================================================== --- minsoc/trunk/prj/src/blackboxes/adbg_top.v (nonexistent) +++ minsoc/trunk/prj/src/blackboxes/adbg_top.v (revision 85) @@ -0,0 +1,180 @@ + + +`include "adbg_defines.v" + +module adbg_top( + // JTAG signals + tck_i, + tdi_i, + tdo_o, + rst_i, + + + // TAP states + shift_dr_i, + pause_dr_i, + update_dr_i, + capture_dr_i, + + // Instructions + debug_select_i + + + `ifdef DBG_WISHBONE_SUPPORTED + // WISHBONE common signals + , + wb_clk_i, + wb_rst_i, + + // WISHBONE master interface + wb_adr_o, + wb_dat_o, + wb_dat_i, + wb_cyc_o, + wb_stb_o, + wb_sel_o, + wb_we_o, + wb_ack_i, + wb_cab_o, + wb_err_i, + wb_cti_o, + wb_bte_o + `endif + + `ifdef DBG_CPU0_SUPPORTED + // CPU signals + , + cpu0_clk_i, + cpu0_addr_o, + cpu0_data_i, + cpu0_data_o, + cpu0_bp_i, + cpu0_stall_o, + cpu0_stb_o, + cpu0_we_o, + cpu0_ack_i, + cpu0_rst_o + `endif + + `ifdef DBG_CPU1_SUPPORTED + // CPU signals + , + cpu1_clk_i, + cpu1_addr_o, + cpu1_data_i, + cpu1_data_o, + cpu1_bp_i, + cpu1_stall_o, + cpu1_stb_o, + cpu1_we_o, + cpu1_ack_i, + cpu1_rst_o + `endif + + `ifdef DBG_JSP_SUPPORTED + , + `ifndef DBG_WISHBONE_SUPPORTED + wb_clk_i, + wb_rst_i, + `endif + + // WISHBONE target interface + wb_jsp_adr_i, + wb_jsp_dat_o, + wb_jsp_dat_i, + wb_jsp_cyc_i, + wb_jsp_stb_i, + wb_jsp_sel_i, + wb_jsp_we_i, + wb_jsp_ack_o, + wb_jsp_cab_i, + wb_jsp_err_o, + wb_jsp_cti_i, + wb_jsp_bte_i, + int_o + `endif + + ); + + + // JTAG signals + input tck_i; + input tdi_i; + output tdo_o; + input rst_i; + + // TAP states + input shift_dr_i; + input pause_dr_i; + input update_dr_i; + input capture_dr_i; + + // Module select from TAP + input debug_select_i; + +`ifdef DBG_WISHBONE_SUPPORTED + input wb_clk_i; + input wb_rst_i; + output [31:0] wb_adr_o; + output [31:0] wb_dat_o; + input [31:0] wb_dat_i; + output wb_cyc_o; + output wb_stb_o; + output [3:0] wb_sel_o; + output wb_we_o; + input wb_ack_i; + output wb_cab_o; + input wb_err_i; + output [2:0] wb_cti_o; + output [1:0] wb_bte_o; +`endif + +`ifdef DBG_CPU0_SUPPORTED + // CPU signals + input cpu0_clk_i; + output [31:0] cpu0_addr_o; + input [31:0] cpu0_data_i; + output [31:0] cpu0_data_o; + input cpu0_bp_i; + output cpu0_stall_o; + output cpu0_stb_o; + output cpu0_we_o; + input cpu0_ack_i; + output cpu0_rst_o; +`endif + +`ifdef DBG_CPU1_SUPPORTED + input cpu1_clk_i; + output [31:0] cpu1_addr_o; + input [31:0] cpu1_data_i; + output [31:0] cpu1_data_o; + input cpu1_bp_i; + output cpu1_stall_o; + output cpu1_stb_o; + output cpu1_we_o; + input cpu1_ack_i; + output cpu1_rst_o; +`endif + +`ifdef DBG_JSP_SUPPORTED + `ifndef DBG_WISHBONE_SUPPORTED + input wb_clk_i; + input wb_rst_i; + `endif + input [31:0] wb_jsp_adr_i; + output [31:0] wb_jsp_dat_o; + input [31:0] wb_jsp_dat_i; + input wb_jsp_cyc_i; + input wb_jsp_stb_i; + input [3:0] wb_jsp_sel_i; + input wb_jsp_we_i; + output wb_jsp_ack_o; + input wb_jsp_cab_i; + output wb_jsp_err_o; + input [2:0] wb_jsp_cti_i; + input [1:0] wb_jsp_bte_i; + output int_o; +`endif + + +endmodule Index: minsoc/trunk/prj/src/blackboxes/or1200_top.v =================================================================== --- minsoc/trunk/prj/src/blackboxes/or1200_top.v (nonexistent) +++ minsoc/trunk/prj/src/blackboxes/or1200_top.v (revision 85) @@ -0,0 +1,152 @@ + + +`include "or1200_defines.v" + +module or1200_top( + // System + clk_i, rst_i, pic_ints_i, clmode_i, + + // Instruction WISHBONE INTERFACE + iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i, + iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o, +`ifdef OR1200_WB_CAB + iwb_cab_o, +`endif +`ifdef OR1200_WB_B3 + iwb_cti_o, iwb_bte_o, +`endif + // Data WISHBONE INTERFACE + dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i, + dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o, +`ifdef OR1200_WB_CAB + dwb_cab_o, +`endif +`ifdef OR1200_WB_B3 + dwb_cti_o, dwb_bte_o, +`endif + + // External Debug Interface + dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, + dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o, + +`ifdef OR1200_BIST + // RAM BIST + mbist_si_i, mbist_so_o, mbist_ctrl_i, +`endif + // Power Management + pm_cpustall_i, + pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o, + pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o + +,sig_tick + +); + +parameter dw = `OR1200_OPERAND_WIDTH; +parameter aw = `OR1200_OPERAND_WIDTH; +parameter ppic_ints = `OR1200_PIC_INTS; + +// +// I/O +// + +// +// System +// +input clk_i; +input rst_i; +input [1:0] clmode_i; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4 +input [ppic_ints-1:0] pic_ints_i; + +// +// Instruction WISHBONE interface +// +input iwb_clk_i; // clock input +input iwb_rst_i; // reset input +input iwb_ack_i; // normal termination +input iwb_err_i; // termination w/ error +input iwb_rty_i; // termination w/ retry +input [dw-1:0] iwb_dat_i; // input data bus +output iwb_cyc_o; // cycle valid output +output [aw-1:0] iwb_adr_o; // address bus outputs +output iwb_stb_o; // strobe output +output iwb_we_o; // indicates write transfer +output [3:0] iwb_sel_o; // byte select outputs +output [dw-1:0] iwb_dat_o; // output data bus +`ifdef OR1200_WB_CAB +output iwb_cab_o; // indicates consecutive address burst +`endif +`ifdef OR1200_WB_B3 +output [2:0] iwb_cti_o; // cycle type identifier +output [1:0] iwb_bte_o; // burst type extension +`endif + +// +// Data WISHBONE interface +// +input dwb_clk_i; // clock input +input dwb_rst_i; // reset input +input dwb_ack_i; // normal termination +input dwb_err_i; // termination w/ error +input dwb_rty_i; // termination w/ retry +input [dw-1:0] dwb_dat_i; // input data bus +output dwb_cyc_o; // cycle valid output +output [aw-1:0] dwb_adr_o; // address bus outputs +output dwb_stb_o; // strobe output +output dwb_we_o; // indicates write transfer +output [3:0] dwb_sel_o; // byte select outputs +output [dw-1:0] dwb_dat_o; // output data bus +`ifdef OR1200_WB_CAB +output dwb_cab_o; // indicates consecutive address burst +`endif +`ifdef OR1200_WB_B3 +output [2:0] dwb_cti_o; // cycle type identifier +output [1:0] dwb_bte_o; // burst type extension +`endif + +// +// External Debug Interface +// +input dbg_stall_i; // External Stall Input +input dbg_ewt_i; // External Watchpoint Trigger Input +output [3:0] dbg_lss_o; // External Load/Store Unit Status +output [1:0] dbg_is_o; // External Insn Fetch Status +output [10:0] dbg_wp_o; // Watchpoints Outputs +output dbg_bp_o; // Breakpoint Output +input dbg_stb_i; // External Address/Data Strobe +input dbg_we_i; // External Write Enable +input [aw-1:0] dbg_adr_i; // External Address Input +input [dw-1:0] dbg_dat_i; // External Data Input +output [dw-1:0] dbg_dat_o; // External Data Output +output dbg_ack_o; // External Data Acknowledge (not WB compatible) + +`ifdef OR1200_BIST +// +// RAM BIST +// +input mbist_si_i; +input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; +output mbist_so_o; +`endif + +// +// Power Management +// +input pm_cpustall_i; +output [3:0] pm_clksd_o; +output pm_dc_gate_o; +output pm_ic_gate_o; +output pm_dmmu_gate_o; +output pm_immu_gate_o; +output pm_tt_gate_o; +output pm_cpu_gate_o; +output pm_wakeup_o; +output pm_lvolt_o; + +// +// CPU and TT +// +output sig_tick; // jb + + +endmodule Index: minsoc/trunk/prj/sim/minsoc_top.src =================================================================== --- minsoc/trunk/prj/sim/minsoc_top.src (nonexistent) +++ minsoc/trunk/prj/sim/minsoc_top.src (revision 85) @@ -0,0 +1,23 @@ ++incdir+/home/raul/or1k/minsoc/prj/../backend ++incdir+/home/raul/or1k/minsoc/prj/../bench/verilog ++incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/vpi ++incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib ++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog ++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup +/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v +/home/raul/or1k/minsoc/prj/../backend/minsoc_bench_defines.v +/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_bench.v +/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_memory_model.v +/home/raul/or1k/minsoc/prj/../bench/verilog/vpi/dbg_comm_vpi.v +/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib/fpga_memory_primitives.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_shift.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_clgen.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/OR1K_startup_generic.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v Index: minsoc/trunk/prj/sim/uart_top.src =================================================================== --- minsoc/trunk/prj/sim/uart_top.src (nonexistent) +++ minsoc/trunk/prj/sim/uart_top.src (revision 85) @@ -0,0 +1,12 @@ ++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_wb.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_regs.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_defines.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/raminfr.v Index: minsoc/trunk/prj/sim/adbg_top.src =================================================================== --- minsoc/trunk/prj/sim/adbg_top.src (nonexistent) +++ minsoc/trunk/prj/sim/adbg_top.src (revision 85) @@ -0,0 +1,11 @@ ++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v Index: minsoc/trunk/prj/sim/ethmac.src =================================================================== --- minsoc/trunk/prj/sim/ethmac.src (nonexistent) +++ minsoc/trunk/prj/sim/ethmac.src (revision 85) @@ -0,0 +1,26 @@ ++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_cop.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_registers.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_miim.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac_defines.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_crc.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_random.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_register.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v Index: minsoc/trunk/prj/sim/or1200_top.src =================================================================== --- minsoc/trunk/prj/sim/or1200_top.src (nonexistent) +++ minsoc/trunk/prj/sim/or1200_top.src (revision 85) @@ -0,0 +1,64 @@ ++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_du.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rf.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_alu.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tt.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pm.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pic.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_if.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_defines.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_except.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v Index: minsoc/trunk/prj/sim/jtag_top.src =================================================================== --- minsoc/trunk/prj/sim/jtag_top.src (nonexistent) +++ minsoc/trunk/prj/sim/jtag_top.src (revision 85) @@ -0,0 +1,3 @@ ++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v Index: minsoc/trunk/prj/sim/minsoc.src =================================================================== --- minsoc/trunk/prj/sim/minsoc.src (nonexistent) +++ minsoc/trunk/prj/sim/minsoc.src (revision 85) @@ -0,0 +1,139 @@ ++incdir+/home/raul/or1k/minsoc/prj/../backend ++incdir+/home/raul/or1k/minsoc/prj/../bench/verilog ++incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/vpi ++incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib ++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog ++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup +/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v +/home/raul/or1k/minsoc/prj/../backend/minsoc_bench_defines.v +/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_bench.v +/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_memory_model.v +/home/raul/or1k/minsoc/prj/../bench/verilog/vpi/dbg_comm_vpi.v +/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib/fpga_memory_primitives.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_shift.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_clgen.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/OR1K_startup_generic.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v ++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_du.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rf.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_alu.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tt.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pm.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pic.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_if.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_defines.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_except.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v ++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v ++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v ++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_top.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_wb.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_regs.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_defines.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/raminfr.v ++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_cop.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_registers.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_miim.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac_defines.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_crc.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_random.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_register.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v +/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v Index: minsoc/trunk/prj/xilinx/or1200_top.prj =================================================================== --- minsoc/trunk/prj/xilinx/or1200_top.prj (nonexistent) +++ minsoc/trunk/prj/xilinx/or1200_top.prj (revision 85) @@ -0,0 +1,63 @@ +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_du.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rf.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_alu.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tt.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pm.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pic.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_if.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_defines.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_except.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_top.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v" Index: minsoc/trunk/prj/xilinx/jtag_top.prj =================================================================== --- minsoc/trunk/prj/xilinx/jtag_top.prj (nonexistent) +++ minsoc/trunk/prj/xilinx/jtag_top.prj (revision 85) @@ -0,0 +1,2 @@ +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v" Index: minsoc/trunk/prj/xilinx/or1200_top.xst =================================================================== --- minsoc/trunk/prj/xilinx/or1200_top.xst (nonexistent) +++ minsoc/trunk/prj/xilinx/or1200_top.xst (revision 85) @@ -0,0 +1,12 @@ +set -tmpdir ./xst +run +-vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog" } +-ifn /home/raul/or1k/minsoc/prj/../prj/or1200_top.prj +-ifmt Verilog +-ofn or1200_top +-ofmt NGC +-p DEVICE_PART +-top or1200_top +-opt_mode Speed +-opt_level 1 +-iobuf no Index: minsoc/trunk/prj/xilinx/jtag_top.xst =================================================================== --- minsoc/trunk/prj/xilinx/jtag_top.xst (nonexistent) +++ minsoc/trunk/prj/xilinx/jtag_top.xst (revision 85) @@ -0,0 +1,12 @@ +set -tmpdir ./xst +run +-vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog" } +-ifn /home/raul/or1k/minsoc/prj/../prj/jtag_top.prj +-ifmt Verilog +-ofn jtag_top +-ofmt NGC +-p DEVICE_PART +-top jtag_top +-opt_mode Speed +-opt_level 1 +-iobuf no Index: minsoc/trunk/prj/xilinx/minsoc_top.prj =================================================================== --- minsoc/trunk/prj/xilinx/minsoc_top.prj (nonexistent) +++ minsoc/trunk/prj/xilinx/minsoc_top.prj (revision 85) @@ -0,0 +1,21 @@ +`include "/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v" +`include "/home/raul/or1k/minsoc/prj/../backend/minsoc_bench_defines.v" +`include "/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_bench.v" +`include "/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_memory_model.v" +`include "/home/raul/or1k/minsoc/prj/../bench/verilog/vpi/dbg_comm_vpi.v" +`include "/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib/fpga_memory_primitives.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_top.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_top.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_shift.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_clgen.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/OR1K_startup_generic.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v" +`include "/home/raul/or1k/minsoc/prj/src/blackboxes/adbg_top.v" +`include "/home/raul/or1k/minsoc/prj/src/blackboxes/ethmac.v" +`include "/home/raul/or1k/minsoc/prj/src/blackboxes/or1200_top.v" +`include "/home/raul/or1k/minsoc/prj/src/blackboxes/uart_top.v" Index: minsoc/trunk/prj/xilinx/minsoc_top.xst =================================================================== --- minsoc/trunk/prj/xilinx/minsoc_top.xst (nonexistent) +++ minsoc/trunk/prj/xilinx/minsoc_top.xst (revision 85) @@ -0,0 +1,12 @@ +set -tmpdir ./xst +run +-vlgincdir { "/home/raul/or1k/minsoc/prj/../backend" "/home/raul/or1k/minsoc/prj/../bench/verilog" "/home/raul/or1k/minsoc/prj/../bench/verilog/vpi" "/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib" "/home/raul/or1k/minsoc/prj/../rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup" } +-ifn /home/raul/or1k/minsoc/prj/../prj/minsoc_top.prj +-ifmt Verilog +-ofn minsoc_top +-ofmt NGC +-p DEVICE_PART +-top minsoc_top +-opt_mode Speed +-opt_level 1 +-iobuf yes Index: minsoc/trunk/prj/xilinx/uart_top.prj =================================================================== --- minsoc/trunk/prj/xilinx/uart_top.prj (nonexistent) +++ minsoc/trunk/prj/xilinx/uart_top.prj (revision 85) @@ -0,0 +1,11 @@ +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_top.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_wb.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_regs.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_defines.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/raminfr.v" Index: minsoc/trunk/prj/xilinx/adbg_top.prj =================================================================== --- minsoc/trunk/prj/xilinx/adbg_top.prj (nonexistent) +++ minsoc/trunk/prj/xilinx/adbg_top.prj (revision 85) @@ -0,0 +1,10 @@ +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v" Index: minsoc/trunk/prj/xilinx/uart_top.xst =================================================================== --- minsoc/trunk/prj/xilinx/uart_top.xst (nonexistent) +++ minsoc/trunk/prj/xilinx/uart_top.xst (revision 85) @@ -0,0 +1,12 @@ +set -tmpdir ./xst +run +-vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog" } +-ifn /home/raul/or1k/minsoc/prj/../prj/uart_top.prj +-ifmt Verilog +-ofn uart_top +-ofmt NGC +-p DEVICE_PART +-top uart_top +-opt_mode Speed +-opt_level 1 +-iobuf no Index: minsoc/trunk/prj/xilinx/ethmac.prj =================================================================== --- minsoc/trunk/prj/xilinx/ethmac.prj (nonexistent) +++ minsoc/trunk/prj/xilinx/ethmac.prj (revision 85) @@ -0,0 +1,25 @@ +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_cop.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_registers.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_miim.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac_defines.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_crc.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_random.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_register.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v" +`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v" Index: minsoc/trunk/prj/xilinx/adbg_top.xst =================================================================== --- minsoc/trunk/prj/xilinx/adbg_top.xst (nonexistent) +++ minsoc/trunk/prj/xilinx/adbg_top.xst (revision 85) @@ -0,0 +1,12 @@ +set -tmpdir ./xst +run +-vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog" } +-ifn /home/raul/or1k/minsoc/prj/../prj/adbg_top.prj +-ifmt Verilog +-ofn adbg_top +-ofmt NGC +-p DEVICE_PART +-top adbg_top +-opt_mode Speed +-opt_level 1 +-iobuf no Index: minsoc/trunk/prj/xilinx/ethmac.xst =================================================================== --- minsoc/trunk/prj/xilinx/ethmac.xst (nonexistent) +++ minsoc/trunk/prj/xilinx/ethmac.xst (revision 85) @@ -0,0 +1,12 @@ +set -tmpdir ./xst +run +-vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog" } +-ifn /home/raul/or1k/minsoc/prj/../prj/ethmac.prj +-ifmt Verilog +-ofn ethmac +-ofmt NGC +-p DEVICE_PART +-top ethmac +-opt_mode Speed +-opt_level 1 +-iobuf no Index: minsoc/trunk/prj/Makefile =================================================================== --- minsoc/trunk/prj/Makefile (nonexistent) +++ minsoc/trunk/prj/Makefile (revision 85) @@ -0,0 +1,36 @@ +PROJECTS = minsoc_top.prj or1200_top.prj adbg_top.prj jtag_top.prj uart_top.prj ethmac.prj + +SRC_DIR = src +SCRIPTS_DIR = scripts + +SIMULATION_DIR = sim +XILINX_DIR = xilinx +ALTERA_DIR = altera + +SIMULATION_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .src, $(basename $(PROJECTS)))) +XILINX_PRJ_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS)))) +XILINX_XST_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .xst, $(basename $(PROJECTS)))) + +all: $(SIMULATION_DIR)/minsoc.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES) + +clean: + rm -rf $(SIMULATION_DIR)/*.src $(XILINX_DIR)/*.prj $(XILINX_DIR)/*.xst + +$(XILINX_DIR)/minsoc_top.xst: $(SRC_DIR)/minsoc_top.prj + bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ minsoc_top.prj minsoc_top topmodule + +$(XILINX_DIR)/minsoc_top.prj: $(SRC_DIR)/minsoc_top.prj + bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@ topmodule + +$(XILINX_DIR)/%.xst: $(SRC_DIR)/%.prj + bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ $*.prj $* + +$(XILINX_DIR)/%.prj: $(SRC_DIR)/%.prj + bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@ + +$(SIMULATION_DIR)/minsoc.src: $(SIMULATION_FILES) + cat $(SIMULATION_FILES) > $(SIMULATION_DIR)/minsoc.src + +$(SIMULATION_DIR)/%.src: $(SRC_DIR)/%.prj + bash $(SCRIPTS_DIR)/simprj.sh $^ $@ +