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Rev 85 → Rev 86

/jart/branches/ver0branch/yu.vhd
21,8 → 21,10
-- You should have received a copy of the GNU General Public License
-- along with JART (Just Another Ray Tracer). If not, see <http://www.gnu.org/licenses/>.library ieee;
-- Unitary ray vector Y component integrator. In a memory block of 1x16384 bits, it is stored the FY' that represents the first derivate of FY, this function is the Y function along any horizontal line in the image.
-- The derivative is stored in this way: logic 0 means a 0 pendant and logic 1 means a -1 pendant. So a counter with enable / disable control it is everything we need, and of course a load input to represent the initial value added to the integral.
-- Ray Generator.....
-- The entity synthesizes 4 simmetrical rays each clock. The ena signal enables/disables the ray production.
-- The Ray Generator starts by generating after the first clock's rising edge with the ena signal set.
-- The first four rays generated are the Rays passing through the center of the screen, in the 320x200 screen these rays are : (159,99)(160,99)(159,100)(160,100), after those rays the next four rays are (158,99)(161,99)(158,100)(161,100).
 
library ieee;
use ieee.std_logic_1164.all;
32,6 → 34,9
 
entity yu is
generic (
VALSTARTX : integer := 34;
VALSTARTY : integer := 1023;
VALSTARTZ : integer := 9;
TOP : integer := 1024; -- Define the max counting number.. the number must be expressed as 2 power, cause the range of counting is going to be defined as TOP-1 downto TOP/2.
-- However this is going to be by now, cause in the future the ray generation will GO on for higher resolution images , and perhaps it would be required a more extended range for the yu component.
SCREENW : integer := 320 -- resolution width is 320
39,13 → 44,17
port (
clk,rst,ena : in std_logic;
lineDone : out std_logic; -- Finished image row. once a hundred and sixty times....
ypos : out integer range TOP/2 to TOP-1
-- ocntr : out integer range 0 to SCREENW/2
ocntr : out integer range 0 to SCREENW/2;
ypos : out integer range TOP/2 to TOP-1;
zpos : out integer range -TOP to TOP-1;
zneg : out integer range -TOP to TOP-1;
xpos : out integer range -TOP to TOP-1;
xneg : out integer range -TOP to TOP-1
 
);
end entity;
 
architecture rtl of yu is
-- 1x16384 bits, true dual port, ROM Memory declaration.
-- This memory uses 2 cycles.. a memory fetch cycle and a data to q memory cycle.
component yurom
61,7 → 70,7
end component;
 
constant linefeed : integer range 0 to (SCREENW/2) := (SCREENW/2)-2;
constant linefeed : integer range 0 to (SCREENW/2) := (SCREENW/2)-4;
-- Support signals.
70,13 → 79,20
signal sf0 : std_logic_vector (0 downto 0); -- Derivative function
signal sf1 : std_logic_vector (0 downto 0); -- Derivative curve, initial constant derivative function.
signal cc : integer range 0 to SCREENW/2;
signal f0 : integer range TOP/2 to TOP-1;
signal fy : integer range TOP/2 to TOP-1;
signal pivotCol,pivotRow : std_logic;
signal fz : integer range -TOP to TOP-1;
signal fx : integer range -TOP to TOP-1;
begin
 
-- Connect f0, to the output.
ypos <= f0;
 
-- Connect fy, to the output.
ypos <= fy;
xpos <= fx;
xneg <= -fx;
zpos <= fz;
zneg <= -fz;
ocntr<= cc;
derivate : yurom
port map (
address_a => s1addf0,
89,33 → 105,47
integrationControl : process (clk,rst,ena)
variable f1 : integer range TOP/2 to TOP-1;
begin
if rst='0' then
 
f0<=TOP-1;
f1:=TOP-1;
lineDone<='0';
fy<=TOP/2;
f1:=VALSTARTY;
fz<=VALSTARTZ-2;
fx<=0;
pivotCol <= '0';
pivotRow <= '0';
elsif rising_edge(clk) and ena='1' then
if cc=0 then
lineDone<='1';
if sf1(0) ='1' then
f1 := f1 - 1;
end if;
f0 <= f1;
if cc=(SCREENW/2)-1 then
-- Y component
f1 := f1 - CONV_INTEGER('0'&sf1(0));
fy <= f1;
-- X component
fx <= VALSTARTX;
-- Z component
fz <= fz+2+CONV_INTEGER('0'&pivotRow); -- Beware of the sign!
pivotRow <= not (pivotRow);
else
lineDone<='0';
if sf0(0) = '1' then
f0 <= f0-1;
end if;
-- Y Component
fy <= fy-CONV_INTEGER('0'&sf0(0));
-- X component
fx <= fx+2+CONV_INTEGER('0'&pivotCol); -- Beware of the sign!
pivotCol <= not(pivotCol);
end if;
end if;
126,12 → 156,15
if rst='0' then
cc<=0;
cc<=SCREENW/2-1;
lineDone<='0';
elsif rising_edge(clk) and ena='1' then
if cc=(SCREENW/2)-1 then
lineDone<='1';
cc<=0;
else
lineDone<='0';
cc<=cc+1;
end if;
end if;

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