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Rev 85 → Rev 86

/v586/trunk/tb/tb_top.v
0,0 → 1,39
/* verilator lint_off UNUSED */
/* verilator lint_off CASEX */
/* verilator lint_off PINNOCONNECT */
/* verilator lint_off PINMISSING */
/* verilator lint_off IMPLICIT */
/* verilator lint_off WIDTH */
/* verilator lint_off COMBDLY */
 
module tb_top ();
wire [1:0] Ae;
wire [15:0] DB;
wire [23:0] Ad;
wire LB,UB;
reg RXD,clk,rstn;
 
TOP_SYS U_TOP (
.TXD(TXD),.rstn(rstn),.clk100(clk), .RXD(RXD),
.extWEN(WEN),.extUB(UB),.extLB(LB),.extA(Ad),.extDB(DB), .extOE(OE), .extCRE(CRE), .extADV(ADV), .extCLK(memCLK),.extCSN(memCE),
.gpio_in(7'b000_0000)//, .extWAIT(1'b0)
);
 
extram uextram(.clk(clk) , .DB(DB) , .A(Ad) , .WEN(WEN) ,.LB(LB), .UB(UB), .OE(OE) );
 
initial
begin
RXD =1;
clk=0;
rstn =0;
#1000;
rstn = 1;
#100000
$finish;
end
 
always #5 clk<=~clk;
 
always @(posedge clk) if ((U_TOP.v586.writeio_req == 1)&&(U_TOP.i_periph.csn_16750 == 0)) $write("%c",U_TOP.i_periph.writeio_data[7:0]);
 
endmodule

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