URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 86 to Rev 87
- ↔ Reverse comparison
Rev 86 → Rev 87
/trunk/gen_or1k_isa/sources/gen_or1k_isa.c
25,6 → 25,47
} field[50]; |
} decoded; |
|
struct info { |
struct or1k_isa *desc; |
struct or32_opcode *opcode; |
} info; |
|
void transform_tex(char *input, char *output) |
{ |
while (*input != '\0') { |
if (*input == '[') { |
*output++ = '{'; |
*output++ = '['; |
*output++ = '}'; |
} else if (*input == ']') { |
*output++ = '{'; |
*output++ = ']'; |
*output++ = '}'; |
} else if (*input == '%') { |
*output++ = '\\'; |
*output++ = '%'; |
} else if (*input == '\\') { |
*output++ = '\\'; |
*output++ = '\\'; |
} else if (*input == '_') { |
*output++ = '\\'; |
*output++ = '_'; |
} else if (*input == '\t') { |
*output++ = '\\'; |
*output++ = 'i'; |
*output++ = 'n'; |
*output++ = 'd'; |
*output++ = 'e'; |
*output++ = 'n'; |
*output++ = 't'; |
*output++ = ' '; |
} else |
*output++ = *input; |
input++; |
} |
*output = '\0'; |
} |
|
void print_encoding() |
{ |
int i, j; |
36,7 → 77,12
for(i = 1; i <= decoded.fldcnt; i++) { |
printf("|"); |
for(j = 0; j < decoded.field[i].bitsize; j++) |
printf("c"); |
if (j == 0) |
printf("l"); |
else if (j+1 == decoded.field[i].bitsize) |
printf("r"); |
else |
printf("c"); |
} |
printf("|}\n\\hline\n"); |
|
45,7 → 91,7
if (decoded.bitpos[i]) |
printf("%d&\n", i); |
else |
printf("&\n"); |
printf(".&\n"); |
printf("0\\\\\n\\hline\n"); |
|
/* print second row of the table */ |
76,13 → 122,15
printf("{%sc|}{%d bits}&\n", (i == 1 ? "|":""), decoded.field[i].bitsize); |
} |
printf("\\multicolumn{%d}", decoded.field[i].bitsize); |
printf("{%sc|}{%d bits}\\\\\n", (i == 1 ? "|":""), decoded.field[i].bitsize); |
printf("\n\\hline\n"); |
printf("\\end{tabular}\\par}\n"); |
|
printf("{%sc|}{%d bits}\\\\\n", (i == 1 ? "|":""), decoded.field[i].bitsize); |
/* printf("\n\\hline\n"); |
/* printf("\\multicolumn{32}"); |
/* printf("{|c|}{\\textcolor{white}{XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX "); |
printf("XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX}}\\\\\n");*/ |
printf("\\end{tabular}\\par}\n"); |
} |
|
void decode(struct or1_opcode *insn) |
void decode(struct or32_opcode *insn) |
{ |
int opc_pos = 0; |
char *enc; |
173,103 → 221,165
enc++; |
} |
|
void print_header(struct or1_opcode *insn, struct or1k_isa *info) |
void print_header(struct or32_opcode *insn, struct or1k_isa *info) |
{ |
printf("\n\n\\newpage\n"); |
char tmp[2000]; |
|
printf("\n\n\\pagebreak\n"); |
printf("\\vspace{10mm}\n"); |
/* printf("\\section{Appendix A}\n"); */ |
printf("\\lyxline{\\small}\\vspace{-1\\parskip}\n"); |
printf("\\vspace{10mm}\n"); |
printf("{\\raggedright \\begin{tabular}{ccc}\n"); |
printf("{\\centering \\begin{tabular}{ccc}\n"); |
printf("\\textbf{\\textcolor{white}{\\small Left}}\\textcolor{white}{\\small }&\n"); |
printf("\\textcolor{white}{\\small }\\textbf{\\textcolor{white}{\\small Middle Middle\n"); |
printf("Middle Middle Middle Middle Middle Middle}} \\textcolor{white}{\\small }&\n"); |
printf("\\textcolor{white}{\\small }\\textbf{\\textcolor{white}{\\small Middle \n"); |
printf("Middle Middle Middle Middle Middle Middle "); |
printf("Middle Middle Middle Middle Middle Middle "); |
printf("Middle Middle Middle}} \\textcolor{white}{\\small }&\n"); |
printf("\\textcolor{white}{\\small }\\textbf{\\textcolor{white}{\\small Right}}\\\\\n"); |
printf("\\textbf{\\huge %s}&\n", insn->name); |
printf("\\multicolumn{1}{c}{\\textbf{\\huge %s}}&\n", info->title); |
printf("\\textbf{\\huge %s}\\\\\n", insn->name); |
transform_tex(insn->name, tmp); |
printf("\\textbf{\\Large %s}&\n", tmp); |
transform_tex(info->title, tmp); |
printf("\\multicolumn{1}{c}{\\textbf{\\Large %s}}&\n", tmp); |
transform_tex(insn->name, tmp); |
printf("\\textbf{\\Large %s}\\\\\n", tmp); |
printf("\\end{tabular}\\par}\n\\bigskip{}\n\n"); |
} |
|
struct or1k_isa *get_or1k_isa(char *name) |
struct or1k_isa *get_or1k_isa(unsigned long classes, struct info *info) |
{ |
int i; |
struct or1k_isa *tmp; |
|
while (1) { |
/* Pick first instruction that wasn't printed yet and meets current class constraint */ |
for (i = 0; strlen(or1k_isa_info[i].name); i++) |
if ((!or1k_isa_info[i].printed) && ((1<<or1k_isa_info[i].class)>>1 & classes)) |
break; |
|
/* Don't return any instruction if they were all already processed or don't meet |
class constraint. */ |
if (strlen(or1k_isa_info[i].name) == 0) { |
fprintf(stderr, "All instructions that meet class constraint %x were processed.\n", classes); |
return NULL; |
} |
|
for (i = 0; strlen(or1k_isa_info[i].name); i++) |
if (strcmp(or1k_isa_info[i].name, name) == 0) |
break; |
tmp = &or1k_isa_info[i]; |
|
return &or1k_isa_info[i]; |
/* Check if tmp instruction is first in order to be processed. If preceeding |
instructions are found, they are used instead. */ |
for (i = 0; strlen(or1k_isa_info[i].name); i++) |
if ((!or1k_isa_info[i].printed) && ((1<<or1k_isa_info[i].class)>>1 & classes) && |
(strcmp(or1k_isa_info[i].name, tmp->name) < 0)) |
tmp = &or1k_isa_info[i]; |
|
tmp->printed = 1; |
|
/* Find matching encoding. */ |
for (i = 0; strlen(or32_opcodes[i].name); i++) |
if (strcmp(tmp->name, or32_opcodes[i].name) == 0) { |
fprintf(stderr, "PROCESSING: %s\n", tmp->name); |
info->desc = tmp; |
info->opcode = &or32_opcodes[i]; |
return tmp; |
} |
} |
|
return NULL; |
} |
|
void transform_tex(char *input, char *output) |
void cross_ref_check() |
{ |
while (*input != '\0') { |
if (*input == '[') { |
*output++ = '{'; |
*output++ = '['; |
*output++ = '}'; |
} else if (*input == ']') { |
*output++ = '{'; |
*output++ = ']'; |
*output++ = '}'; |
} else if (*input == '\\') { |
*output++ = '\\'; |
*output++ = '\\'; |
} else |
*output++ = *input; |
input++; |
int i, j; |
|
for (i = 0; strlen(or32_opcodes[i].name); i++) { |
for (j = 0; strlen(or1k_isa_info[j].name); j++) |
if (strcmp(or32_opcodes[i].name, or1k_isa_info[j].name) == 0) |
break; |
if (strlen(or1k_isa_info[j].name) == 0) |
fprintf(stderr, "Description for %s missing.\n", or32_opcodes[i].name); |
} |
*output = '\0'; |
|
for (i = 0; strlen(or1k_isa_info[i].name); i++) { |
for (j = 0; strlen(or32_opcodes[j].name); j++) |
if (strcmp(or1k_isa_info[i].name, or32_opcodes[j].name) == 0) |
break; |
if (strlen(or32_opcodes[j].name) == 0) |
fprintf(stderr, "Encoding for %s missing.\n", or1k_isa_info[i].name); |
} |
} |
|
void print_body(struct or1_opcode *insn, struct or1k_isa *info) |
void print_body(struct or32_opcode *insn, struct or1k_isa *info) |
{ |
char tmp[2000]; |
|
printf("\\vspace{15mm}\n"); |
|
printf("{\\par\\raggedright \\textbf{\\LARGE Format:}\\LARGE \\par}\n"); |
printf("{\\par \\raggedright \\textbf{\\Large Format:}\\Large \\par}\n"); |
printf("\\vspace{5mm}\n"); |
printf("\\begin{quotation}\n"); |
printf("\\texttt{\\large %s\\ %s}{\\large \\par}\n", insn->name, insn->args); |
transform_tex(info->name, tmp); |
printf("\\texttt{\\large %s\\ ", tmp); |
transform_tex(insn->args, tmp); |
printf("%s}{\\large \\par}\n", tmp); |
printf("\\end{quotation}\n"); |
printf("\\vspace{10mm}\n"); |
|
printf("\\textbf{\\LARGE Description:}{\\LARGE \\par}\n"); |
printf("\\textbf{\\Large Description:}{\\Large \\par}\n"); |
printf("\\vspace{5mm}\n"); |
printf("\\begin{quotation}\n"); |
printf("\\texttt{\\large %s}{\\large \\par}\n", info->desc); |
transform_tex(info->desc, tmp); |
printf("%s\n", tmp); |
printf("\\end{quotation}\n"); |
printf("\\vspace{10mm}\n"); |
|
printf("\\textbf{\\LARGE Operation:}{\\LARGE \\par}\n"); |
printf("\\textbf{\\Large 32-bit Operation:}{\\Large \\par}\n"); |
printf("\\vspace{5mm}\n"); |
printf("\\begin{flushleft}\n"); |
printf("\\begin{quotation}\n"); |
transform_tex(info->oper, tmp); |
printf("%s\n", tmp); |
transform_tex(info->oper32, tmp); |
printf("\\texttt{\\large %s}{\\large \\par}\n", tmp); |
printf("\\end{quotation}\n"); |
printf("\\end{flushleft}\n"); |
printf("\\vspace{10mm}\n"); |
|
printf("\\textbf{\\LARGE Notes:}{\\LARGE \\par}\n"); |
printf("\\textbf{\\Large 64-bit Operation:}{\\Large \\par}\n"); |
printf("\\vspace{5mm}\n"); |
printf("\\begin{flushleft}\n"); |
printf("\\begin{quotation}\n"); |
transform_tex(info->oper64, tmp); |
printf("\\texttt{\\large %s}{\\large \\par}\n", tmp); |
printf("\\end{quotation}\n"); |
printf("\\end{flushleft}\n"); |
printf("\\vspace{10mm}\n"); |
|
printf("\\textbf{\\Large Exceptions:}{\\Large \\par}\n"); |
printf("\\vspace{5mm}\n"); |
printf("\\begin{flushleft}\n"); |
printf("\\begin{quotation}\n"); |
transform_tex(info->except, tmp); |
printf("\\texttt{\\large %s}{\\large \\par}\n",tmp); |
printf("\\end{quotation}\n"); |
printf("\\end{flushleft}\n"); |
printf("\\vspace{10mm}\n"); |
|
printf("\\textbf{\\Large Notes:}{\\Large \\par}\n"); |
printf("\\vspace{5mm}\n"); |
printf("\\begin{quotation}\n"); |
printf("\n"); |
printf("\\end{quotation}\n"); |
printf("\\vspace{10mm}\n"); |
|
printf("\\vfill\n"); |
printf("%s: \n", or1k_isa_classes[info->class].title); |
printf("{\\centering \\begin{tabular}{|c|c|c|}\n"); |
printf("{\\centering \\begin{tabular}{|c|c|}\n"); |
printf("\\hline\n"); |
printf("Architecture Level&\n"); |
printf("Execution Mode&\n"); |
printf("Instruction Subset&\n"); |
printf("Implementation\\\\\n"); |
printf("\\hline\n"); |
printf("%s\n", or1k_isa_classes[info->class].table); |
printf("\\hline\n"); |
transform_tex(or1k_isa_classes[info->class].table, tmp); |
printf("%s\n", tmp); |
printf("\\end{tabular}\\par}\n"); |
|
|
printf("\n"); |
} |
|
276,21 → 386,22
int main() |
{ |
int i; |
struct or1k_isa *info; |
|
cross_ref_check(); |
printf("\n\\begin{document}\n\\vspace{50mm}"); |
printf("\\section{OpenRISC 1000 Instruction Set}\n"); |
printf("Draft, Do not distribute\n"); |
|
for(i = 0; strlen(or1_opcodes[i].name); i++) { |
for(i = 0; strlen(or1k_order[i].title); i++) { |
printf("\\section{%s}\n", or1k_order[i].title); |
|
while (get_or1k_isa(or1k_order[i].classes, &info)) { |
|
print_header(info.opcode, info.desc); |
decode(info.opcode); |
print_encoding(); |
print_body(info.opcode, info.desc); |
} |
} |
|
info = get_or1k_isa(or1_opcodes[i].name); |
|
print_header(&or1_opcodes[i], info); |
decode(&or1_opcodes[i]); |
print_encoding(); |
print_body(&or1_opcodes[i], info); |
} |
printf("\n\\end{document}\n"); |
return 0; |
} |
/trunk/gen_or1k_isa/sources/main1.html
0,0 → 1,42
<html xmlns:o="urn:schemas-microsoft-com:office:office" |
xmlns:w="urn:schemas-microsoft-com:office:word" |
xmlns="http://www.w3.org/TR/REC-html40"> |
|
<head> |
<meta http-equiv=Content-Type content="text/html; charset=windows-1252"> |
<link rel=File-List href="./filelist.xml"> |
<title>Stran 1</title> |
<!--[if gte mso 9]><xml> |
</xml><![endif]--><!--[if gte mso 9]><xml> |
<w:WordDocument> |
<w:View>Print</w:View> |
<w:Zoom>75</w:Zoom> |
</w:WordDocument> |
</xml><![endif]--> |
<style> |
<!-- |
/* Style Definitions */ |
p.MsoNormal, li.MsoNormal, div.MsoNormal |
{mso-style-parent:""; |
margin:0in; |
margin-bottom:.0001pt; |
mso-pagination:widow-orphan; |
font-size:12.0pt; |
font-family:"Times New Roman"; |
mso-fareast-font-family:"Times New Roman";} |
p.MsoHeader, li.MsoHeader, div.MsoHeader |
{margin:0in; |
margin-bottom:.0001pt; |
mso-pagination:widow-orphan; |
tab-stops:center 3.0in right 6.0in; |
font-size:12.0pt; |
font-family:"Times New Roman"; |
mso-fareast-font-family:"Times New Roman";} |
p.MsoFooter, li.MsoFooter, div.MsoFooter |
{margin:0in; |
margin-bottom:.0001pt; |
mso-pagination:widow-orphan; |
tab-stops:center 3.0in right 6.0in; |
font-size:12.0pt; |
font-family:"Times New Roman"; |
mso-fareast-font-family:"Times New Roman";} |
/trunk/gen_or1k_isa/sources/filelist.xml
0,0 → 1,5
<xml xmlns:o="urn:schemas-microsoft-com:office:office"> |
<o:MainFile HRef="or1k_isa.html"/> |
<o:File HRef="hf.html"/> |
<o:File HRef="filelist.xml"/> |
</xml> |
/trunk/gen_or1k_isa/sources/or1k_isadesc.h
5,457 → 5,2236
char *name; |
char *title; |
char *desc; |
char *oper; |
char *oper32; |
char *oper64; |
char *except; |
int class; |
int printed; |
}; |
|
#define ORBIS32I 1 |
#define ORBIS32II 2 |
#define ORBIS64I 3 |
#define ORBIS64II 4 |
#define ORFPX32I 5 |
#define ORFPX32II 6 |
#define ORFPX64I 7 |
#define ORFPX64II 8 |
#define ORVDX64I 9 |
#define ORVDX64II 10 |
|
static struct or1k_isa or1k_isa_info[] = |
{ |
|
{"l.addi32s", "Add Immediate Signed", |
"Immediate is signed-extended and added to the contents of general " |
"register rB to form the result. The result is placed into general " |
"register rA.", |
"rA <- rB + exts(Immediate)", "Integer Overflow", 1,}, |
/*** ORBIS32 ***/ |
|
{"l.subi32s", "Subtract Immediate Signed", |
"Immediate is signed-extended and subtracted from the contents of general " |
"register rB to form the result. The result is placed into general " |
"register rA.", |
"rA <- rB - exts(Immediate)", "Integer Overflow", 1,}, |
{"l.addi", "Add Immediate Signed", |
"Immediate is signed-extended and added to the contents of general-purpose" |
"register rA to form the result. The result is placed into general-purpose" |
"register rD.", |
"rD[31:0] <- rA[31:0] + exts(Immediate)", |
"rD[63:0] <- rA[63:0] + exts(Immediate)", |
"Integer Overflow", ORBIS32I,}, |
|
{"l.sub32s", "Subtract Signed", |
"The contents of general register rC is subtracted from the contents " |
"of general register rB to form the result. The result is placed into " |
"general register rA.", |
"rA <- rB - rC", "Integer Overflow", 1,}, |
{"l.addic", "Add Immediate Signed and Carry", |
"Immediate is signed-extended and added to the contents of general-purpose" |
"register rA and carry SR[CY] to form the result. The result is placed " |
"into general-purpose register rD.", |
"rD[31:0] <- rA[31:0] + exts(Immediate) + SR[CY]", |
"rD[63:0] <- rA[63:0] + exts(Immediate) + SR[CY]", |
"Integer Overflow", ORBIS32II,}, |
|
{"h.add32s", "Add Signed", |
"The contents of general register rC is added to the contents " |
"of general register rB to form the result. The result is placed into " |
"general register rA.", |
"rA <- rB + rC", "Integer Overflow", 1,}, |
{"l.subi", "Subtract Immediate Signed", |
"Immediate is signed-extended and subtracted from the contents of general-purpose" |
"register rA to form the result. The result is placed into general-purpose" |
"register rD.", |
"rD[31:0] <- rA[31:0] - exts(Immediate)", |
"rD[63:0] <- rA[63:0] - exts(Immediate)", |
"Integer Overflow", ORBIS32I,}, |
|
{"h.ext16s", "Extend Half Word with Sign", |
"Bit 15 of general register rA is placed in high-order 16 bits of " |
"general register rA. The low-order 16 bits of general register rA " |
"are left unchanged.", |
"rA[31:16] <- rA[15]", "None", 2,}, |
{"l.andi", "And with Immediate Half Word", |
"Immediate is zero-extended and combined with the contents " |
"of general-purpose register rB in a bit-wise logical AND operation. The " |
"result is placed into general-purpose register rD.", |
"rD[31:0] <- rB[31:0] AND extz(Immediate)", |
"rD[63:0] <- rB[63:0] AND extz(Immediate)", |
"None", ORBIS32I,}, |
|
{"h.ext8s", "Extend Byte with Sign", |
"Bit 7 of general register rA is placed in high-order 24 bits of " |
"general register rA. The low-order eight bits of general register rA " |
"are left unchanged.", |
"rA[31:8] <- rA[7]", "None", 2,}, |
{"l.ori", "Or with Immediate Half Word", |
"Immediate is zero-extended and combined with the contents " |
"of general-purpose register rB in a bit-wise logical OR operation. The " |
"result is placed into general-purpose register rD.", |
"rD[31:0] <- rB[31:0] OR extz(Immediate)", |
"rD[63:0] <- rB[63:0] OR extz(Immediate)", |
"None", ORBIS32I,}, |
|
{"h.ext8z", "Extend Byte with Zero", |
"Zero is placed in high-order 24 bits of " |
"general register rA. The low-order eight bits of general register rA " |
"are left unchanged.", |
"rA[31:8] <- 0", "None", 2,}, |
{"l.xori", "Exclusive Or with Immediate Half Word", |
"Immediate is zero-extended and combined with the contents of general-purpose " |
"register rB in a bit-wise logical XOR operation. The result is " |
"placed into general-purpose register rD.", |
"rD[31:0] <- rB[31:0] XOR exts(Immediate)", |
"rD[63:0] <- rB[63:0] XOR exts(Immediate)", |
"None", ORBIS32I,}, |
|
{"h.ext16z", "Extend Half Word with Zero", |
"Zero is placed in high-order 16 bits of " |
"general register rA. The low-order 16 bits of general register rA " |
"are left unchanged.", |
"rA[31:16] <- 0", "None", 2,}, |
{"l.slli", "Shift Left Logical with Immediate", |
"6-bit immediate specifies the number of " |
"bit positions the contents of general-purpose register rA are shifted left, " |
"inserting zeros into the low-order bits. Result is written into general-purpose " |
"rD.", |
"rD[31:L] <- rA[31-L:0]\\rD[L-1:0] <- 0", |
"rD[63:L] <- rA[63-L:0]\\rD[L-1:0] <- 0", |
"None", ORBIS32I,}, |
|
{"l.load8s", "Load Byte and Extend with Sign", |
"Offset is sign-extended and added to the contents of general " |
"register rB. Sum represents effective address. The byte in memory " |
{"l.srai", "Shift Right Arithmetic with Immediate", |
"6-bit immediate specifies the number of " |
"bit positions the contents of general-purpose register rA are shifted right, " |
"sign-extending the high-order bits. Result is written into " |
"general-purpose register rD.", |
"rD[31-L:0] <- rA[31:L]\\rD[31:32-L] <- rA[31]", |
"rD[63-L:0] <- rA[63:L]\\rD[63:64-L] <- rA[63]", |
"None", ORBIS32I,}, |
|
{"l.srli", "Shift Right Logical with Immediate", |
"6-bit Immediate specifies the number of " |
"bit positions the contents of general-purpose register rA are shifted right, " |
"inserting zeros into the high-order bits. Result is written into general-purpose " |
"register rD.", |
"rD[31-L:0] <- rA[31:L]\\rD[31:32-L] <- 0", |
"rD[63-L:0] <- rA[63:L]\\rD[63:64-L] <- 0", |
"None", ORBIS32I,}, |
|
{"l.rori", "Rotate Right with Immediate", |
"6-bit immediate specifies the number of " |
"bit positions the contents of general-purpose register rA are rotated right. " |
"Result is written into general-purpose register rD.", |
"rD[31-L:0] <- rA[31:L]\\rD[31:32-L] <- rA[L-1:0]", |
"rD[63-L:0] <- rA[63:L]\\rD[63:64-L] <- rA[L-1:0]", |
"None", ORBIS32I,}, |
|
{"l.muli", "Multiply Immediate Signed", |
"Immediate and the contents of general-purpose register rA are " |
"multiplied and the result is truncated to destination register width and placed into " |
"general-purpose register rD.", |
"rD[31:0] <- rA[31:0] * Immediate", |
"rD[63:0] <- rA[63:0] * Immediate", |
"None", ORBIS32I,}, |
|
{"l.exths", "Extend Half Word with Sign", |
"Bit 15 of general-purpose register rA is placed in high-order bits of " |
"general-purpose register rD. The low-order 16 bits of general-purpose register rA " |
"are copied into low-order 16 bits of general-purpose register rD.", |
"rD[31:16] <- rA[15]\\rD[15:0] <- rA[15:0]", |
"rD[63:16] <- rA[15]\\rD[15:0] <- rA[15:0]", |
"None", ORBIS32II,}, |
|
{"l.extbs", "Extend Byte with Sign", |
"Bit 7 of general-purpose register rA is placed in high-order bits of " |
"general-purpose register rD. The low-order eight bits of general-purpose register rA " |
"are copied from low-order eight bits of general-purpose register rD.", |
"rD[31:8] <- rA[7]\\rD[7:0] <- rA[7:0]", |
"rD[63:8] <- rA[7]\\rD[7:0] <- rA[7:0]", |
"None", ORBIS32II,}, |
|
{"l.extbz", "Extend Byte with Zero", |
"Zero is placed in high-order bits of " |
"general-purpose register rD. The low-order eight bits of general-purpose register rA " |
"are copied into low-order eight bits of general-purpose register rD.", |
"rD[31:8] <- 0\\rD[7:0] <- rA[7:0]", |
"rD[63:8] <- 0\\rD[7:0] <- rA[7:0]", |
"None", ORBIS32II,}, |
|
{"l.exthz", "Extend Half Word with Zero", |
"Zero is placed in high-order bits of " |
"general-purpose register rD. The low-order 16 bits of general-purpose register rA " |
"are copied into low-order 16 bits of general-purpose register rD.", |
"rD[31:16] <- 0\\rD[15:0] <- rA[15:0]", |
"rD[63:16] <- 0\\rD[15:0] <- rA[15:0]", |
"None", ORBIS32II,}, |
|
{"l.extwz", "Extend Word with Zero", |
"Zero is placed in high-order bits of " |
"general-purpose register rD. The low-order 32 bits of general-purpose register rA " |
"are copied into low-order 32 bits of general-purpose register rD.", |
"rD[31:0] <- rA[31:0]", |
"rD[63:32] <- 0\\rD[31:0] <- rA[31:0]", |
"None", ORBIS64II,}, |
|
{"l.extws", "Extend Word with Sign", |
"Bit 31 of general-purpose register rA is placed in high-order bits of " |
"general-purpose register rD. The low-order 32 bits of general-purpose register rA " |
"are copied from low-order 32 bits of general-purpose register rD.", |
"rD[31:0] <- rA[31:0]", |
"rD[63:32] <- rA[31]\\rD[31:0] <- rA[31:0]", |
"None", ORBIS64II,}, |
|
{"l.lbs", "Load Byte and Extend with Sign", |
"Offset is sign-extended and added to the contents of general-purpose " |
"register rA. Sum represents effective address. The byte in memory " |
"addressed by EA is loaded into the low-order eight bits of " |
"general register rA. " |
"High-order 24 bits of general register rA are replaced with " |
"general-purpose register rD. " |
"High-order bits of general-purpose register rD are replaced with " |
"bit 7 of the loaded value.", |
"EA <- exts(Immediate) + rB\\rA[7:0] <- (EA)[7:0]\\rA[31:8] <- rA[8]", |
"TLB miss\\Page fault\\Bus error", 1,}, |
"EA <- exts(Immediate) + rA[31:0]\\rD[7:0] <- (EA)[7:0]\\rD[31:8] <- rA[8]", |
"EA <- exts(Immediate) + rA[63:0]\\rD[7:0] <- (EA)[7:0]\\rD[63:8] <- rA[8]", |
"TLB miss\\Page fault\\Bus error", ORBIS32I,}, |
|
{"l.load16s", "Load Half Word and Extend with Sign", |
"Offset is sign-extended and added to the contents of general " |
"register rB. Sum represents effective address. The half word in memory " |
{"l.lhs", "Load Half Word and Extend with Sign", |
"Offset is sign-extended and added to the contents of general-purpose " |
"register rA. Sum represents effective address. The half word in memory " |
"addressed by EA is loaded into the low-order 16 bits of " |
"general register rA. " |
"High-order 16 bits of general register rA are replaced with " |
"general-purpose register rD. " |
"High-order bits of general-purpose register rD are replaced with " |
"bit 15 of the loaded value.", |
"EA <- exts(Immediate) + rB\\rA[15:0] <- (EA)[15:0]\\rA[31:16] <- rA[15]", |
"TLB miss\\Page fault\\Bus error", 1,}, |
"EA <- exts(Immediate) + rA[31:0]\\rD[15:0] <- (EA)[15:0]\\rD[31:16] <- rA[15]", |
"EA <- exts(Immediate) + rA[63:0]\\rD[15:0] <- (EA)[15:0]\\rD[63:16] <- rA[15]", |
"TLB miss\\Page fault\\Bus error", ORBIS32I,}, |
|
{"l.load8u", "Load Byte and Extend with Zero", |
"Offset is sign-extended and added to the contents of general " |
"register rB. Sum represents effective address. The byte in memory " |
{"l.lws", "Load Single Word and Extend with Sign", |
"Offset is sign-extended and added to the contents of general-purpose " |
"register rA. Sum represents effective address. The single word in memory " |
"addressed by EA is loaded into the low-order 32 bits of " |
"general-purpose register rD. " |
"High-order bits of general-purpose register rD are replaced with " |
"bit 31 of the loaded value.", |
"EA <- exts(Immediate) + rA[31:0]\\rD[31:0] <- (EA)[31:0]", |
"EA <- exts(Immediate) + rA[63:0]\\rD[31:0] <- (EA)[31:0]\\rD[63:32] <- rA[31]", |
"TLB miss\\Page fault\\Bus error", ORBIS32I,}, |
|
{"l.lbz", "Load Byte and Extend with Zero", |
"Offset is sign-extended and added to the contents of general-purpose " |
"register rA. Sum represents effective address. The byte in memory " |
"addressed by EA is loaded into the low-order eight bits of " |
"general register rA. " |
"High-order 24 bits of general register rA are replaced with " |
"general-purpose register rD. " |
"High-order bits of general-purpose register rD are replaced with " |
"zero.", |
"EA <- exts(Immediate) + rB\\rA[7:0] <- (EA)[7:0]\\rA[31:8] <- 0", |
"TLB miss\\Page fault\\Bus error", 1,}, |
"EA <- exts(Immediate) + rA[31:0]\\rD[7:0] <- (EA)[7:0]\\rD[31:8] <- 0", |
"EA <- exts(Immediate) + rA[63:0]\\rD[7:0] <- (EA)[7:0]\\rD[63:8] <- 0", |
"TLB miss\\Page fault\\Bus error", ORBIS32I,}, |
|
{"l.load16u", "Load Half Word and Extend with Zero", |
"Offset is sign-extended and added to the contents of general " |
"register rB. Sum represents effective address. The half word in memory " |
{"l.lhz", "Load Half Word and Extend with Zero", |
"Offset is sign-extended and added to the contents of general-purpose " |
"register rA. Sum represents effective address. The half word in memory " |
"addressed by EA is loaded into the low-order 16 bits of " |
"general register rA. " |
"High-order 16 bits of general register rA are replaced with " |
"general-purpose register rD. " |
"High-order bits of general-purpose register rD are replaced with " |
"zero.", |
"EA <- exts(Immediate) + rB\\rA[15:0] <- (EA)[15:0]\\rA[31:16] <- 0", |
"TLB miss\\Page fault\\Bus error", 1,}, |
"EA <- exts(Immediate) + rA[31:0]\\rD[15:0] <- (EA)[15:0]\\rD[31:16] <- 0", |
"EA <- exts(Immediate) + rA[63:0]\\rD[15:0] <- (EA)[15:0]\\rD[63:16] <- 0", |
"TLB miss\\Page fault\\Bus error", ORBIS32I,}, |
|
{"l.load32u", "Load Word and Extend with Zero", |
"Offset is sign-extended and added to the contents of general " |
"register rB. Sum represents effective address. The word in memory " |
"addressed by EA is loaded into general register rA. ", |
"EA <- exts(Immediate) + rB\\rA <- (EA)[31:0]", |
"TLB miss\\Page fault\\Bus error", 1,}, |
{"l.lwz", "Load Single Word and Extend with Zero", |
"Offset is sign-extended and added to the contents of general-purpose " |
"register rA. Sum represents effective address. The single word in memory " |
"addressed by EA is loaded into the low-order 32 bits of " |
"general-purpose register rD. " |
"High-order bits of general-purpose register rD are replaced with " |
"zero.", |
"EA <- exts(Immediate) + rA[31:0]\\rD[31:0] <- (EA)[31:0]", |
"EA <- exts(Immediate) + rA[63:0]\\rD[31:0] <- (EA)[31:0]\\rD[63:32] <- 0", |
"TLB miss\\Page fault\\Bus error", ORBIS32I,}, |
|
{"h.load32u", "Load Word and Extend with Zero", |
"Offset is sign-extended and added to the contents of general " |
"register rB. Sum represents effective address. The word in memory " |
"addressed by EA is loaded into general register rA. ", |
"EA <- exts(Immediate) + rB\\rA <- (EA)[31:0]", |
"TLB miss\\Page fault\\Bus error", 2,}, |
{"l.ld", "Load Double Word", |
"Offset is sign-extended and added to the contents of general-purpose " |
"register rA. Sum represents effective address. The double word in memory " |
"addressed by EA is loaded into general-purpose register rD. ", |
"N/A", |
"EA <- exts(Immediate) + rA[63:0]\\rD[63:0] <- (EA)[63:0]", |
"TLB miss\\Page fault\\Bus error", ORBIS64I,}, |
|
{"l.stor32", "Store Word", |
"Offset is sign-extended and added to the contents of general " |
"register rA. Sum represents effective address. The word in " |
"general register rB is stored to memory addressed by EA. ", |
"EA <- exts(Immediate) + rA\\(EA)[31:0] <- rB", |
"TLB miss\\Page fault\\Bus error", 1,}, |
{"l.sd", "Store Double Word", |
"Offset is sign-extended and added to the contents of general-purpose " |
"register rA. Sum represents effective address. The double word in " |
"general-purpose register rB is stored to memory addressed by EA. ", |
"N/A", |
"EA <- exts(Immediate) + rA[63:0]\\(EA)[63:0] <- rB[63:0]", |
"TLB miss\\Page fault\\Bus error", ORBIS64I,}, |
|
{"h.stor32", "Store Word", |
"Offset is sign-extended and added to the contents of general " |
"register rA. Sum represents effective address. The word in " |
"general register rB is stored to memory addressed by EA. ", |
"EA <- exts(Immediate) + rA\\(EA)[31:0] <- rB", |
"TLB miss\\Page fault\\Bus error", 2,}, |
{"l.sw", "Store Single Word", |
"Offset is sign-extended and added to the contents of general-purpose " |
"register rA. Sum represents effective address. The low-order 32 bits of " |
"general-purpose register rB are stored to memory addressed by EA. ", |
"EA <- exts(Immediate) + rA[31:0]\\(EA)[31:0] <- rB[31:0]", |
"EA <- exts(Immediate) + rA[63:0]\\(EA)[31:0] <- rB[31:0]", |
"TLB miss\\Page fault\\Bus error", ORBIS32I,}, |
|
{"l.stor16", "Store Half Word", |
"Offset is sign-extended and added to the contents of general " |
{"l.sh", "Store Half Word", |
"Offset is sign-extended and added to the contents of general-purpose " |
"register rA. Sum represents effective address. The low-order 16 bits " |
"of general register rB are stored to memory addressed by EA. ", |
"EA <- exts(Immediate) + rA\\(EA)[15:0] <- rB[15:0]", |
"TLB miss\\Page fault\\Bus error", 1,}, |
"of general-purpose register rB are stored to memory addressed by EA. ", |
"EA <- exts(Immediate) + rA[31:0]\\(EA)[15:0] <- rB[15:0]", |
"EA <- exts(Immediate) + rA[63:0]\\(EA)[15:0] <- rB[15:0]", |
"TLB miss\\Page fault\\Bus error", ORBIS32I,}, |
|
{"l.stor8", "Store Byte", |
"Offset is sign-extended and added to the contents of general " |
{"l.sb", "Store Byte", |
"Offset is sign-extended and added to the contents of general-purpose " |
"register rA. Sum represents effective address. The low-order 8 bits " |
"of general register rB are stored to memory addressed by EA. ", |
"EA <- exts(Immediate) + rA\\(EA)[7:0] <- rB[7:0]", |
"TLB miss\\Page fault\\Bus error", 1,}, |
"of general-purpose register rB are stored to memory addressed by EA. ", |
"EA <- exts(Immediate) + rA[31:0]\\(EA)[7:0] <- rB[7:0]", |
"EA <- exts(Immediate) + rA[63:0]\\(EA)[7:0] <- rB[7:0]", |
"TLB miss\\Page fault\\Bus error", ORBIS32I,}, |
|
{"l.shla32", "Shift Left Arithmetic", |
"Immediate is combined with low-order 5 bits of general register rC " |
"in a bit-wise logical OR operation. The result specifies the number of " |
"bit positions the contents of general register rB are shifted left, " |
"inserting zeros into the low-order bits.", |
"b <- Immediate | rC\\rA[31:b] <- rB[31-b:0]\\rA[b:0] <- 0", |
"None", 1,}, |
{"l.add", "Add Signed", |
"The contents of general-purpose register rA is added to the contents " |
"of general-purpose register rB to form the result. The result is placed into " |
"general-purpose register rD.", |
"rD[31:0] <- rA[31:0] + rB[31:0]", |
"rD[63:0] <- rA[63:0] + rB[63:0]", |
"Integer Overflow", ORBIS32I,}, |
|
{"l.shra32", "Shift Right Arithmetic", |
"Immediate is combined with low-order 5 bits of general register rC " |
"in a bit-wise logical OR operation. The result specifies the number of " |
"bit positions the contents of general register rB are shifted right, " |
"sign-extending the high-order bits.", |
"b <- Immediate | rC\\rA[31-b:0] <- rB[31:b]\\rA[31-b:31] <- rB[31]", |
"None", 1,}, |
{"l.addc", "Add Signed and Carry", |
"The contents of general-purpose register rA is added to the contents " |
"of general-purpose register rB and carry SR[CY] to form the result. " |
"The result is placed into general-purpose register rD.", |
"rD[31:0] <- rA[31:0] + rB[31:0]", |
"rD[63:0] <- rA[63:0] + rB[63:0]", |
"Integer Overflow", ORBIS32I,}, |
|
{"l.shrl32", "Shift Right Logical", |
"Immediate is combined with low-order 5 bits of general register rC " |
"in a bit-wise logical OR operation. The result specifies the number of " |
"bit positions the contents of general register rB are shifted right, " |
"inserting zeros into the high-order bits.", |
"b <- Immediate | rC\\rA[31-b:0] <- rB[31:b]\\rA[31-b:31] <- 0", |
"None", 1,}, |
{"l.sub", "Subtract Signed", |
"The contents of general-purpose register rB is subtracted from the contents " |
"of general-purpose register rA to form the result. The result is placed into " |
"general-purpose register rD.", |
"rD[31:0] <- rA[31:0] - rB[31:0]", |
"rD[63:0] <- rA[63:0] - rB[63:0]", |
"Integer Overflow", ORBIS32I,}, |
|
{"l.and32", "And", |
"The contents of general register rB are combined with the contents " |
"of general register rC in a bit-wise logical AND operation. The " |
"result is placed into general register rA.", |
"rA <- rB AND rC", |
"None", 1,}, |
{"l.sll", "Shift Left Logical", |
"General-purpose register rB specifies the number of " |
"bit positions the contents of general-purpose register rA are shifted left, " |
"inserting zeros into the low-order bits. Result is written into general-purpose " |
"rD.", |
"rD[31:rB] <- rA[31-rB:0]\\rD[rB-1:0] <- 0", |
"rD[63:rB] <- rA[63-rB:0]\\rD[rB-1:0] <- 0", |
"None", ORBIS32I,}, |
|
{"l.or32", "Or", |
"The contents of general register rB are combined with the contents " |
"of general register rC in a bit-wise logical OR operation. The " |
"result is placed into general register rA.", |
"rA <- rB OR rC", |
"None", 1,}, |
{"l.sra", "Shift Right Arithmetic", |
"General-purpose register rB specifies the number of " |
"bit positions the contents of general-purpose register rA are shifted right, " |
"sign-extending the high-order bits. Result is written into " |
"general-purpose register rD.", |
"rD[31-rB:0] <- rA[31:rB]\\rD[31:32-rB] <- rB[31]", |
"rD[63-rB:0] <- rA[63:rB]\\rD[63:64-rB] <- rB[63]", |
"None", ORBIS32I,}, |
|
{"l.xor32", "Exclusive Or", |
"The contents of general register rB are combined with the contents " |
"of general register rC in a bit-wise logical XOR operation. The " |
"result is placed into general register rA.", |
"rA <- rB XOR rC", |
"None", 1,}, |
{"l.srl", "Shift Right Logical", |
"General-purpose register rB specifies the number of " |
"bit positions the contents of general-purpose register rA are shifted right, " |
"inserting zeros into the high-order bits. Result is written into general-purpose " |
"register rD.", |
"rD[31-rB:0] <- rA[31:rB]\\rD[31:32-rB] <- 0", |
"rD[63-rB:0] <- rA[63:rB]\\rD[63:64-rB] <- 0", |
"None", ORBIS32I,}, |
|
{"l.xori16", "Exclusive Or Immediate Half Word", |
"Immediate is zero-extended and combined with the contents of general " |
"register rB in a bit-wise logical XOR operation. The result is " |
"placed into general register rA.", |
"rA <- rB XOR exts(Immediate)", "None", 3,}, |
{"l.ror", "Rotate Right", |
"General-purpose register rB specifies the number of " |
"bit positions the contents of general-purpose register rA are rotated right. " |
"Result is written into general-purpose register rD.", |
"rD[31-rB:0] <- rA[31:rB]\\rD[31:32-rB] <- rA[rB-1:0]", |
"rD[63-rB:0] <- rA[63:rB]\\rD[63:64-rB] <- rA[rB-1:0]", |
"None", ORBIS32II,}, |
|
{"l.muli32s", "Multiply Immediate Signed", |
"Immediate and the contents of general register rB are " |
"multiplied and the result is truncated to 32 bits and placed into " |
"general register rA.", |
"rA <- rB * Immediate", "None", 2,}, |
{"l.and", "And", |
"The contents of general-purpose register rA are combined with the contents " |
"of general-purpose register rB in a bit-wise logical AND operation. The " |
"result is placed into general-purpose register rD.", |
"rD[31:0] <- rA[31:0] AND rB[31:0]", |
"rD[63:0] <- rA[63:0] AND rB[63:0]", |
"None", ORBIS32I,}, |
|
{"l.mul32s", "Multiply Signed", |
"The contents of general register rB and the contents of general " |
"register rC are multiplied and the result is truncated to 32 " |
"bits and placed into general register rA. Both operands are treated " |
"as unsigned integers.", |
"rA <- rB * rC", "None", 2,}, |
{"l.or", "Or", |
"The contents of general-purpose register rA are combined with the contents " |
"of general-purpose register rB in a bit-wise logical OR operation. The " |
"result is placed into general-purpose register rD.", |
"rD[31:0] <- rA[31:0] OR rB[31:0]", |
"rD[63:0] <- rA[63:0] OR rB[63:0]", |
"None", ORBIS32I,}, |
|
{"l.mul32u", "Multiply Unsigned", |
"The contents of general register rB and the contents of general " |
"register rC are multiplied and the result is truncated to 32 " |
"bits and placed into general register rA. Both operands are treated " |
"as unsigned integers.", |
"rA <- rB * rC", "None", 2,}, |
{"l.xor", "Exclusive Or", |
"The contents of general-purpose register rA are combined with the contents " |
"of general-purpose register rB in a bit-wise logical XOR operation. The " |
"result is placed into general-purpose register rD.", |
"rD[31:0] <- rA[31:0] XOR rB[31:0]", |
"rD[63:0] <- rA[63:0] XOR rB[63:0]", |
"None", ORBIS32I,}, |
|
{"l.div32s", "Divide Signed", |
"The contents of general register rB are divided by the contents of " |
"general register rC and the result is placed into general register " |
"rA. Both operands are treated as signed integers. A divisor " |
{"l.mac", "Multiply Signed and Accumulate", |
"The contents of general-purpose register rA and the contents of general-purpose " |
"register rB are multiplied and the result is truncated to 32 bits and added " |
"to the special-purpose registers MACHI and MACLO. " |
"All operands are treated as signed integers.", |
"M[31:0] <- rA[31:0] * rB[31:0]\\MACHI[31:0]MACLO[31:0] <- M[31:0] + MACHI[31:0]MACLO[31:0]", |
"M[31:0] <- rA[63:0] * rB[63:0]\\MACHI[31:0]MACLO[31:0] <- M[31:0] + MACHI[31:0]MACLO[31:0]", |
"None", ORBIS32II,}, |
|
{"l.mul", "Multiply Signed", |
"The contents of general-purpose register rA and the contents of general-purpose " |
"register rB are multiplied and the result is truncated to destination register width " |
"and placed into general-purpose register rD. " |
"Both operands are treated as unsigned integers.", |
"rD[31:0] <- rA[31:0] * rB[31:0]", |
"rD[63:0] <- rA[63:0] * rB[63:0]", |
"None", ORBIS32I,}, |
|
{"l.mulu", "Multiply Unsigned", |
"The contents of general-purpose register rA and the contents of general-purpose " |
"register rB are multiplied and the result is truncated to destination register width " |
"and placed into general-purpose register rD. " |
"Both operands are treated as unsigned integers.", |
"rD[31:0] <- rA[31:0] * rB[31:0]", |
"rD[63:0] <- rA[63:0] * rB[63:0]", |
"None", ORBIS32I,}, |
|
{"l.div", "Divide Signed", |
"The contents of general-purpose register rA are divided by the contents of " |
"general-purpose register rB and the result is placed into general-purpose register " |
"rD. Both operands are treated as signed integers. A divide by zero " |
"flag is set when the divisor is zero.", |
"rA <- rB / rC", "None", 3,}, |
"rD[31:0] <- rA[31:0] / rB[31:0]", |
"rD[63:0] <- rA[63:0] / rB[63:0]", |
"None", ORBIS32II,}, |
|
{"l.div32u", "Divide Unsigned", |
"The contents of general register rB are divided by the contents of " |
"general register rC and the result is placed into general register " |
"rA. Both operands are treated as unsigned integers. A divisor " |
{"l.divu", "Divide Unsigned", |
"The contents of general-purpose register rA are divided by the contents of " |
"general-purpose register rA and the result is placed into general-purpose register " |
"rD. Both operands are treated as unsigned integers. A divide by zero " |
"flag is set when the divisor is zero.", |
"rA <- rB / rC", "None", 3,}, |
"rD[31:0] <- rA[31:0] / rB[31:0]", |
"rD[63:0] <- rA[63:0] / rB[63:0]", |
"None", ORBIS32II,}, |
|
{"h.sfeq32", "Set Flag if Equal", |
"The contents of general register rA and the contents of general " |
{"l.sfeq", "Set Flag if Equal", |
"The contents of general-purpose register rA and the contents of general-purpose " |
"register rB are compared. If the two registers are equal, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- rA == rB", "None", 1,}, |
"flag <- rA[31:0] == rB[31:0]", |
"flag <- rA[63:0] == rB[63:0]", |
"None", ORBIS32I,}, |
|
{"h.sfne32", "Set Flag if Not Equal", |
"The contents of general register rA and the contents of general " |
{"l.sfne", "Set Flag if Not Equal", |
"The contents of general-purpose register rA and the contents of general-purpose " |
"register rB are compared. If the two registers are not equal, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- rA != rB", "None", 1,}, |
"flag <- rA[31:0] != rB[31:0]", |
"flag <- rA[63:0] != rB[63:0]", |
"None", ORBIS32I,}, |
|
{"h.sfgt32s", "Set Flag if Greater Than Signed", |
"The contents of general register rA and the contents of general " |
{"l.sfgts", "Set Flag if Greater Than Signed", |
"The contents of general-purpose register rA and the contents of general-purpose " |
"register rB are compared as signed integers. If the contents " |
"of the first register are greater than the contents of the second " |
"register, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- rA > rB", "None", 1,}, |
"flag <- rA[31:0] > rB[31:0]", |
"flag <- rA[63:0] > rB[63:0]", |
"None", ORBIS32I,}, |
|
{"h.sfge32s", "Set Flag if Greater or Equal Than Signed", |
"The contents of general register rA and the contents of general " |
{"l.sfges", "Set Flag if Greater or Equal Than Signed", |
"The contents of general-purpose register rA and the contents of general-purpose " |
"register rB are compared as signed integers. If the contents " |
"of the first register are greater or equal than the contents of the second " |
"register, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- rA >= rB", "None", 1,}, |
"flag <- rA[31:0] >= rB[31:0]", |
"flag <- rA[63:0] >= rB[63:0]", |
"None", ORBIS32I,}, |
|
{"h.sflt32s", "Set Flag if Less Than Signed", |
"The contents of general register rA and the contents of general " |
{"l.sflts", "Set Flag if Less Than Signed", |
"The contents of general-purpose register rA and the contents of general-purpose " |
"register rB are compared as signed integers. If the contents " |
"of the first register are less than the contents of the second " |
"register, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- rA < rB", "None", 1,}, |
"flag <- rA[31:0] < rB[31:0]", |
"flag <- rA[63:0] < rB[63:0]", |
"None", ORBIS32I,}, |
|
{"h.sfle32s", "Set Flag if Less or Equal Than Signed", |
"The contents of general register rA and the contents of general " |
{"l.sfles", "Set Flag if Less or Equal Than Signed", |
"The contents of general-purpose register rA and the contents of general-purpose " |
"register rB are compared as signed integers. If the contents " |
"of the first register are less or equal than the contents of the second " |
"register, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- rA <= rB", "None", 1,}, |
"flag <- rA[31:0] <= rB[31:0]", |
"flag <- rA[63:0] <= rB[63:0]", |
"None", ORBIS32I,}, |
|
{"h.sfgt32u", "Set Flag if Greater Than Unsigned", |
"The contents of general register rA and the contents of general " |
{"l.sfgtu", "Set Flag if Greater Than Unsigned", |
"The contents of general-purpose register rA and the contents of general-purpose " |
"register rB are compared as unsigned integers. If the contents " |
"of the first register are greater than the contents of the second " |
"register, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- rA > rB", "None", 1,}, |
"flag <- rA[31:0] > rB[31:0]", |
"flag <- rA[63:0] > rB[63:0]", |
"None", ORBIS32I,}, |
|
{"h.sfge32u", "Set Flag if Greater or Equal Than Unsigned", |
"The contents of general register rA and the contents of general " |
{"l.sfgeu", "Set Flag if Greater or Equal Than Unsigned", |
"The contents of general-purpose register rA and the contents of general-purpose " |
"register rB are compared as unsigned integers. If the contents " |
"of the first register are greater or equal than the contents of the second " |
"register, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- rA >= rB", "None", 1,}, |
"flag <- rA[31:0] >= rB[31:0]", |
"flag <- rA[63:0] >= rB[63:0]", |
"None", ORBIS32I,}, |
|
{"h.sflt32u", "Set Flag if Less Than Unsigned", |
"The contents of general register rA and the contents of general " |
{"l.sfltu", "Set Flag if Less Than Unsigned", |
"The contents of general-purpose register rA and the contents of general-purpose " |
"register rB are compared as unsigned integers. If the contents " |
"of the first register are less than the contents of the second " |
"register, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- rA < rB", "None", 1,}, |
"flag <- rA[31:0] < rB[31:0]", |
"flag <- rA[63:0] < rB[63:0]", |
"None", ORBIS32I,}, |
|
{"h.sfle32u", "Set Flag if Less or Equal Than Unsigned", |
"The contents of general register rA and the contents of general " |
{"l.sfleu", "Set Flag if Less or Equal Than Unsigned", |
"The contents of general-purpose register rA and the contents of general-purpose " |
"register rB are compared as unsigned integers. If the contents " |
"of the first register are less or equal than the contents of the second " |
"register, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- rA <= rB", "None", 1,}, |
"flag <- rA[31:0] <= rB[31:0]", |
"flag <- rA[63:0] <= rB[63:0]", |
"None", ORBIS32I,}, |
|
{"l.sfeqi", "Set Flag if Equal Immediate", |
"The contents of general-purpose register rA and sign-extended immediate " |
"are compared. If the two registers are equal, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- rA[31:0] == rB[31:0]", |
"flag <- rA[63:0] == rB[63:0]", |
"None", ORBIS32II,}, |
|
{"l.mtsr", "Move To Special Register", |
"The contents of general register rA are moved into special register " |
"rS.", |
"rS <- rA", "None", 4,}, |
{"l.sfnei", "Set Flag if Not Equal Immediate", |
"The contents of general-purpose register rA and " |
"sign-extended immediate are compared. If the two registers are not equal, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- rA[31:0] != rB[31:0]", |
"flag <- rA[63:0] != rB[63:0]", |
"None", ORBIS32II,}, |
|
{"l.mfsr", "Move From Special Register", |
"The contents of special register rS are moved into general register " |
"rA.", |
"rA <- rS", "None", 4,}, |
{"l.sfgtsi", "Set Flag if Greater Than Immediate Signed", |
"The contents of general-purpose register rA and " |
"sign-extended immediate are compared as signed integers. If the contents " |
"of the first register are greater than the contents of the second " |
"register, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- rA[31:0] > rB[31:0]", |
"flag <- rA[63:0] > rB[63:0]", |
"None", ORBIS32II,}, |
|
{"h.mov32", "Move", |
"The contents of general register rB are moved into general register " |
"rA.", |
"rA <- rB", "None", 2,}, |
{"l.sfgesi", "Set Flag if Greater or Equal Than Immediate Signed", |
"The contents of general-purpose register rA and " |
"sign-extended immediate are compared as signed integers. If the contents " |
"of the first register are greater or equal than the contents of the second " |
"register, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- rA[31:0] >= rB[31:0]", |
"flag <- rA[63:0] >= rB[63:0]", |
"None", ORBIS32II,}, |
|
{"h.immch32s", "Immediate Byte Signed", |
"8 bit immediate is sign-extended to 32 bits and placed into general " |
"register rA.", |
"rA <- exts(Immediate)", "None", 2,}, |
{"l.sfltsi", "Set Flag if Less Than Immediate Signed", |
"The contents of general-purpose register rA and " |
"sign-extended immediate are compared as signed integers. If the contents " |
"of the first register are less than the contents of the second " |
"register, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- rA[31:0] < rB[31:0]", |
"flag <- rA[63:0] < rB[63:0]", |
"None", ORBIS32II,}, |
|
{"l.immlo16u", "Immediate Low-Order Half Word Unsigned", |
"16 bit immediate is placed into low-order 16 bits of general " |
"register rA.", |
"rA[15:0] <- Immediate", "None", 1,}, |
{"l.sflesi", "Set Flag if Less or Equal Than Immediate Signed", |
"The contents of general-purpose register rA and " |
"sign-extended immediate are compared as signed integers. If the contents " |
"of the first register are less or equal than the contents of the second " |
"register, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- rA[31:0] <= rB[31:0]", |
"flag <- rA[63:0] <= rB[63:0]", |
"None", ORBIS32II,}, |
|
{"l.immhi16u", "Immediate High-Order Half Word Unsigned", |
"16 bit immediate is placed into high-order 16 bits of general " |
"register rA.", |
"rA[31:16] <- Immediate", "None", 1,}, |
{"l.sfgtui", "Set Flag if Greater Than Immediate Unsigned", |
"The contents of general-purpose register rA and " |
"zero-extended immediate are compared as unsigned integers. If the contents " |
"of the first register are greater than the contents of the second " |
"register, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- rA[31:0] > rB[31:0]", |
"flag <- rA[63:0] > rB[63:0]", |
"None", ORBIS32II,}, |
|
{"l.sfgeui", "Set Flag if Greater or Equal Than Immediate Unsigned", |
"The contents of general-purpose register rA and " |
"zero-extended immediate are compared as unsigned integers. If the contents " |
"of the first register are greater or equal than the contents of the second " |
"register, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- rA[31:0] >= rB[31:0]", |
"flag <- rA[63:0] >= rB[63:0]", |
"None", ORBIS32II,}, |
|
{"l.sfltui", "Set Flag if Less Than Immediate Unsigned", |
"The contents of general-purpose register rA and " |
"zero-extended immediate are compared as unsigned integers. If the contents " |
"of the first register are less than the contents of the second " |
"register, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- rA[31:0] < rB[31:0]", |
"flag <- rA[63:0] < rB[63:0]", |
"None", ORBIS32II,}, |
|
{"l.sfleui", "Set Flag if Less or Equal Than Immediate Unsigned", |
"The contents of general-purpose register rA and " |
"zero-extended immediate are compared as unsigned integers. If the contents " |
"of the first register are less or equal than the contents of the second " |
"register, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- rA[31:0] <= rB[31:0]", |
"flag <- rA[63:0] <= rB[63:0]", |
"None", ORBIS32II,}, |
|
{"l.mtsr", "Move To Special-Purpose Register", |
"The contents of general-purpose register rB are moved into special register " |
"identified by the sum of general-purpose register rA and zero-extended immediate.", |
"spr(rA+extz(Immediate)) <- rA[31:0]", |
"spr(rA+extz(Immediate)) <- rA[31:0]", |
"None", ORBIS32I,}, |
|
{"l.mfsr", "Move From Special-Purpose Register", |
"The contents of special register identified by the sum of general-purpose rA and " |
"zero-extended immediate are moved into general-purpose register rD.", |
"rD[31:0] <- spr(rA+extz(Immediate))", |
"rD[63:0] <- spr(rA+extz(Immediate))", |
"None", ORBIS32I,}, |
|
{"l.nop", "No Operation", |
"This instruction does not do anything except it takes at least one " |
"clock cycle to complete. It is often used to fill delay slot gaps.", |
"", |
"", |
"None", ORBIS32I,}, |
|
{"l.movhi", "Move Immediate High", |
"16-bit immediate is zero-extended, shifted left by 16 bits and placed " |
"into general-purpose register rD.", |
"rA[31:0] <- extz(Immediate) << 16", |
"rA[63:0] <- extz(Immediate) << 16", |
"None", ORBIS32I,}, |
|
{"l.bf", "Branch if Flag", |
"The immediate is shifted left two bits, sign-extended to " |
"32 bits and then added to the address of the delay slot. The result " |
"program counter width and then added to the address of the delay slot. The result " |
"is effective address of the branch. If the compare flag is set, " |
"then the program branches " |
"to EA with a delay of one 32 bit or two 16 bit instructions.", |
"to EA with a delay of one instruction.", |
"EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag set", |
"None", 1,}, |
"EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag set", |
"None", ORBIS32I,}, |
|
{"l.bnf", "Branch if No Flag", |
"The immediate is shifted left two bits, sign-extended to " |
"32 bits and then added to the address of the delay slot. The result " |
"program counter width and then added to the address of the delay slot. The result " |
"is effective address of the branch. If the compare flag is cleared, " |
"then the program branches " |
"to EA with a delay of one 32 bit or two 16 bit instructions.", |
"to EA with a delay of one instruction.", |
"EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag cleared", |
"None", 1,}, |
|
{"h.bf", "Branch if Flag", |
"The immediate is shifted left two bits, sign-extended to " |
"32 bits and then added to the address of the delay slot. The result " |
"is effective address of the branch. If the compare flag is set, " |
"then the program branches " |
"to EA with a delay of one 32 bit or two 16 bit instructions.", |
"EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag set", |
"None", 2,}, |
|
{"h.bnf", "Branch if No Flag", |
"The immediate is shifted left two bits, sign-extended to " |
"32 bits and then added to the address of the delay slot. The result " |
"is effective address of the branch. If the compare flag is cleared, " |
"then the program branches " |
"to EA with a delay of one 32 bit or two 16 bit instructions.", |
"EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag cleared", |
"None", 2,}, |
"None", ORBIS32I,}, |
|
{"l.jal", "Jump and Link", |
"The immediate is shifted left two bits, sign-extended to " |
"32 bits and then added to the address of the delay slot. The result " |
"program counter width and then added to the address of the delay slot. The result " |
"is effective address of the jump. The program unconditionally jumps " |
"to EA with a delay of one 32 bit or two 16 bit instructions. The " |
"to EA with a delay of one instruction. The " |
"address of the instruction after the delay slot is placed in the " |
"link register. ", |
"PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4", "None", 1,}, |
"PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4", |
"PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4", |
"None", ORBIS32I,}, |
|
{"l.j", "Jump", |
"The immediate is shifted left two bits, sign-extended to " |
"32 bits and then added to the address of the delay slot. The result " |
"program counter width and then added to the address of the delay slot. The result " |
"is effective address of the jump. The program unconditionally jumps " |
"to EA with a delay of one 32 bit or two 16 bit instructions.", |
"PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4", "None", 1,}, |
"to EA with a delay of one instruction.", |
"PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4", |
"PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4", |
"None", ORBIS32I,}, |
|
{"h.j", "Jump", |
"The immediate is shifted left two bits, sign-extended to " |
"32 bits and then added to the address of the delay slot. The result " |
{"l.jalr", "Jump and Link Register", |
"The contents of general-purpose register rB " |
"is effective address of the jump. The program unconditionally jumps " |
"to EA with a delay of one 32 bit or two 16 bit instructions.", |
"PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4", "None", 2,}, |
|
{"h.jal", "Jump and Link", |
"The immediate is shifted left two bits, sign-extended to " |
"32 bits and then added to the address of the delay slot. The result " |
"is effective address of the jump. The program unconditionally jumps " |
"to EA with a delay of one 32 bit or two 16 bit instructions. The " |
"to EA with a delay of one instruction. The " |
"address of the instruction after the delay slot is placed in the " |
"link register. ", |
"PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4", "None", 2,}, |
"link register.", |
"PC <- rB\\LR <- DelayInsnAddr + 4", |
"PC <- rB\\LR <- DelayInsnAddr + 4", |
"None", ORBIS32I,}, |
|
{"h.jalr", "Jump and Link Register", |
"The contents of general register rA " |
{"l.jr", "Jump Register", |
"The contents of general-purpose register rB " |
"is effective address of the jump. The program unconditionally jumps " |
"to EA with a delay of one 32 bit or two 16 bit instructions. The " |
"address of the instruction after the delay slot is placed in the " |
"link register. ", |
"PC <- rA\\LR <- DelayInsnAddr + 4", "None", 1,}, |
"to EA with a delay of one instruction.", |
"PC <- rB", |
"PC <- rB", |
"None", ORBIS32I,}, |
|
{"l.illegal", "Illegal instruction", |
"The result of this instruction is always an illegal instruction " |
"exception.", |
"PC <- address of illegal instruction exception handler", "None", 1,}, |
{"l.sys", "System Call", |
"Execution of system call instruction results in the system call " |
"exception. System calls exception is a request to the operating system " |
"to provide certain services. Immediate specifies which system service " |
"is required.", |
"system-call-exception(K)", |
"system-call-exception(K)", |
"None", ORBIS32I,}, |
|
{"h.nop", "No Operation", |
"This instruction does not do anything except it takes at least one " |
"clock cycle to complete. It is usually used to fill gaps between " |
"16 bit and 32 bit instructions.", |
"", "None", 1,}, |
{"l.rfe", "Return From Exception", |
"Execution of this instruction restores the state of the processor prior to " |
"the exception.", |
"state_restore()", |
"state_restore()", |
"None", ORBIS32I,}, |
|
{"h.sched", "Schedule", |
"Immediate carries static scheduling information about instruction " |
"scheduling. This information is generated by an optimizing compiler.", |
"", "None", 3,}, |
/*** ORFPX32 ***/ |
|
{"h.movi32", "Move 32 bit Immediate", |
"For simulator. Obsolete", "N/A", "N/A", 0,}, |
{"lf.add.s", "Add Floating-Point Single-Precision", |
"The contents of vector/floating-point register vfrA is added to the contents " |
"of vector/floating-point register vfrB to form the result. The result is placed into " |
"vector/floating-point register vfrD.", |
"vfrD[31:0] <- vfrA[31:0] + vfrB[31:0]", |
"", |
"", ORFPX32I,}, |
|
{"simrdtsc", "Simulate Read Timer", |
"For simulator. Obsolete.", "N/A", "N/A", 0,}, |
{"lf.sub.s", "Subtract Floating-Point Single-Precision", |
"The contents of vector/floating-point register vfrB is subtracted from the contents " |
"of vector/floating-point register vfrA to form the result. The result is placed into " |
"vector/floating-point register vfrD.", |
"vfrD[31:0] <- vfrA[31:0] - vfrB[31:0]", |
"", |
"", ORFPX32I,}, |
|
{"simprintf", "Simulate printf", |
"For simulator. Obsolete.", "N/A", "N/A", 0,}, |
{"lf.mul.s", "Multiply Floating-Point Single-Precision", |
"The contents of vector/floating-point register vfrA is multiplied by the contents " |
"of vector/floating-point register vfrB to form the result. The result is placed into " |
"vector/floating-point register vfrD.", |
"vfrD[31:0] <- vfrA[31:0] * vfrB[31:0]", |
"", |
"", ORFPX32I,}, |
|
{"l.dcbf", "Data Cache Block Flush", |
"TBD", "", "", 5,}, |
{"lf.div.s", "Divide Floating-Point Single-Precision", |
"The contents of vector/floating-point register vfrA is divided by the contents " |
"of vector/floating-point register vfrB to form the result. The result is placed into " |
"vector/floating-point register vfrD.", |
"vfrD[31:0] <- vfrA[31:0] / vfrB[31:0]", |
"", |
"", ORFPX32II,}, |
|
{"l.dcbt", "Data Cache Block Touch", |
"TBD", "", "", 5,}, |
{"lf.rem.s", "Remainder Floating-Point Single-Precision", |
"The contents of vector/floating-point register vfrA is divided by the contents " |
"of vector/floating-point register vfrB and remainder is used as the result. The result is placed into " |
"vector/floating-point register vfrD.", |
"vfrD[31:0] <- vfrA[31:0] % vfrB[31:0]", |
"", |
"", ORFPX32II,}, |
|
{"l.dcbi", "Data Cache Block Invalidate", |
"TBD", "", "", 5,}, |
{"lf.madd.s", "Multiply and Add Floating-Point Single-Precision", |
"The contents of vector/floating-point register vfrA is multiplied by the contents " |
"of vector/floating-point register vfrB and added to special-purpose register " |
"FPMADDLO/FPMADDHI.", |
"FPMADDHI[31:0]FPMADDLO[31:0] <- vfrA[31:0] * vfrB[31:0] + FPMADDHI[31:0]FPMADDLO[31:0]", |
"", |
"", ORFPX32II,}, |
|
{"l.dcia", "Data Cache Invalidate All", |
"TBD", "", "", 5,}, |
{"lf.sfeq.s", "Set Flag if Equal Floating-Point Single-Precision", |
"The contents of vector/floating-point register vfrA and the contents of " |
"vector/floating-point register vfrB are compared. If the two registers are equal, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- vfrA[31:0] == vfrB[31:0]", |
"", |
"None", ORFPX32I,}, |
|
{"l.dcfa", "Data Cache Flush All", |
"TBD", "", "", 5,}, |
{"lf.sfne.s", "Set Flag if Not Equal Floating-Point Single-Precision", |
"The contents of vector/floating-point register vfrA and the contents of " |
"vector/floating-point register vfrB are compared. If the two registers are not equal, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- vfrA[31:0] != vfrB[31:0]", |
"", |
"None", ORFPX32I,}, |
|
{"l.tlbia", "TLB Invalidate All", |
"TBD", "", "", 6,}, |
{"lf.sfgt.s", "Set Flag if Greater Than Floating-Point Single-Precision", |
"The contents of vector/floating-point register vfrA and the contents of " |
"vector/floating-point register vfrB are compared. If first register is greater than " |
"second register, then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- vfrA[31:0] > vfrB[31:0]", |
"", |
"None", ORFPX32I,}, |
|
{"", "", "", "", "", 0} |
{"lf.sfge.s", "Set Flag if Greater or Equal Than Floating-Point Single-Precision", |
"The contents of vector/floating-point register vfrA and the contents of " |
"vector/floating-point register vfrB are compared. If first register is greater " |
"or equal than the second register, then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- vfrA[31:0] >= vfrB[31:0]", |
"", |
"None", ORFPX32I,}, |
|
{"lf.sflt.s", "Set Flag if Less Than Floating-Point Single-Precision", |
"The contents of vector/floating-point register vfrA and the contents of " |
"vector/floating-point register vfrB are compared. If first register is less than " |
"second register, then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- vfrA[31:0] < vfrB[31:0]", |
"", |
"None", ORFPX32I,}, |
|
{"lf.sfle.s", "Set Flag if Less or Equal Than Floating-Point Single-Precision", |
"The contents of vector/floating-point register vfrA and the contents of " |
"vector/floating-point register vfrB are compared. If first register is less " |
"or equal than the second register, then the compare flag is set; otherwise the compare flag is cleared.", |
"flag <- vfrA[31:0] <= vfrB[31:0]", |
"", |
"None", ORFPX32I,}, |
|
{"lf.ftoi.s", "Floating-Point Single-Precision To Integer", |
"The contents of vector/floating-point register vfrA are converted to integer " |
"and stored into general-purpose register rD.", |
"rD[31:0] <- ftoi(vfrA[31:0])", |
"", |
"None", ORFPX32I,}, |
|
{"lf.ftovh.d", "Floating-Point Single-Precision To Vector Half-Word", |
"The contents of vector/floating-point register vfrA are converted to half-word integer " |
"and stored into vector/floating-point register vfrD.", |
"", |
"vfrD[31:0] <- ftoi(vfrA[63:0])\\" |
"vfrD[63:32] <- 0", |
"None", ORFPX32I,}, |
|
{"lf.itof.s", "Integer To Floating-Point Single-Precision", |
"The contents of general-purpose register rA are converted to single-precision " |
"floating-point number and stored into vector/floating-point register vfrD.", |
"vfrD[31:0] <- itof(rA[31:0])", |
"", |
"None", ORFPX32I,}, |
|
/*** ORFPX64 ***/ |
|
{"lf.add.d", "Add Floating-Point Double-Precision", |
"The contents of vector/floating-point register vfrA is added to the contents " |
"of vector/floating-point register vfrB to form the result. The result is placed into " |
"vector/floating-point register vfrD.", |
"", |
"vfrD[63:0] <- vfrA[63:0] + vfrB[63:0]", |
"", ORFPX64I,}, |
|
{"lf.sub.d", "Subtract Floating-Point Double-Precision", |
"The contents of vector/floating-point register vfrB is subtracted from the contents " |
"of vector/floating-point register vfrA to form the result. The result is placed into " |
"vector/floating-point register vfrD.", |
"", |
"vfrD[63:0] <- vfrA[63:0] - vfrB[63:0]", |
"", ORFPX64I,}, |
|
{"lf.mul.d", "Multiply Floating-Point Double-Precision", |
"The contents of vector/floating-point register vfrA is multiplied by the contents " |
"of vector/floating-point register vfrB to form the result. The result is placed into " |
"vector/floating-point register vfrD.", |
"", |
"vfrD[63:0] <- vfrA[63:0] * vfrB[63:0]", |
"", ORFPX64I,}, |
|
{"lf.div.d", "Divide Floating-Point Double-Precision", |
"The contents of vector/floating-point register vfrA is divided by the contents " |
"of vector/floating-point register vfrB to form the result. The result is placed into " |
"vector/floating-point register vfrD.", |
"", |
"vfrD[63:0] <- vfrA[63:0] / vfrB[63:0]", |
"", ORFPX64II,}, |
|
{"lf.rem.d", "Remainder Floating-Point Double-Precision", |
"The contents of vector/floating-point register vfrA is divided by the contents " |
"of vector/floating-point register vfrB and remainder is used as the result. The result is placed into " |
"vector/floating-point register vfrD.", |
"", |
"vfrD[63:0] <- vfrA[63:0] % vfrB[63:0]", |
"", ORFPX64II,}, |
|
{"lf.madd.d", "Multiply and Add Floating-Point Double-Precision", |
"The contents of vector/floating-point register vfrA is multiplied by the contents " |
"of vector/floating-point register vfrB and added to special-purpose register " |
"FPMADDLO/FPMADDHI.", |
"", |
"FPMADDHI[31:0]FPMADDLO[31:0] <- vfrA[63:0] * vfrB[63:0] + FPMADDHI[31:0]FPMADDLO[31:0]", |
"", ORFPX64II,}, |
|
{"lf.sfeq.d", "Set Flag if Equal Floating-Point Double-Precision", |
"The contents of vector/floating-point register vfrA and the contents of " |
"vector/floating-point register vfrB are compared. If the two registers are equal, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"", |
"flag <- vfrA[63:0] == vfrB[63:0]", |
"None", ORFPX64I,}, |
|
{"lf.sfne.d", "Set Flag if Not Equal Floating-Point Double-Precision", |
"The contents of vector/floating-point register vfrA and the contents of " |
"vector/floating-point register vfrB are compared. If the two registers are not equal, " |
"then the compare flag is set; otherwise the compare flag is cleared.", |
"", |
"flag <- vfrA[63:0] != vfrB[63:0]", |
"None", ORFPX64I,}, |
|
{"lf.sfgt.d", "Set Flag if Greater Than Floating-Point Double-Precision", |
"The contents of vector/floating-point register vfrA and the contents of " |
"vector/floating-point register vfrB are compared. If first register is greater than " |
"second register, then the compare flag is set; otherwise the compare flag is cleared.", |
"", |
"flag <- vfrA[63:0] > vfrB[63:0]", |
"None", ORFPX64I,}, |
|
{"lf.sfge.d", "Set Flag if Greater or Equal Than Floating-Point Double-Precision", |
"The contents of vector/floating-point register vfrA and the contents of " |
"vector/floating-point register vfrB are compared. If first register is greater " |
"or equal than the second register, then the compare flag is set; otherwise the compare flag is cleared.", |
"", |
"flag <- vfrA[63:0] >= vfrB[63:0]", |
"None", ORFPX64I,}, |
|
{"lf.sflt.d", "Set Flag if Less Than Floating-Point Double-Precision", |
"The contents of vector/floating-point register vfrA and the contents of " |
"vector/floating-point register vfrB are compared. If first register is less than " |
"second register, then the compare flag is set; otherwise the compare flag is cleared.", |
"", |
"flag <- vfrA[63:0] < vfrB[63:0]", |
"None", ORFPX64I,}, |
|
{"lf.sfle.d", "Set Flag if Less or Equal Than Floating-Point Double-Precision", |
"The contents of vector/floating-point register vfrA and the contents of " |
"vector/floating-point register vfrB are compared. If first register is less " |
"or equal than the second register, then the compare flag is set; otherwise the compare flag is cleared.", |
"", |
"flag <- vfrA[363:0] <= vfrB[63:0]", |
"None", ORFPX64I,}, |
|
{"lf.ftoi.d", "Floating-Point Double-Precision To Integer", |
"The contents of vector/floating-point register vfrA are converted to integer " |
"and stored into general-purpose register rD.", |
"", |
"rD[63:0] <- ftoi(vfrA[63:0])", |
"None", ORFPX64I,}, |
|
{"lf.ftovh.d", "Floating-Point Double-Precision To Vector Half-Word", |
"The contents of vector/floating-point register vfrA are converted to half-word integer " |
"and stored into vector/floating-point register vfrD.", |
"", |
"vfrD[63:0] <- ftoi(vfrA[63:0])", |
"None", ORFPX64I,}, |
|
{"lf.itof.d", "Integer To Floating-Point Double-Precision", |
"The contents of general-purpose register rA are converted to Double-precision " |
"floating-point number and stored into vector/floating-point register vfrD.", |
"", |
"vfrD[63:0] <- itof(rA[63:0])", |
"None", ORFPX64I,}, |
|
/*** ORVDX64 ***/ |
|
{"lv.all_eq.b", "Vector Byte Elements All Equal", |
"All byte elements of vector/floating-point register vfrA are compared " |
"to byte elements of vector/floating-point register vfrB. Compare flag is " |
"set if all corresponding elements are equal; otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[7:0] == vfrB[7:0] \\" |
"\tvfrA[15:8] == vfrB[15:8] \\" |
"\tvfrA[23:16] == vfrB[23:16] \\" |
"\tvfrA[31:24] == vfrB[31:24] \\" |
"\tvfrA[39:32] == vfrB[39:32] \\" |
"\tvfrA[47:40] == vfrB[47:40] \\" |
"\tvfrA[55:48] == vfrB[55:48] \\" |
"\tvfrA[63:56] == vfrB[63:56]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.all_eq.h", "Vector Half-Word Elements All Equal", |
"All half-word elements of vector/floating-point register vfrA are compared " |
"to half-word elements of vector/floating-point register vfrB. Compare flag is " |
"set if all corresponding elements are equal; otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[15:0] == vfrB[15:0] \\" |
"\tvfrA[31:16] == vfrB[31:16] \\" |
"\tvfrA[47:32] == vfrB[47:32] \\" |
"\tvfrA[63:48] == vfrB[63:48]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.all_ge.b", "Vector Byte Elements All Greater or Equal Than", |
"All byte elements of vector/floating-point register vfrA are compared " |
"to byte elements of vector/floating-point register vfrB. Compare flag is " |
"set if all elements of vfrA are greater or equal than elements of vfrB;" |
"otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[7:0] >= vfrB[7:0] \\" |
"\tvfrA[15:8] >= vfrB[15:8] \\" |
"\tvfrA[23:16] >= vfrB[23:16] \\" |
"\tvfrA[31:24] >= vfrB[31:24] \\" |
"\tvfrA[39:32] >= vfrB[39:32] \\" |
"\tvfrA[47:40] >= vfrB[47:40] \\" |
"\tvfrA[55:48] >= vfrB[55:48] \\" |
"\tvfrA[63:56] >= vfrB[63:56]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.all_ge.h", "Vector Half-Word Elements All Greater or Equal Than", |
"All half-word elements of vector/floating-point register vfrA are compared " |
"to half-word elements of vector/floating-point register vfrB. Compare flag is " |
"set if all elements of vfrA are greater or equal than elements of vfrB;" |
"otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[15:0] >= vfrB[15:0] \\" |
"\tvfrA[31:16] >= vfrB[31:16] \\" |
"\tvfrA[47:32] >= vfrB[47:32] \\" |
"\tvfrA[63:48] >= vfrB[63:48]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.all_gt.b", "Vector Byte Elements All Greater Than", |
"All byte elements of vector/floating-point register vfrA are compared " |
"to byte elements of vector/floating-point register vfrB. Compare flag is " |
"set if all elements of vfrA are greater than elements of vfrB;" |
"otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[7:0] > vfrB[7:0] \\" |
"\tvfrA[15:8] > vfrB[15:8] \\" |
"\tvfrA[23:16] > vfrB[23:16] \\" |
"\tvfrA[31:24] > vfrB[31:24] \\" |
"\tvfrA[39:32] > vfrB[39:32] \\" |
"\tvfrA[47:40] > vfrB[47:40] \\" |
"\tvfrA[55:48] > vfrB[55:48] \\" |
"\tvfrA[63:56] > vfrB[63:56]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.all_gt.h", "Vector Half-Word Elements All Greater Than", |
"All half-word elements of vector/floating-point register vfrA are compared " |
"to half-word elements of vector/floating-point register vfrB. Compare flag is " |
"set if all elements of vfrA are greater than elements of vfrB;" |
"otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[15:0] > vfrB[15:0] \\" |
"\tvfrA[31:16] > vfrB[31:16] \\" |
"\tvfrA[47:32] > vfrB[47:32] \\" |
"\tvfrA[63:48] > vfrB[63:48]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.all_lt.b", "Vector Byte Elements All Less Than", |
"All byte elements of vector/floating-point register vfrA are compared " |
"to byte elements of vector/floating-point register vfrB. Compare flag is " |
"set if all elements of vfrA are less than elements of vfrB;" |
"otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[7:0] < vfrB[7:0] \\" |
"\tvfrA[15:8] < vfrB[15:8] \\" |
"\tvfrA[23:16] < vfrB[23:16] \\" |
"\tvfrA[31:24] < vfrB[31:24] \\" |
"\tvfrA[39:32] < vfrB[39:32] \\" |
"\tvfrA[47:40] < vfrB[47:40] \\" |
"\tvfrA[55:48] < vfrB[55:48] \\" |
"\tvfrA[63:56] < vfrB[63:56]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.all_lt.h", "Vector Half-Word Elements All Less Than", |
"All half-word elements of vector/floating-point register vfrA are compared " |
"to half-word elements of vector/floating-point register vfrB. Compare flag is " |
"set if all elements of vfrA are less than elements of vfrB;" |
"otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[15:0] < vfrB[15:0] \\" |
"\tvfrA[31:16] < vfrB[31:16] \\" |
"\tvfrA[47:32] < vfrB[47:32] \\" |
"\tvfrA[63:48] < vfrB[63:48]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.all_le.b", "Vector Byte Elements All Less or Equal Than", |
"All byte elements of vector/floating-point register vfrA are compared " |
"to byte elements of vector/floating-point register vfrB. Compare flag is " |
"set if all elements of vfrA are less or equal than elements of vfrB;" |
"otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[7:0] <= vfrB[7:0] \\" |
"\tvfrA[15:8] <= vfrB[15:8] \\" |
"\tvfrA[23:16] <= vfrB[23:16] \\" |
"\tvfrA[31:24] <= vfrB[31:24] \\" |
"\tvfrA[39:32] <= vfrB[39:32] \\" |
"\tvfrA[47:40] <= vfrB[47:40] \\" |
"\tvfrA[55:48] <= vfrB[55:48] \\" |
"\tvfrA[63:56] <= vfrB[63:56]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.all_le.h", "Vector Half-Word Elements All Less or Equal Than", |
"All half-word elements of vector/floating-point register vfrA are compared " |
"to half-word elements of vector/floating-point register vfrB. Compare flag is " |
"set if all elements of vfrA are less or equal than elements of vfrB;" |
"otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[15:0] ,= vfrB[15:0] \\" |
"\tvfrA[31:16] <= vfrB[31:16] \\" |
"\tvfrA[47:32] <= vfrB[47:32] \\" |
"\tvfrA[63:48] <= vfrB[63:48]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.all_ne.b", "Vector Byte Elements All Not Equal", |
"All byte elements of vector/floating-point register vfrA are compared " |
"to byte elements of vector/floating-point register vfrB. Compare flag is " |
"set if all corresponding elements are not equal; otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[7:0] != vfrB[7:0] \\" |
"\tvfrA[15:8] != vfrB[15:8] \\" |
"\tvfrA[23:16] != vfrB[23:16] \\" |
"\tvfrA[31:24] != vfrB[31:24] \\" |
"\tvfrA[39:32] != vfrB[39:32] \\" |
"\tvfrA[47:40] != vfrB[47:40] \\" |
"\tvfrA[55:48] != vfrB[55:48] \\" |
"\tvfrA[63:56] != vfrB[63:56]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.all_ne.h", "Vector Half-Word Elements All Not Equal", |
"All half-word elements of vector/floating-point register vfrA are compared " |
"to half-word elements of vector/floating-point register vfrB. Compare flag is " |
"set if all corresponding elements are not equal; otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[15:0] != vfrB[15:0] \\" |
"\tvfrA[31:16] != vfrB[31:16] \\" |
"\tvfrA[47:32] != vfrB[47:32] \\" |
"\tvfrA[63:48] != vfrB[63:48]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.any_eq.b", "Vector Byte Elements Any Equal", |
"All byte elements of vector/floating-point register vfrA are compared " |
"to byte elements of vector/floating-point register vfrB. Compare flag is " |
"set if any two corresponding elements are equal; otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[7:0] == vfrB[7:0] ||\\" |
"\tvfrA[15:8] == vfrB[15:8] ||\\" |
"\tvfrA[23:16] == vfrB[23:16] ||\\" |
"\tvfrA[31:24] == vfrB[31:24] ||\\" |
"\tvfrA[39:32] == vfrB[39:32] ||\\" |
"\tvfrA[47:40] == vfrB[47:40] ||\\" |
"\tvfrA[55:48] == vfrB[55:48] ||\\" |
"\tvfrA[63:56] == vfrB[63:56]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.any_eq.h", "Vector Half-Word Elements Any Equal", |
"All half-word elements of vector/floating-point register vfrA are compared " |
"to half-word elements of vector/floating-point register vfrB. Compare flag is " |
"set if any two corresponding elements are equal; otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[15:0] == vfrB[15:0] ||\\" |
"\tvfrA[31:16] == vfrB[31:16] ||\\" |
"\tvfrA[47:32] == vfrB[47:32] ||\\" |
"\tvfrA[63:48] == vfrB[63:48]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.any_ge.b", "Vector Byte Elements Any Greater or Equal Than", |
"All byte elements of vector/floating-point register vfrA are compared " |
"to byte elements of vector/floating-point register vfrB. Compare flag is " |
"set if any element of vfrA is greater or equal than corresponding element of vfrB;" |
"otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[7:0] >= vfrB[7:0] ||\\" |
"\tvfrA[15:8] >= vfrB[15:8] ||\\" |
"\tvfrA[23:16] >= vfrB[23:16] ||\\" |
"\tvfrA[31:24] >= vfrB[31:24] ||\\" |
"\tvfrA[39:32] >= vfrB[39:32] ||\\" |
"\tvfrA[47:40] >= vfrB[47:40] ||\\" |
"\tvfrA[55:48] >= vfrB[55:48] ||\\" |
"\tvfrA[63:56] >= vfrB[63:56]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.any_ge.h", "Vector Half-Word Elements Any Greater or Equal Than", |
"All half-word elements of vector/floating-point register vfrA are compared " |
"to half-word elements of vector/floating-point register vfrB. Compare flag is " |
"set if any element of vfrA is greater or equal than corresponding element of vfrB;" |
"otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[15:0] >= vfrB[15:0] ||\\" |
"\tvfrA[31:16] >= vfrB[31:16] ||\\" |
"\tvfrA[47:32] >= vfrB[47:32] ||\\" |
"\tvfrA[63:48] >= vfrB[63:48]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.any_gt.b", "Vector Byte Elements Any Greater Than", |
"All byte elements of vector/floating-point register vfrA are compared " |
"to byte elements of vector/floating-point register vfrB. Compare flag is " |
"set if any element of vfrA is greater than corresponding element of vfrB;" |
"otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[7:0] > vfrB[7:0] ||\\" |
"\tvfrA[15:8] > vfrB[15:8] ||\\" |
"\tvfrA[23:16] > vfrB[23:16] ||\\" |
"\tvfrA[31:24] > vfrB[31:24] ||\\" |
"\tvfrA[39:32] > vfrB[39:32] ||\\" |
"\tvfrA[47:40] > vfrB[47:40] ||\\" |
"\tvfrA[55:48] > vfrB[55:48] ||\\" |
"\tvfrA[63:56] > vfrB[63:56]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.any_gt.h", "Vector Half-Word Elements Any Greater Than", |
"All half-word elements of vector/floating-point register vfrA are compared " |
"to half-word elements of vector/floating-point register vfrB. Compare flag is " |
"set if any element of vfrA is greater than corresponding element of vfrB;" |
"otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[15:0] > vfrB[15:0] ||\\" |
"\tvfrA[31:16] > vfrB[31:16] ||\\" |
"\tvfrA[47:32] > vfrB[47:32] ||\\" |
"\tvfrA[63:48] > vfrB[63:48]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.any_lt.b", "Vector Byte Elements Any Less Than", |
"All byte elements of vector/floating-point register vfrA are compared " |
"to byte elements of vector/floating-point register vfrB. Compare flag is " |
"set if any element of vfrA is less than corresponding element of vfrB;" |
"otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[7:0] < vfrB[7:0] ||\\" |
"\tvfrA[15:8] < vfrB[15:8] ||\\" |
"\tvfrA[23:16] < vfrB[23:16] ||\\" |
"\tvfrA[31:24] < vfrB[31:24] ||\\" |
"\tvfrA[39:32] < vfrB[39:32] ||\\" |
"\tvfrA[47:40] < vfrB[47:40] ||\\" |
"\tvfrA[55:48] < vfrB[55:48] ||\\" |
"\tvfrA[63:56] < vfrB[63:56]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.any_lt.h", "Vector Half-Word Elements Any Less Than", |
"All half-word elements of vector/floating-point register vfrA are compared " |
"to half-word elements of vector/floating-point register vfrB. Compare flag is " |
"set if any element of vfrA is less than corresponding element of vfrB;" |
"otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[15:0] < vfrB[15:0] ||\\" |
"\tvfrA[31:16] < vfrB[31:16] ||\\" |
"\tvfrA[47:32] < vfrB[47:32] ||\\" |
"\tvfrA[63:48] < vfrB[63:48]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.any_le.b", "Vector Byte Elements Any Less or Equal Than", |
"All byte elements of vector/floating-point register vfrA are compared " |
"to byte elements of vector/floating-point register vfrB. Compare flag is " |
"set if any element of vfrA is less or equal than corresponding element of vfrB;" |
"otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[7:0] <= vfrB[7:0] ||\\" |
"\tvfrA[15:8] <= vfrB[15:8] ||\\" |
"\tvfrA[23:16] <= vfrB[23:16] ||\\" |
"\tvfrA[31:24] <= vfrB[31:24] ||\\" |
"\tvfrA[39:32] <= vfrB[39:32] ||\\" |
"\tvfrA[47:40] <= vfrB[47:40] ||\\" |
"\tvfrA[55:48] <= vfrB[55:48] ||\\" |
"\tvfrA[63:56] <= vfrB[63:56]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.any_le.h", "Vector Half-Word Elements Any Less or Equal Than", |
"All half-word elements of vector/floating-point register vfrA are compared " |
"to half-word elements of vector/floating-point register vfrB. Compare flag is " |
"set if any element of vfrA is less or equal than corresponding element of vfrB;" |
"otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[15:0] ,= vfrB[15:0] ||\\" |
"\tvfrA[31:16] <= vfrB[31:16] ||\\" |
"\tvfrA[47:32] <= vfrB[47:32] ||\\" |
"\tvfrA[63:48] <= vfrB[63:48]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.any_ne.b", "Vector Byte Elements Any Not Equal", |
"All byte elements of vector/floating-point register vfrA are compared " |
"to byte elements of vector/floating-point register vfrB. Compare flag is " |
"set if any two corresponding elements are not equal; otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[7:0] != vfrB[7:0] ||\\" |
"\tvfrA[15:8] != vfrB[15:8] ||\\" |
"\tvfrA[23:16] != vfrB[23:16] ||\\" |
"\tvfrA[31:24] != vfrB[31:24] ||\\" |
"\tvfrA[39:32] != vfrB[39:32] ||\\" |
"\tvfrA[47:40] != vfrB[47:40] ||\\" |
"\tvfrA[55:48] != vfrB[55:48] ||\\" |
"\tvfrA[63:56] != vfrB[63:56]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.any_ne.h", "Vector Half-Word Elements Any Not Equal", |
"All half-word elements of vector/floating-point register vfrA are compared " |
"to half-word elements of vector/floating-point register vfrB. Compare flag is " |
"set if any two corresponding elements are not equal; otherwise compare flag is cleared. " |
"\\Compare flag is replicated into all bit positions of vector/floating-point " |
"register vfrD.", |
"", |
"flag <- vfrA[15:0] != vfrB[15:0] ||\\" |
"\tvfrA[31:16] != vfrB[31:16] ||\\" |
"\tvfrA[47:32] != vfrB[47:32] ||\\" |
"\tvfrA[63:48] != vfrB[63:48]" |
"vfrD[63:0] <- repl(flag)", |
"None", ORVDX64I,}, |
|
{"lv.cmp_eq.b", "Vector Byte Elements Compare Equal", |
"All byte elements of vector/floating-point register vfrA are compared " |
"to byte elements of vector/floating-point register vfrB. Bits of the element " |
"in vector/floating-point register vfrD are set if two corresponding compared " |
"elements are equal; otherwise element bits are cleared. ", |
"", |
"vfrD[7:0] <- repl(vfrA[7:0] == vfrB[7:0]\\" |
"vfrD[15:8] <- repl(vfrA[15:8] == vfrB[15:8]\\" |
"vfrD[23:16] <- repl(vfrA[23:16] == vfrB[23:16]\\" |
"vfrD[31:24] <- repl(vfrA[31:24] == vfrB[31:24]\\" |
"vfrD[39:32] <- repl(vfrA[39:32] == vfrB[39:32]\\" |
"vfrD[47:40] <- repl(vfrA[47:40] == vfrB[47:40]\\" |
"vfrD[55:48] <- repl(vfrA[55:48] == vfrB[55:48]\\" |
"vfrD[63:56] <- repl(vfrA[63:56] == vfrB[63:56]\\", |
"None", ORVDX64I,}, |
|
{"lv.cmp_eq.h", "Vector Half-Word Elements Compare Equal", |
"All half-word elements of vector/floating-point register vfrA are compared " |
"to half-word elements of vector/floating-point register vfrB. Bits of the element " |
"in vector/floating-point register vfrD are set if two corresponding compared " |
"elements are equal; otherwise element bits are cleared. ", |
"", |
"vfrD[15:0] <- repl(vfrA[7:0] == vfrB[7:0]\\" |
"vfrD[31:16] <- repl(vfrA[23:16] == vfrB[23:16]\\" |
"vfrD[47:32] <- repl(vfrA[39:32] == vfrB[39:32]\\" |
"vfrD[63:48] <- repl(vfrA[55:48] == vfrB[55:48]\\", |
"None", ORVDX64I,}, |
|
{"lv.cmp_ge.b", "Vector Byte Elements Compare Greater Than or Equal", |
"All byte elements of vector/floating-point register vfrA are compared " |
"to byte elements of vector/floating-point register vfrB. Bits of the element " |
"in vector/floating-point register vfrD are set if element in vfrA is " |
"greater than or equal to element in vfrB; otherwise element bits are cleared. ", |
"", |
"vfrD[7:0] <- repl(vfrA[7:0] >= vfrB[7:0]\\" |
"vfrD[15:8] <- repl(vfrA[15:8] >= vfrB[15:8]\\" |
"vfrD[23:16] <- repl(vfrA[23:16] >= vfrB[23:16]\\" |
"vfrD[31:24] <- repl(vfrA[31:24] >= vfrB[31:24]\\" |
"vfrD[39:32] <- repl(vfrA[39:32] >= vfrB[39:32]\\" |
"vfrD[47:40] <- repl(vfrA[47:40] >= vfrB[47:40]\\" |
"vfrD[55:48] <- repl(vfrA[55:48] >= vfrB[55:48]\\" |
"vfrD[63:56] <- repl(vfrA[63:56] >= vfrB[63:56]\\", |
"None", ORVDX64I,}, |
|
{"lv.cmp_ge.h", "Vector Half-Word Elements Compare Greater Than or Equal", |
"All half-word elements of vector/floating-point register vfrA are compared " |
"to half-word elements of vector/floating-point register vfrB. Bits of the element " |
"in vector/floating-point register vfrD are set if element in vfrA is " |
"greater than or equal to element in vfrB; otherwise element bits are cleared. ", |
"", |
"vfrD[15:0] <- repl(vfrA[7:0] >= vfrB[7:0]\\" |
"vfrD[31:16] <- repl(vfrA[23:16] >= vfrB[23:16]\\" |
"vfrD[47:32] <- repl(vfrA[39:32] >= vfrB[39:32]\\" |
"vfrD[63:48] <- repl(vfrA[55:48] >= vfrB[55:48]\\", |
"None", ORVDX64I,}, |
|
{"lv.cmp_gt.b", "Vector Byte Elements Compare Greater Than", |
"All byte elements of vector/floating-point register vfrA are compared " |
"to byte elements of vector/floating-point register vfrB. Bits of the element " |
"in vector/floating-point register vfrD are set if element in vfrA is " |
"greater than element in vfrB; otherwise element bits are cleared. ", |
"", |
"vfrD[7:0] <- repl(vfrA[7:0] > vfrB[7:0]\\" |
"vfrD[15:8] <- repl(vfrA[15:8] > vfrB[15:8]\\" |
"vfrD[23:16] <- repl(vfrA[23:16] > vfrB[23:16]\\" |
"vfrD[31:24] <- repl(vfrA[31:24] > vfrB[31:24]\\" |
"vfrD[39:32] <- repl(vfrA[39:32] > vfrB[39:32]\\" |
"vfrD[47:40] <- repl(vfrA[47:40] > vfrB[47:40]\\" |
"vfrD[55:48] <- repl(vfrA[55:48] > vfrB[55:48]\\" |
"vfrD[63:56] <- repl(vfrA[63:56] > vfrB[63:56]\\", |
"None", ORVDX64I,}, |
|
{"lv.cmp_gt.h", "Vector Half-Word Elements Compare Greater Than", |
"All half-word elements of vector/floating-point register vfrA are compared " |
"to half-word elements of vector/floating-point register vfrB. Bits of the element " |
"in vector/floating-point register vfrD are set if element in vfrA is " |
"greater than element in vfrB; otherwise element bits are cleared. ", |
"", |
"vfrD[15:0] <- repl(vfrA[7:0] > vfrB[7:0]\\" |
"vfrD[31:16] <- repl(vfrA[23:16] > vfrB[23:16]\\" |
"vfrD[47:32] <- repl(vfrA[39:32] > vfrB[39:32]\\" |
"vfrD[63:48] <- repl(vfrA[55:48] > vfrB[55:48]\\", |
"None", ORVDX64I,}, |
|
{"lv.cmp_le.b", "Vector Byte Elements Compare Less Than or Equal", |
"All byte elements of vector/floating-point register vfrA are compared " |
"to byte elements of vector/floating-point register vfrB. Bits of the element " |
"in vector/floating-point register vfrD are set if element in vfrA is " |
"less than or equal to element in vfrB; otherwise element bits are cleared. ", |
"", |
"vfrD[7:0] <- repl(vfrA[7:0] <= vfrB[7:0]\\" |
"vfrD[15:8] <- repl(vfrA[15:8] <= vfrB[15:8]\\" |
"vfrD[23:16] <- repl(vfrA[23:16] <= vfrB[23:16]\\" |
"vfrD[31:24] <- repl(vfrA[31:24] <= vfrB[31:24]\\" |
"vfrD[39:32] <- repl(vfrA[39:32] <= vfrB[39:32]\\" |
"vfrD[47:40] <- repl(vfrA[47:40] <= vfrB[47:40]\\" |
"vfrD[55:48] <- repl(vfrA[55:48] <= vfrB[55:48]\\" |
"vfrD[63:56] <- repl(vfrA[63:56] <= vfrB[63:56]\\", |
"None", ORVDX64I,}, |
|
{"lv.cmp_le.h", "Vector Half-Word Elements Compare Less Than or Equal", |
"All half-word elements of vector/floating-point register vfrA are compared " |
"to half-word elements of vector/floating-point register vfrB. Bits of the element " |
"in vector/floating-point register vfrD are set if element in vfrA is " |
"less than or equal to element in vfrB; otherwise element bits are cleared. ", |
"", |
"vfrD[15:0] <- repl(vfrA[7:0] <= vfrB[7:0]\\" |
"vfrD[31:16] <- repl(vfrA[23:16] <= vfrB[23:16]\\" |
"vfrD[47:32] <- repl(vfrA[39:32] <= vfrB[39:32]\\" |
"vfrD[63:48] <- repl(vfrA[55:48] <= vfrB[55:48]\\", |
"None", ORVDX64I,}, |
|
{"lv.cmp_lt.b", "Vector Byte Elements Compare Less Than", |
"All byte elements of vector/floating-point register vfrA are compared " |
"to byte elements of vector/floating-point register vfrB. Bits of the element " |
"in vector/floating-point register vfrD are set if element in vfrA is " |
"less than element in vfrB; otherwise element bits are cleared. ", |
"", |
"vfrD[7:0] <- repl(vfrA[7:0] <= vfrB[7:0]\\" |
"vfrD[15:8] <- repl(vfrA[15:8] <= vfrB[15:8]\\" |
"vfrD[23:16] <- repl(vfrA[23:16] <= vfrB[23:16]\\" |
"vfrD[31:24] <- repl(vfrA[31:24] <= vfrB[31:24]\\" |
"vfrD[39:32] <- repl(vfrA[39:32] <= vfrB[39:32]\\" |
"vfrD[47:40] <- repl(vfrA[47:40] <= vfrB[47:40]\\" |
"vfrD[55:48] <- repl(vfrA[55:48] <= vfrB[55:48]\\" |
"vfrD[63:56] <- repl(vfrA[63:56] <= vfrB[63:56]\\", |
"None", ORVDX64I,}, |
|
{"lv.cmp_lt.h", "Vector Half-Word Elements Compare Less Than", |
"All half-word elements of vector/floating-point register vfrA are compared " |
"to half-word elements of vector/floating-point register vfrB. Bits of the element " |
"in vector/floating-point register vfrD are set if element in vfrA is " |
"less than element in vfrB; otherwise element bits are cleared. ", |
"", |
"vfrD[15:0] <- repl(vfrA[7:0] <= vfrB[7:0]\\" |
"vfrD[31:16] <- repl(vfrA[23:16] <= vfrB[23:16]\\" |
"vfrD[47:32] <- repl(vfrA[39:32] <= vfrB[39:32]\\" |
"vfrD[63:48] <- repl(vfrA[55:48] <= vfrB[55:48]\\", |
"None", ORVDX64I,}, |
|
{"lv.cmp_ne.b", "Vector Byte Elements Compare Not Equal", |
"All byte elements of vector/floating-point register vfrA are compared " |
"to byte elements of vector/floating-point register vfrB. Bits of the element " |
"in vector/floating-point register vfrD are set if two corresponding compared " |
"elements are not equal; otherwise element bits are cleared. ", |
"", |
"vfrD[7:0] <- repl(vfrA[7:0] != vfrB[7:0])\\" |
"vfrD[15:8] <- repl(vfrA[15:8] != vfrB[15:8])\\" |
"vfrD[23:16] <- repl(vfrA[23:16] != vfrB[23:16])\\" |
"vfrD[31:24] <- repl(vfrA[31:24] != vfrB[31:24])\\" |
"vfrD[39:32] <- repl(vfrA[39:32] != vfrB[39:32])\\" |
"vfrD[47:40] <- repl(vfrA[47:40] != vfrB[47:40])\\" |
"vfrD[55:48] <- repl(vfrA[55:48] != vfrB[55:48])\\" |
"vfrD[63:56] <- repl(vfrA[63:56] != vfrB[63:56])\\", |
"None", ORVDX64I,}, |
|
{"lv.cmp_ne.h", "Vector Half-Word Elements Compare Not Equal", |
"All half-word elements of vector/floating-point register vfrA are compared " |
"to half-word elements of vector/floating-point register vfrB. Bits of the element " |
"in vector/floating-point register vfrD are set if two corresponding compared " |
"elements are not equal; otherwise element bits are cleared. ", |
"", |
"vfrD[15:0] <- repl(vfrA[7:0] != vfrB[7:0])\\" |
"vfrD[31:16] <- repl(vfrA[23:16] != vfrB[23:16])\\" |
"vfrD[47:32] <- repl(vfrA[39:32] != vfrB[39:32])\\" |
"vfrD[63:48] <- repl(vfrA[55:48] != vfrB[55:48])\\", |
"None", ORVDX64I,}, |
|
{"lv.and", "Vector And", |
"The contents of vector/floating-point register vfrA are combined with the contents " |
"of vector/floating-point register vfrB in a bit-wise logical AND operation. The " |
"result is placed into vector/floating-point register vfrD.", |
"", |
"vfrD[63:0] <- vfrA[63:0] AND vfrB[63:0]", |
"None", ORVDX64I,}, |
|
{"lv.nand", "Vector Not And", |
"The contents of vector/floating-point register vfrA are combined with the contents " |
"of vector/floating-point register vfrB in a bit-wise logical NAND operation. The " |
"result is placed into vector/floating-point register vfrD.", |
"", |
"vfrD[63:0] <- vfrA[63:0] NAND vfrB[63:0]", |
"None", ORVDX64I,}, |
|
{"lv.nor", "Vector Not Or", |
"The contents of vector/floating-point register vfrA are combined with the contents " |
"of vector/floating-point register vfrB in a bit-wise logical NOR operation. The " |
"result is placed into vector/floating-point register vfrD.", |
"", |
"vfrD[63:0] <- vfrA[63:0] NOR vfrB[63:0]", |
"None", ORVDX64I,}, |
|
{"lv.or", "Vector Or", |
"The contents of vector/floating-point register vfrA are combined with the contents " |
"of vector/floating-point register vfrB in a bit-wise logical OR operation. The " |
"result is placed into vector/floating-point register vfrD.", |
"", |
"vfrD[63:0] <- vfrA[63:0] OR vfrB[63:0]", |
"None", ORVDX64I,}, |
|
{"lv.xor", "Vector Exclusive Or", |
"The contents of vector/floating-point register vfrA are combined with the contents " |
"of vector/floating-point register vfrB in a bit-wise logical XOR operation. The " |
"result is placed into vector/floating-point register vfrD.", |
"", |
"vfrD[63:0] <- vfrA[63:0] XOR vfrB[63:0]", |
"None", ORVDX64I,}, |
|
{"lv.add.b", "Vector Byte Elements Add Signed", |
"The byte elements of vector/floating-point register vfrA are added to the byte elements " |
"of vector/floating-point register vfrB to form the result elements. Result " |
"elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[7:0] <- vfrA[7:0] + vfrB[7:0]\\" |
"vfrD[15:8] <- vfrA[15:8] + vfrB[15:8]\\" |
"vfrD[23:16] <- vfrA[23:16] + vfrB[23:16]\\" |
"vfrD[31:24] <- vfrA[31:24] + vfrB[31:24]\\" |
"vfrD[39:32] <- vfrA[39:32] + vfrB[39:32]\\" |
"vfrD[47:40] <- vfrA[47:40] + vfrB[47:40]\\" |
"vfrD[55:48] <- vfrA[55:48] + vfrB[55:48]\\" |
"vfrD[63:56] <- vfrA[63:56] + vfrB[63:56]", |
"None", ORVDX64I,}, |
|
{"lv.add.h", "Vector Half-Word Elements Add Signed", |
"The half-word elements of vector/floating-point register vfrA are added to the " |
"half-word elements of vector/floating-point register vfrB to form the result " |
"elements. Result elements are placed into vector/floating-point " |
"register vfrD.", |
"", |
"vfrD[15:0] <- vfrA[15:0] + vfrB[15:0]\\" |
"vfrD[31:16] <- vfrA[31:16] + vfrB[31:16]\\" |
"vfrD[47:32] <- vfrA[47:32] + vfrB[47:32]\\" |
"vfrD[63:48] <- vfrA[63:48] + vfrB[63:48]\\", |
"None", ORVDX64I,}, |
|
{"lv.sub.b", "Vector Byte Elements Subtract Signed", |
"The byte elements of vector/floating-point register vfrB are subtracted from the " |
"byte elements of vector/floating-point register vfrA to form the result elements. " |
"Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[7:0] <- vfrA[7:0] - vfrB[7:0]\\" |
"vfrD[15:8] <- vfrA[15:8] - vfrB[15:8]\\" |
"vfrD[23:16] <- vfrA[23:16] - vfrB[23:16]\\" |
"vfrD[31:24] <- vfrA[31:24] - vfrB[31:24]\\" |
"vfrD[39:32] <- vfrA[39:32] - vfrB[39:32]\\" |
"vfrD[47:40] <- vfrA[47:40] - vfrB[47:40]\\" |
"vfrD[55:48] <- vfrA[55:48] - vfrB[55:48]\\" |
"vfrD[63:56] <- vfrA[63:56] - vfrB[63:56]", |
"None", ORVDX64I,}, |
|
{"lv.sub.h", "Vector Half-Word Elements Subtract Signed", |
"The half-word elements of vector/floating-point register vfrB are subtracted from the " |
"half-word elements of vector/floating-point register vfrA to form the result " |
"elements. Result elements are placed into vector/floating-point " |
"register vfrD.", |
"", |
"vfrD[15:0] <- vfrA[15:0] - vfrB[15:0]\\" |
"vfrD[31:16] <- vfrA[31:16] - vfrB[31:16]\\" |
"vfrD[47:32] <- vfrA[47:32] - vfrB[47:32]\\" |
"vfrD[63:48] <- vfrA[63:48] - vfrB[63:48]\\", |
"None", ORVDX64I,}, |
|
{"lv.adds.b", "Vector Byte Elements Add Signed Saturated", |
"The byte elements of vector/floating-point register vfrA are added to the byte elements " |
"of vector/floating-point register vfrB to form the result elements. If the result " |
" exceeds min/max value for the destination data type, it is saturated to min/max value " |
" and placed into vector/floating-point register vfrD.", |
"", |
"vfrD[7:0] <- sat8s(vfrA[7:0] + vfrB[7:0])\\" |
"vfrD[15:8] <- sat8s(vfrA[15:8] + vfrB[15:8])\\" |
"vfrD[23:16] <- sat8s(vfrA[23:16] + vfrB[23:16])\\" |
"vfrD[31:24] <- sat8s(vfrA[31:24] + vfrB[31:24])\\" |
"vfrD[39:32] <- sat8s(vfrA[39:32] + vfrB[39:32])\\" |
"vfrD[47:40] <- sat8s(vfrA[47:40] + vfrB[47:40])\\" |
"vfrD[55:48] <- sat8s(vfrA[55:48] + vfrB[55:48])\\" |
"vfrD[63:56] <- sat8s(vfrA[63:56] + vfrB[63:56])", |
"None", ORVDX64I,}, |
|
{"lv.adds.h", "Vector Half-Word Elements Add Signed Saturated", |
"The half-word elements of vector/floating-point register vfrA are added to the " |
"half-word elements of vector/floating-point register vfrB to form the result " |
"elements. If the result exceeds min/max value for the destination data type, " |
"it is saturated to min/max value and placed into vector/floating-point register vfrD.", |
"", |
"vfrD[15:0] <- sat16s(vfrA[15:0] + vfrB[15:0])\\" |
"vfrD[31:16] <- sat16s(vfrA[31:16] + vfrB[31:16])\\" |
"vfrD[47:32] <- sat16s(vfrA[47:32] + vfrB[47:32])\\" |
"vfrD[63:48] <- sat16s(vfrA[63:48] + vfrB[63:48])", |
"None", ORVDX64I,}, |
|
{"lv.subs.b", "Vector Byte Elements Subtract Signed Saturated", |
"The byte elements of vector/floating-point register vfrB are subtracted from the byte elements " |
"of vector/floating-point register vfrA to form the result elements. If the result " |
"exceeds min/max value for the destination data type, it is saturated to min/max value " |
"and placed into vector/floating-point register vfrD.", |
"", |
"vfrD[7:0] <- sat8s(vfrA[7:0] + vfrB[7:0])\\" |
"vfrD[15:8] <- sat8s(vfrA[15:8] + vfrB[15:8])\\" |
"vfrD[23:16] <- sat8s(vfrA[23:16] + vfrB[23:16])\\" |
"vfrD[31:24] <- sat8s(vfrA[31:24] + vfrB[31:24])\\" |
"vfrD[39:32] <- sat8s(vfrA[39:32] + vfrB[39:32])\\" |
"vfrD[47:40] <- sat8s(vfrA[47:40] + vfrB[47:40])\\" |
"vfrD[55:48] <- sat8s(vfrA[55:48] + vfrB[55:48])\\" |
"vfrD[63:56] <- sat8s(vfrA[63:56] + vfrB[63:56])", |
"None", ORVDX64I,}, |
|
{"lv.subs.h", "Vector Half-Word Elements Subtract Signed Saturated", |
"The half-word elements of vector/floating-point register vfrB are subtracted from the " |
"half-word elements of vector/floating-point register vfrA to form the result " |
"elements. If the result exceeds min/max value for the destination data type, " |
"it is saturated to min/max value and placed into vector/floating-point register vfrD.", |
"", |
"vfrD[15:0] <- sat16s(vfrA[15:0] - vfrB[15:0])\\" |
"vfrD[31:16] <- sat16s(vfrA[31:16] - vfrB[31:16])\\" |
"vfrD[47:32] <- sat16s(vfrA[47:32] - vfrB[47:32])\\" |
"vfrD[63:48] <- sat16s(vfrA[63:48] - vfrB[63:48])", |
"None", ORVDX64I,}, |
|
{"lv.addu.b", "Vector Byte Elements Add Unsigned", |
"The unsigned byte elements of vector/floating-point register vfrA are added to " |
"the unsigned byte elements of vector/floating-point register vfrB to form the " |
"result elements. Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[7:0] <- vfrA[7:0] + vfrB[7:0]\\" |
"vfrD[15:8] <- vfrA[15:8] + vfrB[15:8]\\" |
"vfrD[23:16] <- vfrA[23:16] + vfrB[23:16]\\" |
"vfrD[31:24] <- vfrA[31:24] + vfrB[31:24]\\" |
"vfrD[39:32] <- vfrA[39:32] + vfrB[39:32]\\" |
"vfrD[47:40] <- vfrA[47:40] + vfrB[47:40]\\" |
"vfrD[55:48] <- vfrA[55:48] + vfrB[55:48]\\" |
"vfrD[63:56] <- vfrA[63:56] + vfrB[63:56]", |
"None", ORVDX64I,}, |
|
{"lv.addu.h", "Vector Half-Word Elements Add Unsigned", |
"The unsigned half-word elements of vector/floating-point register vfrA are added to the " |
"unsigned half-word elements of vector/floating-point register vfrB to form the result " |
"elements. Result elements are placed into vector/floating-point " |
"register vfrD.", |
"", |
"vfrD[15:0] <- vfrA[15:0] + vfrB[15:0]\\" |
"vfrD[31:16] <- vfrA[31:16] + vfrB[31:16]\\" |
"vfrD[47:32] <- vfrA[47:32] + vfrB[47:32]\\" |
"vfrD[63:48] <- vfrA[63:48] + vfrB[63:48]\\", |
"None", ORVDX64I,}, |
|
{"lv.subu.b", "Vector Byte Elements Subtract Unsigned", |
"The unsigned byte elements of vector/floating-point register vfrB are subtracted from the " |
"unsigned byte elements of vector/floating-point register vfrA to form the result elements. " |
"Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[7:0] <- vfrA[7:0] - vfrB[7:0]\\" |
"vfrD[15:8] <- vfrA[15:8] - vfrB[15:8]\\" |
"vfrD[23:16] <- vfrA[23:16] - vfrB[23:16]\\" |
"vfrD[31:24] <- vfrA[31:24] - vfrB[31:24]\\" |
"vfrD[39:32] <- vfrA[39:32] - vfrB[39:32]\\" |
"vfrD[47:40] <- vfrA[47:40] - vfrB[47:40]\\" |
"vfrD[55:48] <- vfrA[55:48] - vfrB[55:48]\\" |
"vfrD[63:56] <- vfrA[63:56] - vfrB[63:56]", |
"None", ORVDX64I,}, |
|
{"lv.subu.h", "Vector Half-Word Elements Subtract Unsigned", |
"The unsigned half-word elements of vector/floating-point register vfrB are subtracted from the " |
"unsigned half-word elements of vector/floating-point register vfrA to form the result " |
"elements. Result elements are placed into vector/floating-point " |
"register vfrD.", |
"", |
"vfrD[15:0] <- vfrA[15:0] - vfrB[15:0]\\" |
"vfrD[31:16] <- vfrA[31:16] - vfrB[31:16]\\" |
"vfrD[47:32] <- vfrA[47:32] - vfrB[47:32]\\" |
"vfrD[63:48] <- vfrA[63:48] - vfrB[63:48]\\", |
"None", ORVDX64I,}, |
|
{"lv.addus.b", "Vector Byte Elements Add Unsigned Saturated", |
"The unsigned byte elements of vector/floating-point register vfrA are added to the " |
"unsigned byte elements of vector/floating-point register vfrB to form the result " |
"elements. If the result exceeds min/max value for the destination data type, " |
"it is saturated to min/max value and placed into vector/floating-point register vfrD.", |
"", |
"vfrD[7:0] <- sat8u(vfrA[7:0] + vfrB[7:0])\\" |
"vfrD[15:8] <- sat8u(vfrA[15:8] + vfrB[15:8])\\" |
"vfrD[23:16] <- sat8u(vfrA[23:16] + vfrB[23:16])\\" |
"vfrD[31:24] <- sat8u(vfrA[31:24] + vfrB[31:24])\\" |
"vfrD[39:32] <- sat8u(vfrA[39:32] + vfrB[39:32])\\" |
"vfrD[47:40] <- sat8u(vfrA[47:40] + vfrB[47:40])\\" |
"vfrD[55:48] <- sat8u(vfrA[55:48] + vfrB[55:48])\\" |
"vfrD[63:56] <- sat8u(vfrA[63:56] + vfrB[63:56])", |
"None", ORVDX64I,}, |
|
{"lv.addus.h", "Vector Half-Word Elements Add Unsigned Saturated", |
"The unsigned half-word elements of vector/floating-point register vfrA are added to the " |
"unsigned half-word elements of vector/floating-point register vfrB to form the result " |
"elements. If the result exceeds min/max value for the destination data type, " |
"it is saturated to min/max value and placed into vector/floating-point register vfrD.", |
"", |
"vfrD[15:0] <- sat16s(vfrA[15:0] + vfrB[15:0])\\" |
"vfrD[31:16] <- sat16s(vfrA[31:16] + vfrB[31:16])\\" |
"vfrD[47:32] <- sat16s(vfrA[47:32] + vfrB[47:32])\\" |
"vfrD[63:48] <- sat16s(vfrA[63:48] + vfrB[63:48])", |
"None", ORVDX64I,}, |
|
{"lv.subus.b", "Vector Byte Elements Subtract Unsigned Saturated", |
"The unsigned byte elements of vector/floating-point register vfrB are subtracted from " |
"the unsigned byte elements of vector/floating-point register vfrA to form the result " |
"elements. If the result exceeds min/max value for the destination data type, it is " |
"saturated to min/max value and placed into vector/floating-point register vfrD.", |
"", |
"vfrD[7:0] <- sat8u(vfrA[7:0] + vfrB[7:0])\\" |
"vfrD[15:8] <- sat8u(vfrA[15:8] + vfrB[15:8])\\" |
"vfrD[23:16] <- sat8u(vfrA[23:16] + vfrB[23:16])\\" |
"vfrD[31:24] <- sat8u(vfrA[31:24] + vfrB[31:24])\\" |
"vfrD[39:32] <- sat8u(vfrA[39:32] + vfrB[39:32])\\" |
"vfrD[47:40] <- sat8u(vfrA[47:40] + vfrB[47:40])\\" |
"vfrD[55:48] <- sat8u(vfrA[55:48] + vfrB[55:48])\\" |
"vfrD[63:56] <- sat8u(vfrA[63:56] + vfrB[63:56])", |
"None", ORVDX64I,}, |
|
{"lv.subus.h", "Vector Half-Word Elements Subtract Unsigned Saturated", |
"The unsigned half-word elements of vector/floating-point register vfrB are subtracted " |
"from the unsigned half-word elements of vector/floating-point register vfrA to form " |
"the result elements. If the result exceeds min/max value for the destination data type, " |
"it is saturated to min/max value and placed into vector/floating-point register vfrD.", |
"", |
"vfrD[15:0] <- sat16u(vfrA[15:0] - vfrB[15:0])\\" |
"vfrD[31:16] <- sat16u(vfrA[31:16] - vfrB[31:16])\\" |
"vfrD[47:32] <- sat16u(vfrA[47:32] - vfrB[47:32])\\" |
"vfrD[63:48] <- sat16u(vfrA[63:48] - vfrB[63:48])", |
"None", ORVDX64I,}, |
|
{"lv.avg.b", "Vector Byte Elements Average", |
"The byte elements of vector/floating-point register vfrA are added to the byte elements " |
"of vector/floating-point register vfrB and the sum is shifted right by one to form the " |
"result elements. Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[7:0] <- (vfrA[7:0] + vfrB[7:0]) >> 1\\" |
"vfrD[15:8] <- (vfrA[15:8] + vfrB[15:8]) >> 1\\" |
"vfrD[23:16] <- (vfrA[23:16] + vfrB[23:16]) >> 1\\" |
"vfrD[31:24] <- (vfrA[31:24] + vfrB[31:24]) >> 1\\" |
"vfrD[39:32] <- (vfrA[39:32] + vfrB[39:32]) >> 1\\" |
"vfrD[47:40] <- (vfrA[47:40] + vfrB[47:40]) >> 1\\" |
"vfrD[55:48] <- (vfrA[55:48] + vfrB[55:48]) >> 1\\" |
"vfrD[63:56] <- (vfrA[63:56] + vfrB[63:56]) >> 1", |
"None", ORVDX64I,}, |
|
{"lv.avg.h", "Vector Half-Word Elements Average", |
"The half-word elements of vector/floating-point register vfrA are added to the " |
"half-word elements of vector/floating-point register vfrB and the sum is shifted " |
"right by one to form the result elements. Result elements are placed into " |
"vector/floating-point register vfrD.", |
"", |
"vfrD[15:0] <- (vfrA[15:0] + vfrB[15:0]) >> 1\\" |
"vfrD[31:16] <- (vfrA[31:16] + vfrB[31:16]) >> 1\\" |
"vfrD[47:32] <- (vfrA[47:32] + vfrB[47:32]) >> 1\\" |
"vfrD[63:48] <- (vfrA[63:48] + vfrB[63:48]) >> 1\\", |
"None", ORVDX64I,}, |
|
{"lv.max.b", "Vector Byte Elements Maximum", |
"The byte elements of vector/floating-point register vfrA are compared to the byte elements " |
"of vector/floating-point register vfrB and larger elements are selected to form the " |
"result elements. Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[7:0] <- vfrA[7:0] > vfrB[7:0] ? vfrA[7:0] : vrfB[7:0]\\" |
"vfrD[15:8] <- vfrA[15:8] > vfrB[15:8] ? vfrA[15:8] : vrfB[15:8]\\" |
"vfrD[23:16] <- vfrA[23:16] > vfrB[23:16] ? vfrA[23:16] : vrfB[23:16]\\" |
"vfrD[31:24] <- vfrA[31:24] > vfrB[31:24] ? vfrA[31:24] : vrfB[31:24]\\" |
"vfrD[39:32] <- vfrA[39:32] > vfrB[39:32] ? vfrA[39:32] : vrfB[39:32]\\" |
"vfrD[47:40] <- vfrA[47:40] > vfrB[47:40] ? vfrA[47:40] : vrfB[47:40]\\" |
"vfrD[55:48] <- vfrA[55:48] > vfrB[55:48] ? vfrA[55:48] : vrfB[55:48]\\" |
"vfrD[63:56] <- vfrA[63:56] > vfrB[63:56] ? vfrA[63:56] : vrfB[63:56]", |
"None", ORVDX64I,}, |
|
{"lv.max.h", "Vector Half-Word Elements Maximum", |
"The half-word elements of vector/floating-point register vfrA are compared to the " |
"half-word elements of vector/floating-point register vfrB and larger elements " |
"are selected to form the result elements. Result elements are placed into " |
"vector/floating-point register vfrD.", |
"", |
"vfrD[15:0] <- vfrA[15:0] > vfrB[15:0] ? vfrA[15:0] : vrfB[15:0]\\" |
"vfrD[31:16] <- vfrA[31:16] > vfrB[31:16] ? vfrA[31:16] : vrfB[31:16]\\" |
"vfrD[47:32] <- vfrA[47:32] > vfrB[47:32] ? vfrA[47:32] : vrfB[47:32]\\" |
"vfrD[63:48] <- vfrA[63:48] > vfrB[63:48] ? vfrA[63:48] : vrfB[63:48]\\", |
"None", ORVDX64I,}, |
|
{"lv.min.b", "Vector Byte Elements Minimum", |
"The byte elements of vector/floating-point register vfrA are compared to the byte elements " |
"of vector/floating-point register vfrB and smaller elements are selected to form the " |
"result elements. Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[7:0] <- vfrA[7:0] < vfrB[7:0] ? vfrA[7:0] : vrfB[7:0]\\" |
"vfrD[15:8] <- vfrA[15:8] < vfrB[15:8] ? vfrA[15:8] : vrfB[15:8]\\" |
"vfrD[23:16] <- vfrA[23:16] < vfrB[23:16] ? vfrA[23:16] : vrfB[23:16]\\" |
"vfrD[31:24] <- vfrA[31:24] < vfrB[31:24] ? vfrA[31:24] : vrfB[31:24]\\" |
"vfrD[39:32] <- vfrA[39:32] < vfrB[39:32] ? vfrA[39:32] : vrfB[39:32]\\" |
"vfrD[47:40] <- vfrA[47:40] < vfrB[47:40] ? vfrA[47:40] : vrfB[47:40]\\" |
"vfrD[55:48] <- vfrA[55:48] < vfrB[55:48] ? vfrA[55:48] : vrfB[55:48]\\" |
"vfrD[63:56] <- vfrA[63:56] < vfrB[63:56] ? vfrA[63:56] : vrfB[63:56]", |
"None", ORVDX64I,}, |
|
{"lv.min.h", "Vector Half-Word Elements Minimum", |
"The half-word elements of vector/floating-point register vfrA are compared to the " |
"half-word elements of vector/floating-point register vfrB and smaller elements " |
"are selected to form the result elements. Result elements are placed into " |
"vector/floating-point register vfrD.", |
"", |
"vfrD[15:0] <- vfrA[15:0] < vfrB[15:0] ? vfrA[15:0] : vrfB[15:0]\\" |
"vfrD[31:16] <- vfrA[31:16] < vfrB[31:16] ? vfrA[31:16] : vrfB[31:16]\\" |
"vfrD[47:32] <- vfrA[47:32] < vfrB[47:32] ? vfrA[47:32] : vrfB[47:32]\\" |
"vfrD[63:48] <- vfrA[63:48] < vfrB[63:48] ? vfrA[63:48] : vrfB[63:48]\\", |
"None", ORVDX64I,}, |
|
{"lv.sll.b", "Vector Byte Elements Shift Left Logical", |
"The contents of byte elements of vector/floating-point register vfrA are " |
"shifted left by the number of bits specified in lower 3 bits in each byte element " |
"of vector/floating-point register vfrB, inserting zeros into the low-order bits " |
"elements. Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[7:0] <- vfrA[7:0] << vfrB[2:0]\\" |
"vfrD[15:8] <- vfrA[15:8] << vfrB[10:8]\\" |
"vfrD[23:16] <- vfrA[23:16] << vfrB[18:16]\\" |
"vfrD[31:24] <- vfrA[31:24] << vfrB[26:24]\\" |
"vfrD[39:32] <- vfrA[39:32] << vfrB[34:32]\\" |
"vfrD[47:40] <- vfrA[47:40] << vfrB[42:40]\\" |
"vfrD[55:48] <- vfrA[55:48] << vfrB[50:48]\\" |
"vfrD[63:56] <- vfrA[63:56] << vfrB[58:56]", |
"None", ORVDX64I,}, |
|
{"lv.sll.h", "Vector Half-Word Elements Shift Left Logical", |
"The contents of half-word elements of vector/floating-point register vfrA are " |
"shifted left by the number of bits specified in lower 4 bits in each half-word element " |
"of vector/floating-point register vfrB, inserting zeros into the low-order bits " |
"elements. Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[15:0] <- vfrA[15:0] << vfrB[3:0]\\" |
"vfrD[31:16] <- vfrA[31:16] << vfrB[19:16]\\" |
"vfrD[47:32] <- vfrA[47:32] << vfrB[35:32]\\" |
"vfrD[63:48] <- vfrA[63:48] << vfrB[51:48]\\", |
"None", ORVDX64I,}, |
|
{"lv.srl.b", "Vector Byte Elements Shift Right Logical", |
"The contents of byte elements of vector/floating-point register vfrA are " |
"shifted right by the number of bits specified in lower 3 bits in each byte element " |
"of vector/floating-point register vfrB, inserting zeros into the high-order bits " |
"elements. Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[7:0] <- vfrA[7:0] >> vfrB[2:0]\\" |
"vfrD[15:8] <- vfrA[15:8] >> vfrB[10:8]\\" |
"vfrD[23:16] <- vfrA[23:16] >> vfrB[18:16]\\" |
"vfrD[31:24] <- vfrA[31:24] >> vfrB[26:24]\\" |
"vfrD[39:32] <- vfrA[39:32] >> vfrB[34:32]\\" |
"vfrD[47:40] <- vfrA[47:40] >> vfrB[42:40]\\" |
"vfrD[55:48] <- vfrA[55:48] >> vfrB[50:48]\\" |
"vfrD[63:56] <- vfrA[63:56] >> vfrB[58:56]", |
"None", ORVDX64I,}, |
|
{"lv.srl.h", "Vector Half-Word Elements Shift Right Logical", |
"The contents of half-word elements of vector/floating-point register vfrA are " |
"shifted right by the number of bits specified in lower 4 bits in each half-word element " |
"of vector/floating-point register vfrB, inserting zeros into the low-order bits of " |
"elements. Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[15:0] <- vfrA[15:0] >> vfrB[3:0]\\" |
"vfrD[31:16] <- vfrA[31:16] >> vfrB[19:16]\\" |
"vfrD[47:32] <- vfrA[47:32] >> vfrB[35:32]\\" |
"vfrD[63:48] <- vfrA[63:48] >> vfrB[51:48]\\", |
"None", ORVDX64I,}, |
|
{"lv.sra.b", "Vector Byte Elements Shift Right Arithmetic", |
"The contents of byte elements of vector/floating-point register vfrA are " |
"shifted right by the number of bits specified in lower 3 bits in each byte element " |
"of vector/floating-point register vfrB, inserting most significat bit of each " |
"element into the high-order bits. " |
"Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[7:0] <- vfrA[7:0] sra vfrB[2:0]\\" |
"vfrD[15:8] <- vfrA[15:8] sra vfrB[10:8]\\" |
"vfrD[23:16] <- vfrA[23:16] sra vfrB[18:16]\\" |
"vfrD[31:24] <- vfrA[31:24] sra vfrB[26:24]\\" |
"vfrD[39:32] <- vfrA[39:32] sra vfrB[34:32]\\" |
"vfrD[47:40] <- vfrA[47:40] sra vfrB[42:40]\\" |
"vfrD[55:48] <- vfrA[55:48] sra vfrB[50:48]\\" |
"vfrD[63:56] <- vfrA[63:56] sra vfrB[58:56]", |
"None", ORVDX64I,}, |
|
{"lv.sra.h", "Vector Half-Word Elements Shift Right Arithmetic", |
"The contents of half-word elements of vector/floating-point register vfrA are " |
"shifted right by the number of bits specified in lower 4 bits in each half-word element " |
"of vector/floating-point register vfrB, inserting most significant bit of each element " |
"into the low-order bits. " |
"Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[15:0] <- vfrA[15:0] sra vfrB[3:0]\\" |
"vfrD[31:16] <- vfrA[31:16] sra vfrB[19:16]\\" |
"vfrD[47:32] <- vfrA[47:32] sra vfrB[35:32]\\" |
"vfrD[63:48] <- vfrA[63:48] sra vfrB[51:48]\\", |
"None", ORVDX64I,}, |
|
{"lv.rl.b", "Vector Byte Elements Rotate Left", |
"The contents of byte elements of vector/floating-point register vfrA are " |
"rotated left by the number of bits specified in lower 3 bits in each byte element " |
"of vector/floating-point register vfrB. " |
"Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[7:0] <- vfrA[7:0] rl vfrB[2:0]\\" |
"vfrD[15:8] <- vfrA[15:8] rl vfrB[10:8]\\" |
"vfrD[23:16] <- vfrA[23:16] rl vfrB[18:16]\\" |
"vfrD[31:24] <- vfrA[31:24] rl vfrB[26:24]\\" |
"vfrD[39:32] <- vfrA[39:32] rl vfrB[34:32]\\" |
"vfrD[47:40] <- vfrA[47:40] rl vfrB[42:40]\\" |
"vfrD[55:48] <- vfrA[55:48] rl vfrB[50:48]\\" |
"vfrD[63:56] <- vfrA[63:56] rl vfrB[58:56]", |
"None", ORVDX64I,}, |
|
{"lv.rl.h", "Vector Half-Word Elements Rotate Left", |
"The contents of half-word elements of vector/floating-point register vfrA are " |
"rotated left by the number of bits specified in lower 4 bits in each half-word element " |
"of vector/floating-point register vfrB. " |
"Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[15:0] <- vfrA[15:0] rl vfrB[3:0]\\" |
"vfrD[31:16] <- vfrA[31:16] rl vfrB[19:16]\\" |
"vfrD[47:32] <- vfrA[47:32] rl vfrB[35:32]\\" |
"vfrD[63:48] <- vfrA[63:48] rl vfrB[51:48]\\", |
"None", ORVDX64I,}, |
|
{"lv.sll", "Vector Shift Left Logical", |
"The contents of vector/floating-point register vfrA are " |
"shifted left by the number of bits specified in lower 4 bits in each byte element " |
"of vector/floating-point register vfrB, inserting zeros into the low-order bits of " |
"vfrD. " |
"Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[63:0] <- vfrA[63:0] << vfrB[2:0]", |
"None", ORVDX64I,}, |
|
{"lv.srl", "Vector Shift Right Logical", |
"The contents of vector/floating-point register vfrA are " |
"shifted right by the number of bits specified in lower 4 bits in each byte element " |
"of vector/floating-point register vfrB, inserting zeros into the high-order bits of " |
"vfrD. " |
"Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[63:0] <- vfrA[63:0] >> vfrB[2:0]", |
"None", ORVDX64I,}, |
|
{"lv.merge.b", "Vector Byte Elements Merge", |
"Byte elements of the lower half of the vector/floating-point register vfrA are " |
"combined with the byte elements of the lower half of vector/floating-point " |
"register vfrB in such a way that lowest element is from the vfrB, second element " |
"from the vfrA, third again from the vfrB etc. " |
"Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[7:0] <- vfrB[7:0]\\" |
"vfrD[15:8] <- vfrA[15:8]\\" |
"vfrD[23:16] <- vfrB[23:16]\\" |
"vfrD[31:24] <- vfrA[31:24]\\" |
"vfrD[39:32] <- vfrB[39:32]\\" |
"vfrD[47:40] <- vfrA[47:40]\\" |
"vfrD[55:48] <- vfrB[55:48]\\" |
"vfrD[63:56] <- vfrA[63:56]", |
"None", ORVDX64I,}, |
|
{"lv.merge.h", "Vector Half-Word Elements Merge", |
"Half-word elements of the lower half of the vector/floating-point register vfrA are " |
"combined with the byte elements of the lower half of vector/floating-point " |
"register vfrB in such a way that lowest element is from the vfrB, second element " |
"from the vfrA, third again from the vfrB etc. " |
"Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[15:0] <- vfrB[15:0]\\" |
"vfrD[31:16] <- vfrA[31:16]\\" |
"vfrD[47:32] <- vfrB[47:32]\\" |
"vfrD[63:48] <- vfrA[63:48]", |
"None", ORVDX64I,}, |
|
{"lv.pack.b", "Vector Byte Elements Pack", |
"Lower half of the byte elements of the vector/floating-point register vfrA are " |
"truncated and combined with the lower half of the byte truncated elements of the " |
"vector/floating-point register vfrB in such a way that lowest elements are from " |
"vfrB and highest element from vfrA. " |
"Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[3:0] <- vfrB[3:0]\\" |
"vfrD[7:4] <- vfrB[11:8]\\" |
"vfrD[11:8] <- vfrB[19:16]\\" |
"vfrD[15:12] <- vfrB[27:24]\\" |
"vfrD[19:16] <- vfrB[35:32]\\" |
"vfrD[23:20] <- vfrB[43:40]\\" |
"vfrD[27:24] <- vfrB[51:48]\\" |
"vfrD[31:28] <- vfrB[59:56]\\" |
"vfrD[35:32] <- vfrA[3:0]\\" |
"vfrD[39:36] <- vfrA[11:8]\\" |
"vfrD[43:40] <- vfrA[19:16]\\" |
"vfrD[47:44] <- vfrA[27:24]\\" |
"vfrD[51:48] <- vfrA[35:32]\\" |
"vfrD[55:52] <- vfrA[43:40]\\" |
"vfrD[59:56] <- vfrA[51:48]\\" |
"vfrD[63:60] <- vfrA[59:56]", |
"None", ORVDX64I,}, |
|
{"lv.pack.h", "Vector Half-word Elements Pack", |
"Lower half of the half-word elements of the vector/floating-point register vfrA are " |
"truncated and combined with the lower half of the half-word truncated elements of the " |
"vector/floating-point register vfrB in such a way that lowest elements are from vfrB and highest element " |
"from vfrA. " |
"Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[7:0] <- vfrB[15:0]\\" |
"vfrD[15:8] <- vfrB[31:16]\\" |
"vfrD[23:16] <- vfrB[47:32]\\" |
"vfrD[31:24] <- vfrB[63:48]\\" |
"vfrD[39:32] <- vfrA[15:0]\\" |
"vfrD[47:40] <- vfrA[31:16]\\" |
"vfrD[55:48] <- vfrA[47:32]\\" |
"vfrD[63:56] <- vfrA[63:48]\\", |
"None", ORVDX64I,}, |
|
{"lv.packs.b", "Vector Byte Elements Pack Signed Saturated", |
"Lower half of the signed byte elements of the vector/floating-point register vfrA are " |
"truncated and combined with the lower half of the signed byte truncated elements of " |
"the vector/floating-point register vfrB in such a way that lowest elements are from " |
"vfrB and highest element from vfrA. " |
"If any truncated element exceeds signed 4-bit value, it is saturated. " |
"Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[3:0] <- sat4s(vfrB[7:0]\\" |
"vfrD[7:4] <- sat4s(vfrB[15:8]\\" |
"vfrD[11:8] <- sat4s(vfrB[23:16]\\" |
"vfrD[15:12] <- sat4s(vfrB[31:24]\\" |
"vfrD[19:16] <- sat4s(vfrB[39:32]\\" |
"vfrD[23:20] <- sat4s(vfrB[47:40]\\" |
"vfrD[27:24] <- sat4s(vfrB[55:48]\\" |
"vfrD[31:28] <- sat4s(vfrB[63:56]\\" |
"vfrD[35:32] <- sat4s(vfrA[7:0]\\" |
"vfrD[39:36] <- sat4s(vfrA[15:8]\\" |
"vfrD[43:40] <- sat4s(vfrA[23:16]\\" |
"vfrD[47:44] <- sat4s(vfrA[31:24]\\" |
"vfrD[51:48] <- sat4s(vfrA[39:32]\\" |
"vfrD[55:52] <- sat4s(vfrA[47:40]\\" |
"vfrD[59:56] <- sat4s(vfrA[55:48]\\" |
"vfrD[63:60] <- sat4s(vfrA[63:56]", |
"None", ORVDX64I,}, |
|
{"lv.packs.h", "Vector Half-word Elements Pack Signed Saturated", |
"Lower half of the signed halfpword elements of the vector/floating-point register " |
"vfrA are truncated and combined with the lower half of the signed half-word " |
"truncated elements of the vector/floating-point register vfrB in such a way " |
"that lowest elements are from vfrB and highest element from vfrA. " |
"If any truncated element exceeds signed 8-bit value, it is saturated. " |
"Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[7:0] <- sat8s(vfrB[15:0])\\" |
"vfrD[15:8] <- sat8s(vfrB[31:16])\\" |
"vfrD[23:16] <- sat8s(vfrB[47:32])\\" |
"vfrD[31:24] <- sat8s(vfrB[63:48])\\" |
"vfrD[39:32] <- sat8s(vfrA[15:0])\\" |
"vfrD[47:40] <- sat8s(vfrA[31:16])\\" |
"vfrD[55:48] <- sat8s(vfrA[47:32])\\" |
"vfrD[63:56] <- sat8s(vfrA[63:48])\\", |
"None", ORVDX64I,}, |
|
{"lv.packus.b", "Vector Byte Elements Pack Unsigned Saturated", |
"Lower half of the unsigned byte elements of the vector/floating-point register vfrA are " |
"truncated and combined with the lower half of the unsigned byte truncated elements of " |
"the vector/floating-point register vfrB in such a way that lowest elements are from " |
"vfrB and highest element from vfrA. " |
"If any truncated element exceeds unsigned 4-bit value, it is saturated. " |
"Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[3:0] <- sat4u(vfrB[7:0]\\" |
"vfrD[7:4] <- sat4u(vfrB[15:8]\\" |
"vfrD[11:8] <- sat4u(vfrB[23:16]\\" |
"vfrD[15:12] <- sat4u(vfrB[31:24]\\" |
"vfrD[19:16] <- sat4u(vfrB[39:32]\\" |
"vfrD[23:20] <- sat4u(vfrB[47:40]\\" |
"vfrD[27:24] <- sat4u(vfrB[55:48]\\" |
"vfrD[31:28] <- sat4u(vfrB[63:56]\\" |
"vfrD[35:32] <- sat4u(vfrA[7:0]\\" |
"vfrD[39:36] <- sat4u(vfrA[15:8]\\" |
"vfrD[43:40] <- sat4u(vfrA[23:16]\\" |
"vfrD[47:44] <- sat4u(vfrA[31:24]\\" |
"vfrD[51:48] <- sat4u(vfrA[39:32]\\" |
"vfrD[55:52] <- sat4u(vfrA[47:40]\\" |
"vfrD[59:56] <- sat4u(vfrA[55:48]\\" |
"vfrD[63:60] <- sat4u(vfrA[63:56]", |
"None", ORVDX64I,}, |
|
{"lv.packus.h", "Vector Half-word Elements Pack Unsigned Saturated", |
"Lower half of the unsigned halfpword elements of the vector/floating-point register " |
"vfrA are truncated and combined with the lower half of the unsigned half-word " |
"truncated elements of the vector/floating-point register vfrB in such a way " |
"that lowest elements are from vfrB and highest element from vfrA. " |
"If any truncated element exceeds unsigned 8-bit value, it is saturated. " |
"Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[7:0] <- sat8u(vfrB[15:0])\\" |
"vfrD[15:8] <- sat8u(vfrB[31:16])\\" |
"vfrD[23:16] <- sat8u(vfrB[47:32])\\" |
"vfrD[31:24] <- sat8u(vfrB[63:48])\\" |
"vfrD[39:32] <- sat8u(vfrA[15:0])\\" |
"vfrD[47:40] <- sat8u(vfrA[31:16])\\" |
"vfrD[55:48] <- sat8u(vfrA[47:32])\\" |
"vfrD[63:56] <- sat8u(vfrA[63:48])\\", |
"None", ORVDX64I,}, |
|
{"lv.unpack.b", "Vector Byte Elements Unpack", |
"Lower half of 4-bit elements in vector/floating-point register " |
"vfrA are sign-extended and placed into vector/floating-point register vfrD.", |
"", |
"vfrD[7:0] <- exts(vfrA[3:0])\\" |
"vfrD[15:8] <- exts(vfrA[7:4])\\" |
"vfrD[23:16] <- exts(vfrA[11:8])\\" |
"vfrD[31:24] <- exts(vfrA[15:12])\\" |
"vfrD[39:32] <- exts(vfrA[19:16])\\" |
"vfrD[47:40] <- exts(vfrA[23:20])\\" |
"vfrD[55:48] <- exts(vfrA[27:24])\\" |
"vfrD[63:56] <- exts(vfrA[31:28])", |
"None", ORVDX64I,}, |
|
{"lv.unpack.h", "Vector Half-Word Elements Unpack", |
"Lower half of 8-bit elements in vector/floating-point register " |
"vfrA are sign-extended and placed into vector/floating-point register vfrD.", |
"", |
"vfrD[15:0] <- exts(vfrA[7:0])\\" |
"vfrD[31:16] <- exts(vfrA[15:8])\\" |
"vfrD[47:32] <- exts(vfrA[23:16])\\" |
"vfrD[63:48] <- exts(vfrA[31:24])\\", |
"None", ORVDX64I,}, |
|
{"lv.perm.n", "Vector Nibble Elements Permute", |
"The 4-bit elements of vector/floating-point register vfrA are " |
"permuted according to corresponding 4-bit values in vector/floating-point " |
"register vfrB. " |
"Result elements are placed into vector/floating-point register vfrD.", |
"", |
"vfrD[3:0] <- vfrA[vfrB[3:0]*4+3:vfrB[3:0]*4]\\" |
"vfrD[7:4] <- vfrA[vfrB[7:4]*4+3:vfrB[7:4]*4]\\" |
"vfrD[11:8] <- vfrA[vfrB[11:8]*4+3:vfrB[11:8]*4]\\" |
"vfrD[15:12] <- vfrA[vfrB[15:12]*4+3:vfrB[15:12]*4]\\" |
"vfrD[19:16] <- vfrA[vfrB[19:16]*4+3:vfrB[19:16]*4]\\" |
"vfrD[23:20] <- vfrA[vfrB[23:20]*4+3:vfrB[23:20]*4]\\" |
"vfrD[27:24] <- vfrA[vfrB[27:24]*4+3:vfrB[27:24]*4]\\" |
"vfrD[31:28] <- vfrA[vfrB[31:28]*4+3:vfrB[31:28]*4]\\" |
"vfrD[35:32] <- vfrA[vfrB[35:32]*4+3:vfrB[35:32]*4]\\" |
"vfrD[39:36] <- vfrA[vfrB[39:36]*4+3:vfrB[39:36]*4]\\" |
"vfrD[43:40] <- vfrA[vfrB[43:40]*4+3:vfrB[43:40]*4]\\" |
"vfrD[47:44] <- vfrA[vfrB[47:44]*4+3:vfrB[47:44]*4]\\" |
"vfrD[51:48] <- vfrA[vfrB[51:48]*4+3:vfrB[51:48]*4]\\" |
"vfrD[55:52] <- vfrA[vfrB[55:52]*4+3:vfrB[55:52]*4]\\" |
"vfrD[59:56] <- vfrA[vfrB[59:56]*4+3:vfrB[59:56]*4]\\" |
"vfrD[63:60] <- vfrA[vfrB[63:60]*4+3:vfrB[63:60]*4]", |
"None", ORVDX64I,}, |
|
{"lv.madds.h", "Vector Half-Word Elements Multiply Add Signed Saturated", |
"The signed half-word elements of vector/floating-point register vfrA are multiplied " |
"by the signed half-word elements of vector/floating-point register vfrB to form " |
"intermediate results. They are added to the signed half-word VMAC elements to " |
"form the final results that are placed again in VMAC registers. " |
"Intermediate result is placed into vector/floating-point register vfrD. " |
"If any of the final results exceeds min/max value, it is saturated.", |
"", |
"vfrD[15:0] <- sat32s(vfrA[15:0] * vfrB[15:0] + VMACLO[31:0])\\" |
"vfrD[31:16] <- sat32s(vfrA[31:16] * vfrB[31:16] + VMACLO[63:32])\\" |
"vfrD[47:32] <- sat32s(vfrA[47:32] * vfrB[47:32] + VMACHI[31:0])\\" |
"vfrD[63:48] <- sat32s(vfrA[63:48] * vfrB[63:48] + VMACHI[63:32])\\", |
"None", ORVDX64I,}, |
|
{"lv.msubs.h", "Vector Half-Word Elements Multiply Subtract Signed Saturated", |
"The signed half-word elements of vector/floating-point register vfrA are multiplied " |
"by the signed half-word elements of vector/floating-point register vfrB to form " |
"intermediate results. They are subtracted from the signed half-word VMAC elements to " |
"form the final results that are placed again in VMAC registers. " |
"Intermediate result is placed into vector/floating-point register vfrD. " |
"If any of the final results exceeds min/max value, it is saturated.", |
"", |
"vfrD[15:0] <- sat32s(VMACLO[31:0] - vfrA[15:0] * vfrB[15:0])\\" |
"vfrD[31:16] <- sat32s(VMACLO[63:32] - vfrA[31:16] * vfrB[31:16])\\" |
"vfrD[47:32] <- sat32s(VMACHI[31:0] - vfrA[47:32] * vfrB[47:32])\\" |
"vfrD[63:48] <- sat32s(VMACHI[63:32] - vfrA[63:48] * vfrB[63:48])\\", |
"None", ORVDX64I,}, |
|
{"lv.vtosf", "Vector Half-Word Element Convert To Single-Precision Floating-Point", |
"The least significant half-word element of vector/floating-point register vfrA " |
"is converted to single-precision floating-point number and stored into " |
"vector/floating-point register vfrD. ", |
"", |
"vfrD[31:0] <- itof(vfrA[15:0])\\" |
"vfrD[63:32] <- 0\\", |
"None", ORVDX64I,}, |
|
{"lv.vtodf", "Vector Half-Word Element Convert To Double-Precision Floating-Point", |
"The least significant half-word element of vector/floating-point register vfrA " |
"is converted to double-precision floating-point number and stored into " |
"vector/floating-point register vfrD. ", |
"", |
"vfrD[63:0] <- itof(vfrA[15:0])\\", |
"None", ORVDX64I,}, |
|
|
{"", "", "", "", "", "", 0} |
|
}; |
|
struct or1k_isa_classes { |
464,12 → 2243,29
char *table; |
} or1k_isa_classes[] = { |
|
{ "Class 0", "Invalid instruction class", "&&\\\\", }, |
{ "Class 1", "x", "Core CPU&User and Supervisor&Mandatory always\\\\", }, |
{ "Class 2", "x", "Core CPU&User and Supervisor&Recommended\\\\", }, |
{ "Class 3", "x", "Core CPU&User and Supervisor&Optional\\\\", }, |
{ "Class 4", "x", "System Management&Supervisor only&Mandatory always\\\\", }, |
{ "Class 5", "x", "Cache Management&Supervisor only&Mandatory if cache supported\\\\", }, |
{ "Class 6", "x", "Virtual Memory&Supervisor only&Mandatory if MMU supported\\\\", }, |
{ "", "x", "-&-\\", }, |
{ "", "x", "ORBIS32 I&Required\\", }, |
{ "", "x", "ORBIS32 II&Optional\\", }, |
{ "", "x", "ORBIS64 I&Required\\", }, |
{ "", "x", "ORBIS64 II&Optional\\", }, |
{ "", "x", "ORFPX32 I&Required\\", }, |
{ "", "x", "ORFPX32 II&Optional\\", }, |
{ "", "x", "ORFPX64 I&Required\\", }, |
{ "", "x", "ORFPX64 II&Optional\\", }, |
{ "", "x", "ORVDX64 I&Required\\", }, |
{ "", "x", "ORVDX64 II&Optional\\", }, |
{ "", "x", "&\\", }, |
|
}; |
|
struct or1k_order { |
char *title; |
unsigned long classes; |
} or1k_order[] = { |
|
{ "ORBIS32/64", (1<<ORBIS32I)>>1 | (1<<ORBIS32II)>>1 | (1<<ORBIS64I)>>1 | (1<<ORBIS64II)>>1, }, |
{ "ORFPX32/64", (1<<ORFPX32I)>>1 | (1<<ORFPX32II)>>1 | (1<<ORFPX64I)>>1 | (1<<ORFPX64II)>>1, }, |
{ "ORVDX64", (1<<ORVDX64I)>>1 | (1<<ORVDX64II)>>1, }, |
{ "", 0, }, |
|
}; |
/trunk/gen_or1k_isa/sources/chop_html.c
0,0 → 1,321
#include <stdio.h> |
#include <string.h> |
|
int section = 0; |
int table = 0; |
int tableend = 0; |
int bq = 0; |
int bqend = 0; |
int did_main2start; |
|
#define MAIN1_FILE "tmp/main1.html" |
#define MAIN2_FILE "tmp/main2.html" |
#define HF_FILE "tmp/hf.html" |
#define ISAHTMLSRC_FILE "tmp/isa.html" |
|
/* Which tables go into header? */ |
#define HSTART 1 |
#define HEND 2 |
|
/* Which tables go into footer? */ |
#define FSTART 3 |
#define FEND 3 |
|
void do_main1() |
{ |
FILE *f; |
|
f = fopen(MAIN1_FILE, "a"); |
if (!f) { |
perror("do_main1()/fopen:"); |
exit(1); |
} |
|
fprintf(f, "@page ISA%d\n", section); |
fprintf(f, "\t{size:8.5in 11.0in;\n"); |
fprintf(f, "\tmargin:1.0in 1.25in 1.0in 1.25in;\n"); |
fprintf(f, "\tmso-header-margin:.5in;\n"); |
fprintf(f, "\tmso-footer-margin:.5in;\n"); |
fprintf(f, "\tmso-header:url(\"./hf.html\") ISA%dh;\n", section); |
fprintf(f, "\tmso-footer:url(\"./hf.html\") ISA%df;\n", section); |
fprintf(f, "\tmso-paper-source:0;}\n"); |
fprintf(f, "div.ISA%d\n", section); |
fprintf(f, "\t{page:ISA%d;}\n", section); |
fclose(f); |
} |
|
void do_main2start() |
{ |
FILE *f; |
|
f = fopen(MAIN2_FILE, "a"); |
if (!f) { |
perror("do_main2start()/fopen:"); |
exit(1); |
} |
|
did_main2start = 1; |
fprintf(f, "<div class=ISA%d style='text-align:justify'><br><br>\n", section); |
fclose(f); |
} |
|
void do_main2end() |
{ |
FILE *f; |
|
f = fopen(MAIN2_FILE, "a"); |
if (!f) { |
perror("do_main2end()/fopen:"); |
exit(1); |
} |
|
if (did_main2start) { |
fprintf(f, "</div>\n"); |
fprintf(f, "<span><br clear=all style='page-break-before:always;mso-break-type:section-break'>\n"); |
fprintf(f, "</span>\n"); |
did_main2start = 0; |
} |
fclose(f); |
} |
|
void do_main2(char *line) |
{ |
FILE *f; |
|
f = fopen(MAIN2_FILE, "a"); |
if (!f) { |
perror("do_main2()/fopen:"); |
exit(1); |
} |
|
fprintf(f, "%s\n", line); |
fclose(f); |
} |
|
void create_main2() |
{ |
FILE *f; |
|
f = fopen(MAIN2_FILE, "w"); |
if (!f) { |
perror("create_main2()/fopen:"); |
exit(1); |
} |
|
fprintf(f, "-->\n"); |
fprintf(f, "</style>\n"); |
fprintf(f, "</head>\n"); |
fprintf(f, "<body lang=EN-US style='tab-interval:.5in'>\n"); |
fclose(f); |
} |
|
void finish_main2() |
{ |
FILE *f; |
|
f = fopen(MAIN2_FILE, "a"); |
if (!f) { |
perror("finish_main2()/fopen:"); |
exit(1); |
} |
|
fprintf(f, "</body>\n"); |
fprintf(f, "</html>\n"); |
fclose(f); |
} |
|
void create_hf() |
{ |
FILE *f; |
|
f = fopen(HF_FILE, "w"); |
if (!f) { |
perror("create_hf()/fopen:"); |
exit(1); |
} |
|
fprintf(f, "<html xmlns:v=\"urn:schemas-microsoft-com:vml\"\n"); |
fprintf(f, "xmlns:o=\"urn:schemas-microsoft-com:office:office\"\n"); |
fprintf(f, "xmlns:w=\"urn:schemas-microsoft-com:office:word\"\n"); |
fprintf(f, "xmlns=\"http://www.w3.org/TR/REC-html40\">\n\n"); |
|
fprintf(f, "<head>\n"); |
fprintf(f, "<meta http-equiv=Content-Type content=\"text/html; charset=windows-1252\">\n"); |
fprintf(f, "<link id=Main-File rel=Main-File href=\"or1k_isa.html\">\n"); |
fprintf(f, "</head>\n\n"); |
|
fprintf(f, "<body lang=EN-US>\n\n"); |
fclose(f); |
} |
|
void finish_hf() |
{ |
FILE *f; |
|
f = fopen(HF_FILE, "a"); |
if (!f) { |
perror("finish_hf()/fopen:"); |
exit(1); |
} |
|
fprintf(f, "</body>\n"); |
fprintf(f, "</html>\n"); |
fclose(f); |
} |
|
void do_hstart() |
{ |
FILE *f; |
|
f = fopen(HF_FILE, "a"); |
if (!f) { |
perror("do_hstart()/fopen:"); |
exit(1); |
} |
|
fprintf(f, "<div style='mso-element:header' id=ISA%dh><p class=MsoHeader>\n", section); |
fclose(f); |
} |
|
void do_fstart() |
{ |
FILE *f; |
|
f = fopen(HF_FILE, "a"); |
if (!f) { |
perror("do_fstart()/fopen:"); |
exit(1); |
} |
|
fprintf(f, "<div style='mso-element:footer' id=ISA%df><p class=MsoFooter>\n", section); |
fclose(f); |
} |
|
void do_hfend() |
{ |
FILE *f; |
|
f = fopen(HF_FILE, "a"); |
if (!f) { |
perror("do_hfend()/fopen:"); |
exit(1); |
} |
|
fprintf(f, "</p></div>\n"); |
fclose(f); |
} |
|
void do_hf(char * line) |
{ |
FILE *f; |
|
f = fopen(HF_FILE, "a"); |
if (!f) { |
perror("do_hf()/fopen:"); |
exit(1); |
} |
|
fprintf(f, "%s\n", line); |
fclose(f); |
} |
|
void processline(char *line) |
{ |
if (strstr(line, "<hr")) { |
do_main2end(); |
section++; |
table = 0; |
tableend = 0; |
do_main1(); |
do_main2start(); |
bq = 0; |
bqend = 0; |
} |
|
if (strstr(line, "<table")) { |
table++; |
if (table == HSTART) { |
do_hstart(); |
} |
if (table == FSTART) { |
do_fstart(); |
} |
} |
|
if (strstr(line, "</table>")) { |
tableend++; |
if (tableend == HEND) { |
do_hf(line); |
do_hfend(); |
} |
if (tableend == FEND) { |
do_hf(line); |
do_hfend(); |
} |
} else |
if ((tableend == HEND) && (table == HEND)) { |
char *bqp; |
char *bqendp; |
|
bqp = strstr(line, "<blockquote>"); |
bqendp = strstr(line, "</blockquote>"); |
|
if (bqp) |
bq++; |
if (bqendp) |
bqend++; |
|
if ((bq > 2) && bqp) { |
*bqp = '\0'; |
do_main2(line); |
do_main2("<left>"); |
*bqp = '<'; |
do_main2(bqp); |
} else |
if ((bqend > 2) && bqendp) { |
*bqendp = '\0'; |
do_main2(line); |
do_main2("</left>"); |
*bqendp = '<'; |
do_main2(bqendp); |
} |
else |
do_main2(line); |
} |
|
if (((table == HSTART) || (table == HEND)) && (tableend < HEND)) |
do_hf(line); |
|
if (table == FSTART) |
do_hf(line); |
} |
|
void readsrc(char *filename) |
{ |
FILE *f; |
char line[4000]; |
|
f = fopen(filename, "r"); |
if (!f) { |
perror("readsrc()/fopen:"); |
exit(1); |
} |
|
create_main2(); |
create_hf(); |
|
while (!feof(f)) { |
fscanf(f, "%s", line); |
processline(line); |
/* printf("%s\n", line); */ |
} |
fclose(f); |
|
finish_main2(); |
finish_hf(); |
} |
|
void main() |
{ |
readsrc(ISAHTMLSRC_FILE); |
} |