URL
https://opencores.org/ocsvn/uart16550/uart16550/trunk
Subversion Repositories uart16550
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- This comparison shows the changes necessary to convert path
/
- from Rev 86 to Rev 87
- ↔ Reverse comparison
Rev 86 → Rev 87
/trunk/rtl/verilog/uart_regs.v
62,6 → 62,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.39 2002/07/29 21:16:18 gorban |
// The uart_defines.v file is included again in sources. |
// |
// Revision 1.38 2002/07/22 23:02:23 gorban |
// Bug Fixes: |
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
585,7 → 588,7
|
always @(posedge clk or posedge wb_rst_i) |
if (wb_rst_i) lsr0r <= #1 0; |
else lsr0r <= #1 (rf_count==1 && fifo_read || rx_reset) ? 0 : // deassert condition |
else lsr0r <= #1 (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 0 : // deassert condition |
lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted |
|
// lsr bit 1 (receiver overrun) |
/trunk/rtl/verilog/uart_rfifo.v
60,6 → 60,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/07/29 21:16:18 gorban |
// The uart_defines.v file is included again in sources. |
// |
// Revision 1.1 2002/07/22 23:02:23 gorban |
// Bug Fixes: |
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
227,7 → 230,6
count <= #1 count - 1'b1; |
end |
2'b11 : begin |
fifo[bottom] <= #1 0; |
bottom <= #1 bottom + 1'b1; |
top <= #1 top_plus_1; |
fifo[top] <= #1 data_in[2:0]; |
245,7 → 247,7
if(fifo_reset | reset_status) |
overrun <= #1 1'b0; |
else |
if(push & (count==fifo_depth)) |
if(push & ~pop & (count==fifo_depth)) |
overrun <= #1 1'b1; |
end // always |
|
/trunk/rtl/verilog/uart_defines.v
63,6 → 63,22
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.12 2002/07/22 23:02:23 gorban |
// Bug Fixes: |
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
// Problem reported by Kenny.Tung. |
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. |
// |
// Improvements: |
// * Made FIFO's as general inferrable memory where possible. |
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). |
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. |
// |
// * Added optional baudrate output (baud_o). |
// This is identical to BAUDOUT* signal on 16550 chip. |
// It outputs 16xbit_clock_rate - the divided clock. |
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. |
// |
// Revision 1.10 2001/12/11 08:55:40 mohor |
// Scratch register define added. |
// |
112,7 → 128,7
// remove comments to restore use to the old version with 8 data bit interface |
// in new mode (32bit bus), the wb_sel_i signal is used to pus data in correct place |
// also, in 8-bit version there'll be no debugging features included |
//`define DATA_BUS_WIDTH_8 |
`define DATA_BUS_WIDTH_8 |
|
`ifdef DATA_BUS_WIDTH_8 |
`define UART_ADDR_WIDTH 3 |