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Rev 87 → Rev 88

/trunk/tests/boot/boot.s
49,8 → 49,9
 
!! Set LSU Diagnostic Register to use all ways for L1-icache and L1-dcache
!!setx cregs_lsu_diag_reg_r64, %g1, %l1 !!la variabile (cregs_lsu_diag_reg_r64) contiene il valore 0 (defines.h)
!!ho sostituito questa istruzione con la sua espansione (!! aka "clr %l1")
!!setx cregs_lsu_diag_reg_r64, %g1, %l1
!! cregs_lsu_diag_reg_r64 has value 0 in file defines.h;
!! this instruction has been expanded to:
sethi %hh(0x0),%g1
or %g1,%hm(0x0),%g1
sllx %g1,32,%g1
58,10 → 59,9
or %l1,%g1,%l1
or %l1,%lo(0x0),%l1
 
!! clear to zero the register ASI_LSU_DIAG_REG thus enabling all ways of cache and using the "random replacement" algorithm
mov 0x10, %g1
stxa %l1, [%g1] (66) !! pone a zero il registro ASI_LSU_DIAG_REG ottenendo
!!l'abilitazione di tutte le vie della cache e l'utilizzo
!!dell'algoritmo "random replacement" (aka "stxa %l1, [%g1] ASI_LSU_DIAG_REG")
stxa %l1, [%g1] (66)
 
!! Set LSU Control Register to enable L1-icache and L1-dcache: not enabled in S1 Core
/*
68,55 → 68,52
setx (CREGS_LSU_CTL_REG_IC | (CREGS_LSU_CTL_REG_DC << 1)), %g1, %l1 !! aka "mov 3, %l1"
stxa %l1, [ %g0 ] (69) !! aka "stxa %l1, [%g0] ASI_LSU_CTL_REG"
*/
 
!! Set hpstate.red = 0 and hpstate.enb = 1
rdhpr %hpstate, %l1
and %l1,0x820,%l2
xor %l2,0x800,%l2
wrhpr %l1,%l2,%hpstate !!questo meccanismo "dovrebbe" assicurarmi red=0 enb=1 mantenendo inalterati gli altri bit del registro
!!wrhpr %l1, 0x820, %hpstate !! vecchia istruzione: otteniamo red=0 ed enb=1 solo se in precedenza avevamo red=1 ed enb=0
wrhpr %l1,%l2,%hpstate !! this mechanism should ensure red=0 and enb=1 leaving the other 2 bits of the register unchanged;
!!wrhpr %l1, 0x820, %hpstate !! with the old instruction we got red=0 and enb=1 only if previously they were red=1 and enb=0
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!istruzione aggiunte dal file dal file hboot_tlb_init.s
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!! Instructions added from file hboot_tlb_init.s !!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!! init all itlb entries
!! Init all itlb entries
mov 0x30, %g1
mov %g0, %g2
itlb_init_loop:
!!pulisce data e tag entry del buffer per TLB
stxa %g0, [ %g1 ] 0x50 !!IMMU TLB Tag Access register=0
stxa %g0, [ %g2 ] 0x55 !!IMMU TLB Data Access register=0, g2 assume valori da 0 a 0x7f8
itlb_init_loop:
!! clear data and tag entries of the TLB buffer
stxa %g0, [ %g1 ] 0x50 !! IMMU TLB Tag Access register=0
stxa %g0, [ %g2 ] 0x55 !! IMMU TLB Data Access register=0, g2 values from 0x000 to 0x7f8
 
add %g2, 8, %g2 !!g2= somma 8 (byte) alla volta (64 bit)
cmp %g2, 0x200 !!confronta con 512 (512*8=4096=0x1000), (ma al max VA=0x7F8 ?)
add %g2, 8, %g2 !! increment the g2 register 8 bytes every time (64 bits)
cmp %g2, 0x200 !! compare g2 with 512 (512*8=4096=0x1000), but max VA=0x7F8
bne itlb_init_loop !! if (g2!=512) then run another loop
nop
 
bne itlb_init_loop !!se g2!=da 0x200 ritorna all''inizio del loop
nop
! init all dtlb entries
!! Init all dtlb entries
mov 0x30, %g1
mov %g0, %g2
dtlb_init_loop:
stxa %g0, [ %g1 ] 0x58 !!DMMU TLB Tag Access register=0
stxa %g0, [ %g2 ] 0x5d !!ASI_DTLB_DATA_ACCESS_REG(DMMU TLB Data Access)=0 g2 assume valori da 0 a 0x7f8
stxa %g0, [ %g1 ] 0x58 !! DMMU TLB Tag Access register=0
stxa %g0, [ %g2 ] 0x5d !! ASI_DTLB_DATA_ACCESS_REG(DMMU TLB Data Access) is 0, g2 values from 0x000 to 0x7f8
 
add %g2, 8, %g2 !!incrementa g2 di 64 bit alla voltra
cmp %g2, 0x200 !!confronta g2 con 0x200
bne dtlb_init_loop !!se sono diversi ricomincia il loop
add %g2, 8, %g2 !! increment the g2 register 8 bytes every time (64 bits)
cmp %g2, 0x200 !! compare g2 with 512
bne dtlb_init_loop !! if (g2!=512) then run another loop
nop
 
 
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
! Clear itlb/dtlb valid
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
stxa %g0, [%g0] 0x60 ! ASI_ITLB_INVALIDATE_ALL(IMMU TLB Invalidate register)=0
!! Clear itlb/dtlb valid
stxa %g0, [%g0] 0x60 !! ASI_ITLB_INVALIDATE_ALL(IMMU TLB Invalidate register)=0
mov 0x8, %g1
stxa %g0, [%g0 + %g1] 0x60 ! ASI_DTLB_INVALIDATE_ALL(DMMU TLB Invalidate register)=0
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!da qui riprende il vecchio file boot.s
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
stxa %g0, [%g0 + %g1] 0x60 !! ASI_DTLB_INVALIDATE_ALL(DMMU TLB Invalidate register)=0
 
 
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!! End of instrted instructions, from here we are again in old file boot.s !!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
 
!! Initialize Interrupt Queue Registers: Currently disabled in S1 Core
/*
168,12 → 165,9
stxa %g0, [%g0 + %g1] 0x58 !DMMU Synchronous Fault Status register=0
 
!! Enable error trap
!!setx cregs_sparc_error_en_reg_r64, %g1, %l1 !! aka "stxa %l1, [%g0] ASI_SPARC_ERROR_EN_REG"
!!ho sostituito questa istruzione con la sua espansione
!!ponendo la costante cregs_sparc_error_en_reg_r64=3 (dal file defines.h)
!!l'effetto dovrebbe essere "trap on correctable error" e "trap on uncorrectable error"
!!(!!aka "mov 3, %l1")
!!inizio espansione
!! setx cregs_sparc_error_en_reg_r64, %g1, %l1
!! this instruction has been expanded using constant value cregs_sparc_error_en_reg_r64=3 (from file defines.h)
!! so the effect should be "trap on correctable error" and "trap on uncorrectable error"
sethi %hh(0x3),%g1
or %g1,%hm(0x3),%g1
sllx %g1,32,%g1
180,8 → 174,7
sethi %hi(0x3),%l1
or %l1,%g1,%l1
or %l1,%lo(0x3),%l1
stxa %l1, [%g0] (75) !!mette il contenuto di l1 nel registro "SPARC Error Enable reg"
!!fine espansione
stxa %l1, [%g0] (75) !! copy the content of the l1 register into the "SPARC Error Enable reg"
 
!! Enable L2-ucache error trap: Unused in S1 Core
/*
196,32 → 189,30
stx %l1, [%g1 + 0xc0]
*/
!! Load Partition ID (permette a S.O. multipli di condividere lo stesso TLB)
rd %asr26, %l1 !!%asr26 corrisponde allo Strand Status and Control register
set 0x0300, %g1 !! aka "sethi %hi(0x1c00), %g1" "or %g1, 0x300, %g1"
!! Load Partition ID (permits to multiple OSs to share the same TLB)
rd %asr26, %l1 !! %asr26 corresponds to the "Strand Status and Control register"
set 0x0300, %g1 !! same as "sethi %hi(0x1c00), %g1" "or %g1, 0x300, %g1"
and %l1, %g1, %l1
 
srlx %l1, 8, %l1 !! %l1 has thread ID
 
!!setx part_id_list, %g1, %g2 (part_id_list viene definito nel file hboot.s)
!! this instruction expands as (preso dal file ACCESS.TXT)
!!inizio espansione
sethi %hi(0), %g1
sethi %hi(0x4c000), %g2
mov %g1, %g1
mov %g2, %g2
sllx %g1, 0x20, %g1
or %g2, %g1, %g2
!!fine espansione
!!setx part_id_list, %g1, %g2 (part_id_list is defined in file hboot.s)
!! this instruction is expanded as:
sethi %hi(0), %g1
sethi %hi(0x4c000), %g2
mov %g1, %g1
mov %g2, %g2
sllx %g1, 0x20, %g1
or %g2, %g1, %g2
 
sllx %l1, 3, %l1 !! offset - partition list
ldx [%g2 + %l1], %g2 !! %g2 contains partition ID
sllx %l1, 3, %l1 !! offset - partition list
ldx [%g2 + %l1], %g2 !! %g2 contains partition ID
mov 0x80, %g1
stxa %g2, [%g1] 0x58 !!I/DMMU Partition ID=g2
stxa %g2, [%g1] 0x58 !! I/DMMU Partition ID=g2
 
!! Set Hypervisor Trap Base Address
!!setx HV_TRAP_BASE_PA, %l0, %l7 !!sostituita con la sua espansione e HV_TRAP_BASE_PA=0x80000(!!sethi %hi(0x80000), %l7)
!!inizio espansione
!! setx HV_TRAP_BASE_PA, %l0, %l7
!! being HV_TRAP_BASE_PA=0x80000 it expands to:
sethi %hh(0x80000),%g1
or %g1,%hm(0x80000),%g1
sllx %g1,32,%g1
228,9 → 219,8
sethi %hi(0x80000),%l1
or %l1,%g1,%l1
or %l1,%lo(0x80000),%l1
!!fine espansione
 
wrhpr %l7, %g0, %htba !!i bit da 63-14 servono a selezionare il trap vector per un trap servito in Hyperprivileged mode
wrhpr %l7, %g0, %htba !! bits 63-14 select the trap vector for a trap served in Hyperprivileged mode
 
!! Load TSB config/base from memory and write to corresponding ASI's
!! set tsb-reg (4 at present) for one partition
238,13 → 228,12
 
!!setx tsb_config_base_list, %l0, %g1
!! this instructions expands as
sethi %hi(0), %l0
sethi %hi(0x4c000), %g1
mov %l0, %l0
or %g1, 0x140, %g1
sllx %l0, 0x20, %l0
or %g1, %l0, %g1
!!fine espansione
sethi %hi(0), %l0
sethi %hi(0x4c000), %g1
mov %l0, %l0
or %g1, 0x140, %g1
sllx %l0, 0x20, %l0
or %g1, %l0, %g1
 
sllx %g2, 7, %g2 !! %g2 contains offset to tsb_config_base_list
add %g1, %g2, %g1 !! %g1 contains pointer to tsb_config_base_list
298,8 → 287,6
stxa %g0, [%o2] 0x57 !!registro ASI_IMMU_DEMAP=0 (IMMU TLB demap)
stxa %g0, [%o2] 0x5f !!registro ASI_DMMU_DEMAP=0 (DMMU TLB demap)
 
 
 
!! Initialize primary context register
mov 0x8, %l1
stxa %g0, [%l1] 0x21
315,28 → 302,27
*/
!! Set LSU Control Register to enable immu, dmmu but NOT icache, dcache
mov 0xc, %l1
stxa %l1, [%g0] (69) !!Load/Store Unit Control Register=1100 (aka "stxa %l1, [%g0] ASI_LSU_CTL_REG")
!!l''effetto dovrebbe essere:
!! .dm=1 (DMMU ENABLE)
!! .Im=1 (IMMU ENABLE)
!! .dc=0 (dcache not enabled)
!! .ic=0 (icache not enabled)
!!setx HPriv_Reset_Handler, %g1, %g2
stxa %l1, [%g0] (69)
!! Register 69 is "Load/Store Unit Control Register", and value 0xC=1100 corresponds to:
!! .dm=1 (DMMU ENABLE)
!! .Im=1 (IMMU ENABLE)
!! .dc=0 (dcache not enabled)
!! .ic=0 (icache not enabled)
 
!! setx HPriv_Reset_Handler, %g1, %g2
!! this instructions expands as
sethi %hi(0), %g1
sethi %hi(0x144000), %g2
mov %g1, %g1
mov %g2, %g2
sllx %g1, 0x20, %g1
or %g2, %g1, %g2
!! fine espansione
sethi %hi(0), %g1
sethi %hi(0x144000), %g2
mov %g1, %g1
mov %g2, %g2
sllx %g1, 0x20, %g1
or %g2, %g1, %g2
rdhpr %hpstate, %g3
wrpr 1, %tl !!livello trap corrente=1
wrpr 1, %tl !! current trap level = 1
 
!!setx cregs_htstate_r64, %g1, %g4
!! this instructions expands as !!sostituita con la successive istruzioni (da manuale) (!! aka "clr %g4")
!! inizio espansione
!! setx cregs_htstate_r64, %g1, %g4
!! this instructions expands as
sethi %hh(0x0),%g1
or %g1,%hm(0x0),%g1
sllx %g1,32,%g1
343,14 → 329,12
sethi %hi(0x0),%l1
or %l1,%g1,%l1
or %l1,%lo(0x0),%l1
!!fine espansione
 
wrhpr %g4, %g0, %htstate !! dovrebbe resettare il registro HTSTATE che mantiene lo stato hyperpriviliged dopo un trap
wrpr 0, %tl !! trap level corrente=0 (No Trap)
wrhpr %g4, %g0, %htstate !! it should reset the HTSTATE register that store the hyperpriviliged state after a trap
wrpr 0, %tl !! current trap level corrente = 0 (No Trap)
mov 0x0, %o0 !! aka "clr %o0", don't delete since used in customized IMMU miss trap
jmp %g2
wrhpr %g0, 0x800, %hpstate !!assicura il bit 11 del registro HPSTATE al valore 1 (per evitare comportamenti non previsti)
wrhpr %g0, 0x800, %hpstate !! ensure bit 11 of the HPSTATE register is set (to avoid unwanted behaviors)
nop
nop
 
 

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