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Rev 877 → Rev 878

/trunk/orpmon/include/support.h
43,11 → 43,14
extern int strcmp (const char *s1, const char *s2);
extern char *strcpy (char *dst0, char *src0);
 
/* defined in 'ctype.h'
#define isspace(c) ((c) == ' ' || (c) == '\t')
*/
 
extern volatile unsigned long timestamp;
extern void reset_timer (void);
extern unsigned long get_timer (unsigned long base);
extern void set_timer (unsigned long t);
extern void sleep(unsigned long sleep_time);
 
#endif
/trunk/orpmon/include/ctype.h
0,0 → 1,72
/*
ctype.h -- character types
Implements the usual ctype stuff (only valid for ASCII systems)
Copyright (C) 2002 Richard Herveille, rherveille@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
 
 
#ifndef __CTYPE_H
#define __CTYPE_H
 
/* basic types */
#define __CT_d 0x01 /* numeric digit */
#define __CT_u 0x02 /* upper case */
#define __CT_l 0x04 /* lower case */
#define __CT_c 0x08 /* control character */
#define __CT_s 0x10 /* whitespace */
#define __CT_p 0x20 /* punctuation */
#define __CT_x 0x40 /* hexadecimal */
#define __CT_b 0x80 /* blank (is also space) */
 
/* combination types */
#define __CT_lx (__CT_l | __CT_x) /* lower case hexadecimal */
#define __CT_ux (__CT_u | __CT_x) /* upper case hexadecimal */
 
#define __CT_space (__CT_s | __CT_b)
#define __CT_alphanum (__CT_l | __CT_u | __CT_d)
#define __CT_graph (__CT_l | __CT_u | __CT_d | __CT_p)
#define __CT_print (__CT_l | __CT_u | __CT_d | __CT_p | __CT_b)
 
extern const unsigned char __ctype_table[256];
 
#define _toupper(c) ( (c) ^ 0x20 )
#define _tolower(c) ( (c) ^ 0x20 )
#define toupper(c) ( islower(c) ? _tolower(c) : (c) )
#define tolower(c) ( isupper(c) ? _toupper(c) : (c) )
#define toascii(c) ( (c) & 0x7F )
 
 
/* standard defenitions are taken from man-pages */
/*#define isalnum(c) ( isalpha(c) || isdigit(c) ) */
#define isalnum(c) ( __ctype_table[(int) c] & __CT_alphanum )
/*#define isalpha(c) ( isupper(c) || islower(c) ) */
#define isalpha(c) ( __ctype_table[(int) c] & __CT_ul )
#define isascii(c) ( (c) & ~0x7F )
#define isblank(c) ( __ctype_table[(int) c] & __CT_b )
#define iscntrl(c) ( __ctype_table[(int) c] & __CT_c )
#define isdigit(c) ( __ctype_table[(int) c] & __CT_d )
#define isgraph(c) ( __ctype_table[(int) c] & __CT_graph )
#define islower(c) ( __ctype_table[(int) c] & __CT_l )
#define isprint(c) ( __ctype_table[(int) c] & __CT_print)
#define ispunct(c) ( __ctype_table[(int) c] & __CT_p )
#define isspace(c) ( __ctype_table[(int) c] & __CT_space )
#define isupper(c) ( __ctype_table[(int) c] & __CT_u )
#define isxdigit(c) ( __ctype_table[(int) c] & __CT_x )
 
#endif /* __CTYPE_H */
/trunk/orpmon/include/ata.h
0,0 → 1,310
/*
/////////////////////////////////////////////////////////////////////
//// ////
//// Include file for OpenCores ATA Controller (OCIDEC) ////
//// ////
//// File : oc_ata.h ////
//// Function: c-include file ////
//// ////
//// Authors: Richard Herveille (rherveille@opencores) ////
//// www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// rherveille@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
*/
 
/*
* Definitions for the Opencores ATA Controller Core
*/
 
#ifndef __OC_ATA_H
#define __OC_ATA_H
 
 
#define ATA_DEBUG
 
 
#define MAX_ATA_COMMANDS 100
 
 
#ifndef REG32
#define REG32(adr) *((volatile unsigned int *)(adr))
#endif
 
/* --- Register definitions --- */
 
/* ----- Core Registers */
#define ATA_CTRL 0x00 /* Control register */
#define ATA_STAT 0x04 /* Status register */
#define ATA_PCTR 0x08 /* PIO command timing register */
#define ATA_PFTR0 0x0c /* PIO Fast Timing register Device0 */
#define ATA_PFTR1 0x10 /* PIO Fast Timing register Device1 */
#define ATA_DTR0 0x14 /* DMA Timing register Device2 */
#define ATA_DTR1 0x18 /* DMA Timing register Device1 */
#define ATA_DTXB 0x3c /* DMA Transmit buffer */
#define ATA_RXB 0x3c /* DMA Receive buffer */
 
/* ----- ATA Registers */
#define ATA_ASR 0x78 /* Alternate Status Register (R) */
#define ATA_CR 0x5c /* Command Register (W) */
#define ATA_CHR 0x54 /* Cylinder High Register (R/W) */
#define ATA_CLR 0x50 /* Cylinder Low Register (R/W) */
#define ATA_DR 0x40 /* Data Register */
#define ATA_DCR 0x78 /* Device Control Register (W) */
#define ATA_DHR 0x58 /* Device/Head Register (R/W) */
#define ATA_ERR 0x44 /* Error Register (R) */
#define ATA_FR 0x44 /* Features Register (W) */
#define ATA_SCR 0x48 /* Sector Count Register (R/W) */
#define ATA_SNR 0x4c /* Sector Number Register (R/W) */
#define ATA_SR 0x5c /* Status Register (R) */
#define ATA_DA 0x7c /* Device Address Register (R) */
/* ATA/ATAPI-5 does not describe Device Status Register */
 
/* ---------------------------- */
/* ----- Bits definitions ----- */
/* ---------------------------- */
 
/* ----- Core Control register */
/* bits 31-16 are reserved */
#define ATA_DMA_EN (0<<15) /* DMAen, DMA enable bit */
/* bit 14 is reserved */
#define ATA_DMA_WR (1<<14) /* DMA Write transaction */
#define ATA_DMA_RD (0<<14) /* DMA Read transaction */
/* bits 13-10 are reserved */
#define ATA_BELEC1 (1<< 9) /* Big-Little endian conversion */
/* enable bit for Device1 */
#define ATA_BELEC0 (1<< 8) /* Big-Little endian conversion */
/* enable bit for Device0 */
#define ATA_IDE_EN (1<< 7) /* IDE core enable bit */
#define ATA_FTE1 (1<< 6) /* Device1 Fast PIO Timing Enable bit */
#define ATA_FTE0 (1<< 5) /* Device0 Fast PIO Timing Enable bit */
#define ATA_PWPP (1<< 4) /* PIO Write Ping-Pong Enable bit */
#define ATA_IORDY_FTE1 (1<< 3) /* Device1 Fast PIO Timing IORDY */
/* enable bit */
#define ATA_IORDY_FTE0 (1<< 2) /* Device0 Fast PIO Timing IORDY */
/* enable bit */
#define ATA_IORDY (1<< 1) /* PIO Command Timing IORDY enable bit*/
#define ATA_RST (1<< 0) /* ATA Reset bit */
 
/* ----- Core Status register */
#define ATA_DEVID 0xf0000000 /* bits 31-28 Device-ID */
#define ATA_REVNO 0x0f000000 /* bits 27-24 Revision number */
/* bits 23-16 are reserved */
#define ATA_DMA_TIP (1<<15) /* DMA Transfer in progress */
/* bits 14-10 are reserved */
#define ATA_DRBE (1<<10) /* DMA Receive buffer empty */
#define ATA_DTBF (1<< 9) /* DMA Transmit buffer full */
#define ATA_DMARQ (1<< 8) /* DMARQ Line status */
#define ATA_PIO_TIP (1<< 7 /* PIO Transfer in progress */
#define ATA_PWPPF (1<< 6) /* PIO write ping-pong full */
/* bits 5-1 are reserved */
#define ATA_IDEIS (1<< 0) /* IDE Interrupt status */
 
 
/* ----- Core Timing registers */
#define ATA_TEOC 24 /* End of cycle time DMA/PIO */
#define ATA_T4 16 /* DIOW- data hold time PIO */
#define ATA_T2 8 /* DIOR-/DIOW- pulse width PIO */
#define ATA_TD 8 /* DIOR-/DIOW- pulse width DMA */
#define ATA_T1 0 /* Address valid to DIOR-/DIOW- PIO */
#define ATA_TM 0 /* CS[1:0]valid to DIOR-/DIOW- DMA */
 
 
/* ----- ATA (Alternate) Status Register */
#define ATA_SR_BSY 0x80 /* Busy */
#define ATA_SR_DRDY 0x40 /* Device Ready */
#define ATA_SR_DF 0x20 /* Device Fault */
#define ATA_SR_DSC 0x10 /* Device Seek Complete */
#define ATA_SR_DRQ 0x08 /* Data Request */
#define ATA_SR_COR 0x04 /* Corrected data (obsolete) */
#define ATA_SR_IDX 0x02 /* (obsolete) */
#define ATA_SR_ERR 0x01 /* Error */
 
/* ----- ATA Device Control Register */
/* bits 7-3 are reserved */
#define ATA_DCR_RST 0x04 /* Software reset (RST=1, reset) */
#define ATA_DCR_IEN 0x02 /* Interrupt Enable (IEN=0, enabled) */
/* always write a '0' to bit0 */
 
/* ----- ATA Device Address Register */
/* All values in this register are one's complement (i.e. inverted) */
#define ATA_DAR_WTG 0x40 /* Write Gate */
#define ATA_DAR_H 0x3c /* Head Select */
#define ATA_DAR_DS1 0x02 /* Drive select 1 */
#define ATA_DAR_DS0 0x01 /* Drive select 0 */
 
/* ----- Device/Head Register */
#define ATA_DHR_LBA 0x40 /* LBA/CHS mode ('1'=LBA mode) */
#define ATA_DHR_DEV 0x10 /* Device ('0'=dev0, '1'=dev1) */
#define ATA_DHR_H 0x0f /* Head Select */
 
/* ----- Error Register */
#define ATA_ERR_BBK 0x80 /* Bad Block */
#define ATA_ERR_UNC 0x40 /* Uncorrectable Data Error */
#define ATA_ERR_IDNF 0x10 /* ID Not Found */
#define ATA_ERR_ABT 0x04 /* Aborted Command */
#define ATA_ERR_TON 0x02 /* Track0 Not Found */
#define ATA_ERR_AMN 0x01 /* Address Mark Not Found */
 
 
/* ---------------------------- */
/* ----- ATA commands ----- */
/* ---------------------------- */
#define CFA_ERASE_SECTORS 0xC0
#define CFA_REQUEST_EXTENDED_ERROR_CODE 0x03
#define CFA_TRANSLATE_SECTOR 0x87
#define CFA_WRITE_MULTIPLE_WITHOUT_ERASE 0xCD
#define CFA_WRITE_SECTORS_WITHOUT_ERASE 0x38
#define CHECK_POWER_MODE 0xE5
#define DEVICE_RESET 0x08
#define DOWNLOAD_MICROCODE 0x92
#define EXECUTE_DEVICE_DIAGNOSTIC 0x90
#define FLUSH_CACHE 0xE7
#define GET_MEDIA_STATUS 0xDA
#define IDENTIFY_DEVICE 0xEC
#define IDENTIFY_PACKET_DEVICE 0xA1
#define IDLE 0xE3
#define IDLE_IMMEDIATE 0xE1
#define INITIALIZE_DEVICE_PARAMETERS 0x91
#define MEDIA_EJECT 0xED
#define MEDIA_LOCK 0xDE
#define MEDIA_UNLOCK 0xDF
#define NOP 0x00
#define PACKET 0xA0
#define READ_BUFFER 0xE4
#define READ_DMA 0xC8
#define READ_DMA_QUEUED 0xC7
#define READ_MULTIPLE 0xC4
#define READ_NATIVE_MAX_ADDRESS 0xF8
#define READ_SECTOR 0x20
#define READ_SECTORS 0x20
#define READ_VERIFY_SECTOR 0x40
#define READ_VERIFY_SECTORS 0x40
#define SECURITY_DISABLE_PASSWORD 0xF6
#define SECURITY_ERASE_PREPARE 0xF3
#define SECURITY_ERASE_UNIT 0xF4
#define SECURITY_FREEZE_LOCK 0xF5
#define SECURITY_SET_PASSWORD 0xF1
#define SECURITY_UNLOCK 0xF2
#define SEEK 0x70
#define SERVICE 0xA2
#define SET_FEATURES 0xEF
#define SET_MAX 0xF9
#define SET_MULTIPLE_MODE 0xC6
#define SLEEP 0xE6
#define SMART 0xB0
#define STANDBY 0xE2
#define STANDBY_IMMEDIATE 0xE0
#define WRITE_BUFFER 0xE8
#define WRITE_DMA 0xCA
#define WRITE_DMA_QUEUED 0xCC
#define WRITE_MULTIPLE 0xC5
#define WRITE_SECTOR 0x30
#define WRITE_SECTORS 0x30
 
 
/* SET_FEATURES has a number of sub-commands (in Features Register) */
#define CFA_ENABLE_8BIT_PIO_TRANSFER_MODE 0x01
#define ENABLE_WRITE_CACHE 0x02
#define SET_TRANSFER_MODE_SECTOR_COUNT_REG 0x03
#define ENABLE_ADVANCED_POWER_MANAGEMENT 0x05
#define ENABLE_POWERUP_IN_STANDBY_FEATURE_SET 0x06
#define POWERUP_IN_STANDBY_FEATURE_SET_SPINUP 0x07
#define CFA_ENABLE_POWER_MODE1 0x0A
#define DISABLE_MEDIA_STATUS_NOTIFICATION 0x31
#define DISABLE_READ_LOOKAHEAD 0x55
#define ENABLE_RELEASE_INTERRUPT 0x5D
#define ENABLE_SERVICE_INTERRUPT 0x5E
#define DISABLE_REVERTING_TO_POWERON_DEFAULTS 0x66
#define CFA_DISABLE_8BIT_PIO_TRANSFER_MODE 0x81
#define DISABLE_WRITE_CACHE 0x82
#define DISABLE_ADVANCED_POWER_MANAGEMENT 0x85
#define DISABLE_POWERUP_IN_STANDBY_FEATURE_SET 0x86
#define CFA_DISABLE_POWER_MODE1 0x8A
#define ENABLE_MEDIA_STATUS_NOTIFICATION 0x95
#define ENABLE_READ_LOOKAHEAD_FEATURE 0xAA
#define ENABLE_REVERTING_TO_POWERON_DEFAULTS 0xCC
#define DISABLE_RELEASE_INTERRUPT 0xDD
#define DISABLE_SERVICE_INTERRUPT 0xDE
 
/* SET_MAX has a number of sub-commands (in Features Register) */
#define SET_MAX_ADDRESS 0x00
#define SET_MAX_SET_PASSWORD 0x01
#define SET_MAX_LOCK 0x02
#define SET_MAX_UNLOCK 0x03
#define SET_MAX_FREEZE_LOCK 0x04
 
/* SET_MAX has a number of sub-commands (in Features Register) */
#define SMART_READ_DATA 0xD0
#define SMART_ATTRIBITE_AUTOSAVE 0xD1
#define SMART_SAVE_ATTRIBUTE_VALUES 0xD3
#define SMART_EXECUTE_OFFLINE_IMMEDIATE 0xD4
#define SMART_READ_LOG 0xD5
#define SMART_WRITE_LOG 0xD6
#define SMART_ENABLE_OPERATIONS 0xD8
#define SMART_DISABLE_OPERATIONS 0xD9
#define SMART_RETURN_STATUS 0xDA
 
/* ---------------------------- */
/* ----- Structs ----- */
/* ---------------------------- */
 
/* ---------------------------- */
/* ----- Macros ----- */
/* ---------------------------- */
 
#define ata_astatus(base) (REG32(base + ATA_ASR))
#define ata_status(base) (REG32(base + ATA_SR))
#define ata_error(base) (REG32(base + ATA_ERR))
 
#define ata_dev_busy(base) (ata_astatus(base) & ATA_SR_BSY)
#define ata_dev_cmdrdy(base) (ata_astatus(base) & (~ATA_SR_BSY & ATA_SR_DRDY))
#define ata_dev_datrdy(base) (ata_astatus(base) & ATA_SR_DRQ)
 
/* ---------------------------- */
/* ----- Prototypes ----- */
/* ---------------------------- */
void module_ata_init (void);
int atabug(int argc, char **argv);
int atabug_exit(int argc, char **argv);
int atabug_help(int argc, char **argv);
void register_ata_command (const char *name, const char *params, const char *help, int (*func)(int argc, char *argv[]));
int ata_mon_command(void);
int execute_ata_command(char *pstr, int argc, char **argv);
 
int ata_dump_device_regs_cmd(int argc, char **argv);
int ata_dump_host_regs_cmd(int argc, char **argv);
int ata_enable_cmd(int argc, char **argv);
int ata_exec_cmd_cmd(int argc, char **argv);
int ata_identify_device_cmd(int argc, char **argv);
int ata_read_sector_cmd(int argc, char **argv);
int ata_reset_cmd(int argc, char **argv);
int ata_select_device_cmd(int argc, char **argv);
 
unsigned char atabug_dump_data(unsigned short *buffer, int cnt);
 
 
#endif
trunk/orpmon/include/ata.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/orpmon/include/board.h =================================================================== --- trunk/orpmon/include/board.h (revision 877) +++ trunk/orpmon/include/board.h (revision 878) @@ -12,14 +12,14 @@ #define DC_ENABLE 0 #define DC_SIZE 8192 -#define MC_CSR_VAL 0x0B000300 -#define MC_MASK_VAL 0x000000e0 -#define FLASH_BASE_ADDR 0x04000000 -#define FLASH_SIZE 0x02000000 +#define MC_CSR_VAL 0x0B000300 +#define MC_MASK_VAL 0x000000e0 +#define FLASH_BASE_ADDR 0x04000000 +#define FLASH_SIZE 0x02000000 #define FLASH_BLOCK_SIZE 0x20000 -#define FLASH_TMS_VAL 0x00102102 -#define SDRAM_BASE_ADDR 0x00000000 -#define SDRAM_TMS_VAL 0x07248230 +#define FLASH_TMS_VAL 0x00102102 +#define SDRAM_BASE_ADDR 0x00000000 +#define SDRAM_TMS_VAL 0x07248230 #ifdef XESS #define IN_CLK 10000000 @@ -66,14 +66,16 @@ #define ETH_MACADDR5 0x9a #define CRT_ENABLED 1 -#define CRT_BASE_ADDR 0xc0000000 -#define FB_BASE_ADDR 0xa8000000 +#define CRT_BASE_ADDR 0xc0000000 +#define FB_BASE_ADDR 0xa8000000 +#define ATA_BASE_ADDR 0xc8000000 + /* Whether online help is available -- saves space */ #define HELP_ENABLED 1 /* Whether self check is enabled */ -#define SELF_CHECK 1 +#define SELF_CHECK 0 /* Whether we have keyboard suppport */ #define KBD_ENABLED 1
/trunk/orpmon/include/common.h
46,6 → 46,16
unsigned long erase_method; /* 0 = do not erase, 1 = fully, 2 = as needed */
} global_struct;
 
 
/* structure for command interpreter */
typedef struct {
const char *name;
const char *params;
const char *help;
int (*func)(int argc, char *argv[]);
} command_struct;
 
 
extern bd_t bd;
extern global_struct global;
 
83,5 → 93,6
/* For reading SPR. */
extern unsigned long mfspr(unsigned long spr);
 
 
#endif /* _COMMON_H_ */
 
/trunk/orpmon/cmds/ata.c
0,0 → 1,512
/*
atadbg.c -- ATA debugging
Copyright (C) 2002 Richard Herveille, rherveille@opencores.org
 
This file is part of OpenRISC 1000 Reference Platform Monitor (ORPmon)
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
 
 
#include "support.h"
#include "common.h"
#include "ata.h"
 
#include <ctype.h>
 
int ata_num_commands;
command_struct ata_command[MAX_ATA_COMMANDS];
 
/* buffer for ata-data */
short buf[256];
 
 
/**********************************************************************/
/* */
/* A T A B U G */
/* */
/**********************************************************************/
/*
A T A _ I N I T
 
initializes the ATA core, and registers it with ORPmon
*/
void module_ata_init (void)
{
ata_num_commands = 0;
 
register_command ("atabug", "", "ATA debugger. Type 'atabug help' for help", atabug);
 
register_ata_command ("help", "", "Display this help message", atabug_help);
register_ata_command ("exit", "", "Exit atabug and return to ORPmon", atabug_exit);
register_ata_command ("reset", "[<mode>]", "Reset ata device(s). Mode: 0=hw_reset, 1=sw_reset, 2=device_reset", ata_reset_cmd);
register_ata_command ("enable", "[<mode>]", "Clear ata reset bits. Mode: 0=hw_reset, 1=sw_reset", ata_enable_cmd);
register_ata_command ("dump_device_regs", "", "Dump the (readable) ata device registers.", ata_dump_device_regs_cmd);
register_ata_command ("dump_host_regs", "", "Dump the ata host registers.", ata_dump_host_regs_cmd);
register_ata_command ("exec_cmd", "[<cmd>]", "Execute ata command <cmd> (hex)", ata_exec_cmd_cmd);
register_ata_command ("select_device", "[<device_no>]", "Select ata device. device_no=<0|1>", ata_select_device_cmd);
register_ata_command ("identify_device", "", "Read device ID", ata_identify_device_cmd);
register_ata_command ("read_sector", "[<sectorno>]", "Reads sector <sectorno>(dec)from the selected device (LBA mode)", ata_read_sector_cmd);
}
 
 
int atabug(int argc, char **argv)
{
 
/* take care of commandline options */
if (argc == 0)
{
/* start atabug */
while ( !ata_mon_command() );
}
else
return execute_ata_command(argv[0], argc -1, &argv[1]);
 
return 0;
}
 
int atabug_exit(int argc, char **argv)
{
return -2;
}
 
/*
The next code is graceously taken from the "common.c" file
and slightly modified to suit the big list of ATA commands
 
Better would be if we could access the routines in 'common.c'
directly, using our own set of commands.
*/
 
/* Process command-line, generate arguments */
int ata_mon_command(void)
{
char c = '\0';
char str[1000];
char *pstr = str;
char *command_str;
char *argv[20];
int argc = 0;
 
 
/* Show prompt */
printf ("\natabug> ");
 
 
/* Get characters from UART */
c = getc();
while (c != '\r' && c != '\f' && c != '\n')
{
if (c == '\b')
pstr--;
else
*pstr++ = c;
putc(c);
c = getc();
}
*pstr = '\0';
printf ("\n");
 
/* Skip leading blanks */
pstr = str;
while ( isspace(*pstr) ) pstr++;
 
/* Get command from the string */
command_str = pstr;
 
while (1) {
/* Go to next argument */
while ( isgraph(*pstr) ) pstr++;
if (*pstr) {
*pstr++ = '\0';
while ( isspace(*pstr) ) pstr++;
argv[argc++] = pstr;
}
else
break;
}
 
return execute_ata_command(command_str, argc, argv);
}
 
 
int execute_ata_command(char *command_str, int argc, char **argv)
{
int i, found = 0;
 
for (i = 0; i < ata_num_commands; i++)
if ( !strcmp(command_str, ata_command[i].name) )
{
switch ( ata_command[i].func(argc, argv) )
{
case -1:
printf ("Missing/wrong parameters, usage: %s %s\n", ata_command[i].name, ata_command[i].params);
break;
 
case -2:
return -1;
}
 
found++;
break;
}
if (!found)
printf ("Unknown command. Type 'ata help' for help.\n");
 
return 0;
}
 
 
void register_ata_command (const char *name, const char *params, const char *help, int (*func)(int argc, char *argv[]) )
{
if (ata_num_commands < MAX_ATA_COMMANDS)
{
ata_command[ata_num_commands].name = name;
ata_command[ata_num_commands].params = params;
ata_command[ata_num_commands].help = help;
ata_command[ata_num_commands].func = func;
ata_num_commands++;
}
else
printf ("ata-command '%s' ignored; MAX_COMMANDS limit reached\n", name);
}
 
int atabug_help(int argc, char **argv)
{
int i;
 
for (i = 0; i < ata_num_commands; i++)
printf ("%-20s %-15s -%s\n", ata_command[i].name, ata_command[i].params, ata_command[i].help);
return 0;
}
 
 
 
 
/**********************************************************************/
/* */
/* A T A B U G C O M M A N D S E T */
/* */
/**********************************************************************/
 
/*
A T A _ D U M P _ D E V I C E _ R E G S
 
Dumps the (readable) ata-registers.
Exception: status register is not read, this could mask an interrupt
*/
int ata_dump_device_regs_cmd(int argc, char **argv)
{
if (argc)
printf("\nWARNING: Ignoring invalid argument(s)\n\n");
 
 
printf("Alternate status register : 0x%02lX\n", REG32(ATA_BASE_ADDR + ATA_ASR) );
printf("Cylinder high register : 0x%02lX\n", REG32(ATA_BASE_ADDR + ATA_CHR) );
printf("Cylinder low register : 0x%02lX\n", REG32(ATA_BASE_ADDR + ATA_CLR) );
printf("Device head register : 0x%02lX\n", REG32(ATA_BASE_ADDR + ATA_DHR) );
printf("Error register : 0x%02lX\n", REG32(ATA_BASE_ADDR + ATA_ERR) );
printf("Sector count register : 0x%02lX\n", REG32(ATA_BASE_ADDR + ATA_SCR) );
printf("Sector number register : 0x%02lX\n", REG32(ATA_BASE_ADDR + ATA_SNR) );
printf("Status register (see alternate status register)\n" );
 
return 0;
}
 
 
/*
A T A _ D U M P _ H O S T _ R E G S
 
Dumps the ata-host registers
*/
int ata_dump_host_regs_cmd(int argc, char **argv)
{
if (argc)
printf("\nWARNING: Ignoring invalid argument(s)\n\n");
 
 
printf("Control register CTRL : 0x%08lX\n", REG32(ATA_BASE_ADDR + ATA_CTRL) );
printf("Status register STAT : 0x%08lX\n", REG32(ATA_BASE_ADDR + ATA_STAT) );
printf("Pio command timing register PCTR : 0x%08lX\n", REG32(ATA_BASE_ADDR + ATA_PCTR) );
printf("Pio fast timing register (device0) PFTR0: 0x%08lX\n", REG32(ATA_BASE_ADDR + ATA_PFTR0) );
printf("Pio fast timing register (device1) PFTR1: 0x%08lX\n", REG32(ATA_BASE_ADDR + ATA_PFTR0) );
printf("Dma timing register (device0) DTR0 : 0x%08lX\n", REG32(ATA_BASE_ADDR + ATA_DTR0) );
printf("Dma timing register (device1) DTR1 : 0x%08lX\n", REG32(ATA_BASE_ADDR + ATA_DTR1) );
 
return 0;
}
 
 
/*
A T A _ E N A B L E
 
clears reset bits
*/
int ata_enable_cmd(int argc, char **argv)
{
if (argc != 1)
return -1;
 
switch (**argv)
{
case '0': /* ata hardware reset */
REG32(ATA_BASE_ADDR + ATA_CTRL) &= ~ATA_RST;
return 0;
 
case '1': /* ata software reset */
REG32(ATA_BASE_ADDR + ATA_DCR) &= ~ATA_DCR_RST;
return 0;
 
default:
return -1;
}
}
 
 
/*
A T A _ E X E C _ C M D
 
Executes the command; writes the command number in the command register
*/
int ata_exec_cmd_cmd(int argc, char **argv)
{
if (argc != 1)
return -1;
 
REG32(ATA_BASE_ADDR + ATA_CR) = strtoul(*argv, argv, 16);
return 0;
}
 
 
/*
A T A _ I D E N T I F Y _ D E V I C E
 
Reads the identify_device block and dumps it to the screen
*/
int ata_identify_device_cmd(int argc, char **argv)
{
int i;
unsigned short *buf_ptr;
unsigned char checksum;
 
if (argc != 0)
printf("Ignoring invalid parameters\n");
 
 
/* check for busy flag */
if ( ata_dev_busy(ATA_BASE_ADDR) )
printf("Selected ata device busy, ignoring command\n");
else
{
/* send 'identify_device' command */
REG32(ATA_BASE_ADDR + ATA_CR) = IDENTIFY_DEVICE;
 
/* read data from devices and store it in local buffer */
buf_ptr = buf;
for (i=0; i < 256; i++)
*buf_ptr++ = REG32(ATA_BASE_ADDR + ATA_DR);
 
/* dump data to the screen */
checksum = atabug_dump_data(buf, 256);
 
printf("Checksum = 0x%2X (%s)\n", checksum, checksum ? "error" : "OK");
}
return 0;
}
 
 
/*
A T A _ R E A D _ S E C T O R
 
Reads 1 sector from the device and dumps it to the screen
*/
int ata_read_sector_cmd(int argc, char **argv)
{
int i;
unsigned short *buf_ptr;
unsigned long lba;
short tmp;
 
if (argc != 1)
return -1;
 
 
/* check for busy flag */
if ( ata_dev_busy(ATA_BASE_ADDR) )
printf("Selected ata device busy, ignoring command\n");
else
{
/* get the LBA (Large Block Address) */
lba = strtoul(*argv, argv, 10);
 
/* program ata-device registers */
REG32(ATA_BASE_ADDR + ATA_DHR) = ((lba >> 24) & ATA_DHR_H) | ATA_DHR_LBA;
REG32(ATA_BASE_ADDR + ATA_CHR) = (lba >> 16) & 0xff;
REG32(ATA_BASE_ADDR + ATA_CLR) = (lba >> 8) & 0xff;
REG32(ATA_BASE_ADDR + ATA_SNR) = lba & 0xff;
 
REG32(ATA_BASE_ADDR + ATA_SCR) = 1; /* read 1 sector */
 
/* send 'read_sector(s)' command */
REG32(ATA_BASE_ADDR + ATA_CR) = READ_SECTORS;
 
/* check status & error registers */
if ( ata_astatus(ATA_BASE_ADDR) & ATA_SR_ERR)
{
printf("Error while executing READ_SECTOR(S) command\n");
printf("Status register = 0x%02lX, error register = 0x%02lX\n", \
ata_astatus(ATA_BASE_ADDR), ata_error(ATA_BASE_ADDR) );
}
else
{
/* read data from devices and store it in local buffer */
buf_ptr = buf;
for (i=0; i < 256; i++)
*buf_ptr++ = REG32(ATA_BASE_ADDR + ATA_DR);
 
/* the data is byte reversed, switch upper & lower bytes */
buf_ptr = buf;
for (i=0; i < 256; i++)
{
tmp = *buf_ptr;
*buf_ptr++ = (tmp << 8) | (tmp >> 8);
}
 
/* dump data to the screen */
atabug_dump_data(buf, 256);
}
}
return 0;
}
 
 
/*
A T A _ R E S E T
 
resets the ATA device, using the select method
*/
int ata_reset_cmd(int argc, char **argv)
{
if (argc != 1)
return -1;
 
switch (**argv)
{
case '0': /* ata hardware reset */
REG32(ATA_BASE_ADDR + ATA_CTRL) |= ATA_RST;
return 0;
 
case '1': /* ata software reset */
REG32(ATA_BASE_ADDR + ATA_DCR) |= ATA_DCR_RST;
return 0;
 
case '2': /* ata device reset (send DEVICE_RESET command) */
REG32(ATA_BASE_ADDR + ATA_CR) = DEVICE_RESET;
return 0;
 
default:
return -1;
}
}
 
 
/*
A T A _ S E L E C T _ D E V I C E
 
selects the ATA device; sets the DEV bit in the device/head register
*/
int ata_select_device_cmd(int argc, char **argv)
{
if (argc != 1)
return -1;
 
switch (**argv)
{
case '0':
REG32(ATA_BASE_ADDR + ATA_DHR) &= ~ATA_DHR_DEV;
break;
 
case '1':
REG32(ATA_BASE_ADDR + ATA_DHR) |= ATA_DHR_DEV;
break;
 
default:
return -1;
}
 
printf("Ata device %1d selected.\n", REG32(ATA_BASE_ADDR + ATA_DHR) & ATA_DHR_DEV ? 1 : 0);
return 0;
}
 
 
/**********************************************************************/
/* */
/* A T A B U G T O O L S */
/* */
/**********************************************************************/
 
/*
D U M P _ D A T A
 
dumps byte-data in a buffer of type short to the screen
and returns the byte-checksum
*buffer = pointer to (short)buffer
cnt = number of words to display
*/
unsigned char atabug_dump_data(unsigned short *buffer, int cnt)
{
int i, n, words_per_line = 8;
unsigned char c, checksum;
unsigned short *buf_ptr;
 
/* prepare stored data for display & calculate checksum */
checksum = 0;
buf_ptr = buffer;
 
/* display data */
for (i=0; i < cnt; i += words_per_line)
{
printf("%2X ", i);
 
/* print hexadecimal notation */
for (n=0; n < words_per_line; n++)
printf("%04X ", *buf_ptr++);
 
buf_ptr -= words_per_line; /* back to the start (of this block) */
 
/* print ASCII notation & calculate checksum */
for (n=0; n < words_per_line; n++)
{
/* first character, stored in upper byte */
c = (*buf_ptr >> 8) & 0xff;
printf(" %c", isprint(c) ? c : '.');
checksum += c;
 
/* second character, stored in lower byte */
c = *buf_ptr & 0xff;
printf(" %c", isprint(c) ? c : '.');
checksum += c;
 
buf_ptr++;
}
printf("\n");
}
 
return checksum;
}
 
/trunk/orpmon/cmds/Makefile
1,6 → 1,6
 
LIB = cmds.o
OBJS = dhry.o eth.o cpu.o camera.o load.o memory.o global.o touch.o
OBJS = dhry.o eth.o cpu.o camera.o load.o memory.o global.o touch.o ata.o
 
all: $(LIB)
 
/trunk/orpmon/sim.cfg
1,9 → 1,9
/* sim.cfg -- Simulator configuration script file
Copyright (C) 2001, Marko Mlinar, markom@opencores.org
 
This file includes a lot of help about configurations and default one
 
This file is part of OpenRISC 1000 Architectural Simulator.
It contains the default configuration and help about configuring
the simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
22,25 → 22,27
 
/* INTRODUCTION
 
The or1ksim have various parameters, which can be set in configuration
files. Multiple configurations may be used and switched between at
or1ksim startup.
By default, or1ksim loads condfiguration file from './sim.cfg' and if not
found it checks '~/.or1k/sim.cfg'. If even this file is not found or
all parameters are not defined, default configuration is used.
Users should not rely on default configuration, but rather redefine all
critical settings, since default configuration may differ in newer
versions of the or1ksim.
If multiple configurations are used, user can switch between them by
supplying -f <filename.cfg> option when starting simulator.
The ork1sim has various parameters, that are set in configuration files
like this one. The user can switch between configurations at startup by
specifying the required configuration file with the -f <filename.cfg> option.
If no configuration file is specified or1ksim searches for the default
configuration file sim.cfg. First it searches for './sim.cfg'. If this
file is not found, it searches for '~/or1k/sim.cfg'. If this file is
not found too, it reverts to the built-in default configuration.
NOTE: Users should not rely on the built-in configuration, since the
default configuration may differ between version.
Rather create a configuration file that sets all critical values.
 
This file may contain (standard C) only comments - no // support.
This file may contain (standard C) comments only - no // support.
Configure files may be be included, using:
include "file_name_to_include"
 
Like normal configuration file, this file is divided in sections,
where each section is described in detail also.
Like normal configuration files, the included file is divided into
sections. Each section is described in detail also.
 
Some section also have subsections. One example of such subsection is
block:
Some section have subsections. One example of such a subsection is:
 
device <index>
instance specific parameters...
52,20 → 54,22
 
/* MEMORY SECTION
 
This section specifies how is initial memory generated and which blocks
it consist of.
This section specifies how the memory is generated and the blocks
it consists of.
 
type = random/unknown/pattern
specifies the initial memory values. 'random' parameter generate
random memory using seed 'random_seed' parameter. 'pattern' parameter
fills memory with 'pattern' parameter and 'unknown' does not specify
how memory should be generated - the fastest option.
Specifies the initial memory values.
'random' generates random memory using seed 'random_seed'.
'pattern' fills memory with 'pattern'.
'unknown' does not specify how memory should be generated,
leaving the memory in a undefined state. This is the fastest
option.
 
random_seed = <value>
random seed for randomizer, used if type = random
random seed for randomizer, used if type = 'random'.
 
pattern = <value>
pattern to fill memory, used if type = pattern
pattern to fill memory, used if type = 'pattern'.
 
nmemories = <value>
number of memory instances connected
89,13 → 93,11
delayw = <value>
cycles, required for write access, -1 if instance does not support writing
 
16550 = 0/1
0, if this device is uart 16450 and 1, if it is 16550
 
log = "<filename>"
filename, where to log memory accesses to, no log, if log command is not specified
*/
 
 
section memory
/*random_seed = 12345
type = random*/
102,6 → 104,7
pattern = 0x00
type = unknown /* Fastest */
 
 
nmemories = 3
device 0
name = "FLASH"
110,7 → 113,6
size = 0x00800000
delayr = 10
delayw = -1
/* log = "flash.log"*/
enddevice
 
device 1
120,8 → 122,8
size = 0x00400000
delayr = 1
delayw = 2
/* log = "ram.log"*/
enddevice
 
device 2
name = "SRAM"
ce = 2
129,16 → 131,17
size = 0x00400000
delayr = 1
delayw = 2
/* log = "ram.log"*/
enddevice
end
 
 
/* IMMU SECTION
 
This section configures Instruction Memory Menangement Unit
This section configures the Instruction Memory Manangement Unit
 
enabled = 0/1
whether IMMU is enabled
'0': disabled
'1': enabled
(NOTE: UPR bit is set)
 
nsets = <value>
155,6 → 158,12
 
ustates = <value>
number of ITLB usage states (2, 3, 4 etc., max is 4)
hitdelay = <value>
number of cycles immu hit costs
missdelay = <value>
number of cycles immu miss costs
*/
 
section immu
162,14 → 171,18
nsets = 64
nways = 1
pagesize = 8192
hitdelay = 0
missdelay = 0
end
 
 
/* DMMU SECTION
 
This section configures Data Memory Menangement Unit
This section configures the Data Memory Manangement Unit
 
enabled = 0/1
whether DMMU is enabled
'0': disabled
'1': enabled
(NOTE: UPR bit is set)
 
nsets = <value>
186,6 → 199,12
 
ustates = <value>
number of DTLB usage states (2, 3, 4 etc., max is 4)
 
hitdelay = <value>
number of cycles dmmu hit costs
 
missdelay = <value>
number of cycles dmmu miss costs
*/
 
section dmmu
193,28 → 212,37
nsets = 64
nways = 1
pagesize = 8192
hitdelay = 0
missdelay = 0
end
 
 
/* IC SECTION
 
This section configures Instruction Cache
This section configures the Instruction Cache
 
enabled = 0/1
whether IC is enabled
(NOTE: UPR bit is set)
enabled = 0/1
'0': disabled
'1': enabled
(NOTE: UPR bit is set)
 
nsets = <value>
number of IC sets; must be power of two
nsets = <value>
number of IC sets; must be power of two
 
nways = <value>
number of IC ways
nways = <value>
number of IC ways
 
blocksize = <value>
IC block size in bytes; must be power of two
blocksize = <value>
IC block size in bytes; must be power of two
 
ustates = <value>
number of IC usage states (2, 3, 4 etc., max is 4)
ustates = <value>
number of IC usage states (2, 3, 4 etc., max is 4)
 
hitdelay = <value>
number of cycles ic hit costs
missdelay = <value>
number of cycles ic miss costs
*/
 
section ic
222,27 → 250,43
nsets = 256
nways = 1
blocksize = 16
hitdelay = 0
missdelay = 0
end
 
 
/* DC SECTION
 
This section configures Data Cache
This section configures the Data Cache
 
enabled = 0/1
whether DC is enabled
(NOTE: UPR bit is set)
enabled = 0/1
'0': disabled
'1': enabled
(NOTE: UPR bit is set)
 
nsets = <value>
number of DC sets; must be power of two
nsets = <value>
number of DC sets; must be power of two
 
nways = <value>
number of DC ways
nways = <value>
number of DC ways
 
blocksize = <value>
DC block size in bytes; must be power of two
blocksize = <value>
DC block size in bytes; must be power of two
 
ustates = <value>
number of DC usage states (2, 3, 4 etc., max is 4)
ustates = <value>
number of DC usage states (2, 3, 4 etc., max is 4)
 
load_hitdelay = <value>
number of cycles dc load hit costs
load_missdelay = <value>
number of cycles dc load miss costs
store_hitdelay = <value>
number of cycles dc load hit costs
store_missdelay = <value>
number of cycles dc load miss costs
*/
 
section dc
250,41 → 294,80
nsets = 256
nways = 1
blocksize = 16
load_hitdelay = 0
load_missdelay = 0
store_hitdelay = 0
store_missdelay = 0
end
 
 
/* SIM SECTION
 
This section specifies how should sim behave.
This section specifies how or1ksim should behave.
 
verbose = 0/1
whether to print out extra messages
'0': don't print extra messages
'1': print extra messages
 
debug = 0-9
= 0 disabled debug messages
1-9 level of sim debug information, greater the number more verbose is
the output
0 : no debug messages
1-9: debug message level.
higher numbers produce more messages
 
profile = 0/1
whether to generate profiling file 'sim.profile'
'0': don't generate profiling file 'sim.profile'
'1': don't generate profiling file 'sim.profile'
 
prof_fn = "<filename>"
filename, where to generate profiling info, used
only if 'profile' is set
optional filename for the profiling file.
valid only if 'profile' is set
mprofile = 0/1
'0': don't generate memory profiling file 'sim.mprofile'
'1': generate memory profiling file 'sim.mprofile'
 
mprof_fn = "<filename>"
optional filename for the memory profiling file.
valid only if 'mprofile' is set
 
history = 0/1
whether instruction execution flow is tracked for
display by simulator hist command. Useful for
back-trace debugging.
'0': don't track execution flow
'1': track execution flow
Execution flow can be tracked for the simulator's
'hist' command. Useful for back-trace debugging.
 
iprompt = 0/1
whether we strart in interactive prompt
'0': start in <not interactive prompt> (so what do we start in ???)
'1': start in interactive prompt.
 
exe_log = 0/1
whether execution log should be generated
'0': don't generate execution log.
'1': generate execution log.
exe_log = default/hardware/simple/software
type of execution log, default is used when not specified
exe_log_start = <value>
index of first instruction to start logging, default = 0
exe_log_end = <value>
index of last instruction to end logging; not limited, if omitted
exe_log_marker = <value>
<value> specifies number of instructions before horizontal marker is
printed; if zero, markers are disabled (default)
 
exe_log_fn = "<filename>"
where to put execution log in, used only if 'exe_log'
is set
filename for the exection log file.
valid only if 'exe_log' is set
 
spr_log = 0/1
'0': log reads/writes to/from sprs
'1': don't log reads/write to/from sprs
 
spr_log_fn = "<filename>"
filename for the sprs log file.
valid only if 'spr_log' is set
clkcycle = <value>[ps|ns|us|ms]
specifies time measurement for one cycle
296,7 → 379,7
profile = 0
prof_fn = "sim.profile"
 
history = 0
history = 1
/* iprompt = 0 */
exe_log = 0
exe_log_type = software
304,25 → 387,37
/* exe_log_end = 20000000*/
exe_log_marker = 10000
exe_log_fn = "executed.log"
 
spr_log = 0
spr_log_fn = "spr.log"
clkcycle = 100ns
end
 
 
/* SECTION VAPI
 
This section configures Verification API, used for Advanced
This section configures the Verification API, used for Advanced
Core Verification.
 
enabled = 0/1
whether to start VAPI server
'0': disbable VAPI server
'1': enable/start VAPI server
 
server_port = <value>
TCP/IP port to start VAPI server on
 
log_enabled = 0/1
whether logging of VAPI requests is enabled
'0': disable VAPI requests logging
'1': enable VAPI requests logging
 
hide_device_id = 0/1
'0': don't log device id (for compatability with old version)
'1': log device id
 
vapi_fn = <filename>
specifies filename where to log into, if log_enabled is selected
filename for the log file.
valid only if log_enabled is set
*/
 
section VAPI
343,30 → 438,32
 
upr = <value>
changes the upr register
sr = <value>
sets the initial Supervision Register value
 
superscalar = 0/1
whether CPU is scalar or superscalar
'0': CPU is scalar
'1': CPU is superscalar
(modify cpu/or32/execute.c to tune superscalar model)
 
hazards = 0/1
whether data hazards are tracked in superscalar CPU
and displayed by the simulator r command
'0': don't track data hazards in superscalar CPU
'1': track data hazards in superscalar CPU
If tracked, data hazards can be displayed using the
simulator's 'r' command.
 
dependstats = 0/1
whether inter-instruction dependencies are calculated
and displayed by simulator stats command.
'0': don't calculate inter-instruction dependencies.
'1': calculate inter-instruction dependencies.
If calculated, inter-instruction dependencies can be
displayed using the simulator's 'stat' command.
 
slp = 0/1
calculation of subroutine level parallelism. Displayed
by simulator stats command.
 
btic = 0/1
enable branch target instruction cache model
 
bpb = 0/1
enable branch prediction buffer model
 
parameters for CPU analysis
raw_range = <value>
range in cycles for raw register over time analysis, 0 = disabled
sbuf_len = <value>
length of store buffer (<= 256), 0 = disabled
*/
 
section cpu
376,26 → 473,82
superscalar = 0
hazards = 0
dependstats = 0
slp = 0
end
 
 
/* PM SECTION
 
This section specifies Power Management parameters
 
enabled = 0/1
'0': disable power management
'1': enable power management
*/
 
section pm
enabled = 0
end
 
 
/* BPB SECTION
 
This section specifies how branch prediction should behave.
enabled = 0/1
'0': disable branch prediction
'1': enable branch prediction
btic = 0/1
'0': disable branch target instruction cache model
'1': enable branch target instruction cache model
 
sbp_bf_fwd = 0/1
Static branch prediction for 'l.bf'
'0': don't use forward prediction
'1': use forward prediction
sbp_bnf_fwd = 0/1
Static branch prediction for 'l.bnf'
'0': don't use forward prediction
'1': use forward prediction
 
hitdelay = <value>
number of cycles bpb hit costs
missdelay = <value>
number of cycles bpb miss costs
*/
 
section bpb
enabled = 0
btic = 0
bpb = 0
sbp_bf_fwd = 0
sbp_bnf_fwd = 0
hitdelay = 0
missdelay = 0
end
 
 
/* DEBUG SECTION
 
This sections specifies how debug unit should behave.
This sections specifies how the debug unit should behave.
 
enabled = 0/1
whether debug unit is enabled
'0': disable debug unit
'1': enable debug unit
 
gdb_enabled = 0/1
whether to start gdb server at 'server_port' port
'0': don't start gdb server
'1': start gdb server at port 'server_port'
 
server_port = <value>
TCP/IP port to start gdb server on, used only if gdb_enabled
is set
TCP/IP port to start gdb server on
valid only if gdb_enabled is set
 
vapi_id = <hex_value>
Used to create "fake" vapi log file containing the JTAG proxy messages.
*/
 
section debug
enabled = 0
gdb_enabled = 0
408,7 → 561,8
This section configures the memory controller
 
enabled = 0/1
whether memory controller is enabled
'0': disable memory controller
'1': enable memory controller
 
baseaddr = <hex_value>
address of first MC register
426,11 → 580,8
 
/* UART SECTION
 
This section configures UARTs
This section configures the UARTs
 
enabled = 0/1
whether uarts are enabled
 
nuarts = <value>
make specified number of instances, configure each
instance within device - enddevice construct.
439,10 → 590,10
baseaddr = <hex_value>
address of first UART register for this device
 
rx_file = "<filename>"
rxfile = "<filename>"
filename, where to read data from
 
tx_file = "<filename>"
txfile = "<filename>"
filename, where to write data to
 
irq = <value>
449,7 → 600,8
irq number for this device
 
16550 = 0/1
0, if this device is uart 16450 and 1, if it is 16550
'0': this device is a UART16450
'1': this device is a UART16550
 
jitter = <value>
in msecs... time to block, -1 to disable it
459,14 → 611,13
*/
 
section uart
enabled = 1
nuarts = 1
 
device 0
baseaddr = 0x90000000
irq = 19
rxfile = "uart0.rx"
txfile = "uart0.tx"
rxfile = "/tmp/uart0.rx"
txfile = "/tmp/uart0.tx"
jitter = -1 /* async behaviour */
16550 = 1
enddevice
475,11 → 626,8
 
/* DMA SECTION
 
This section configures DMAs
This section configures the DMAs
 
enabled = 0/1
whether DMAs are enabled
 
ndmas = <value>
make specified number of instances, configure each
instance within device - enddevice construct.
496,23 → 644,21
*/
 
section dma
enabled = 0
ndmas = 1
ndmas = 0
 
/*
device 0
baseaddr = 0xa0000000
irq = 4
enddevice
*/
end
 
 
/* ETHERNET SECTION
 
This section configures ethernets
This section configures the ETHERNETs
 
enabled = 0/1
whether ethernets are enabled
 
nethernets = <value>
make specified number of instances, configure each
instance within device - enddevice construct.
524,6 → 670,12
dma = <value>
which controller is this ethernet "connected" to
 
irq = <value>
ethernet mac IRQ level
 
rtx_type = <value>
use 0 - file interface, 1 - socket interface
 
rx_channel = <value>
DMA channel used for RX
 
530,12 → 682,15
tx_channel = <value>
DMA channel used for TX
 
rx_file = "<filename>"
rxfile = "<filename>"
filename, where to read data from
 
tx_file = "<filename>"
txfile = "<filename>"
filename, where to write data to
 
sockif = "<ifacename>"
interface name of ethernet socket
 
vapi_id = <hex_value>
VAPI id of this instance
*/
556,6 → 711,70
enddevice
end
 
 
/* GPIO SECTION
 
This section configures the GPIOs
 
ngpios = <value>
make specified number of instances, configure each
instance within device - enddevice construct.
 
instance specific:
baseaddr = <hex_value>
address of first GPIO register for this device
 
irq = <value>
irq number for this device
 
base_vapi_id = <hex_value>
first VAPI id of this instance
GPIO uses 8 consecutive VAPI IDs
*/
 
section gpio
ngpios = 1
 
device 0
baseaddr = 0xA1000000
irq = 23
base_vapi_id = 0x0200
enddevice
end
 
/* VGA SECTION
This section configures the VGA/LCD controller
nvgas = <value>
number of VGA devices connected
instance specific:
baseaddr = <hex_value>
address of first VGA register
irq = <value>
irq number for this device
refresh_rate = <value>
number of cycles between screen dumps
filename = "<filename>"
template name for generated names (e.g. "primary" produces "primary0023.bmp")
*/
 
section vga
nvgas = 1
device 0
baseaddr = 0xb0000000
irq = 20
refresh_rate = 100000
filename = "primary"
enddevice
end
 
 
/* TICK TIMER SECTION
 
This section configures tick timer
566,12 → 785,33
irq = <value>
irq number
*/
 
/*
section tick
enabled = 1
irq = 0
end
*/
 
/* FB SECTION
This section configures the frame buffer
enabled = 0/1
whether frame buffer is enabled
baseaddr = <hex_value>
base address of frame buffer
paladdr = <hex_value>
base address of first palette entry
refresh_rate = <value>
number of cycles between screen dumps
filename = "<filename>"
template name for generated names (e.g. "primary" produces "primary0023.bmp")
*/
 
section fb
enabled = 1
baseaddr = 0xc0000000
579,16 → 819,17
filename = "primary"
end
 
 
/* KBD SECTION
 
This section configures PS/2 compatible keyboard
 
This section configures the PS/2 compatible keyboard
enabled = 0/1
whether keyboard is enabled
 
baseaddr = <hex_value>
base address of the keyboard device
 
rxfile = "<filename>"
filename, where to read data from
*/
600,3 → 841,66
rxfile = "kbd.rx"
end
 
 
/* ATA SECTION
This section configures the ATA/ATAPI host controller
natas = <value>
number of ATA hosts connected
instance specific:
baseaddr = <hex_value>
address of first ATA register
irq = <value>
irq number for this device
 
debug = <value>
debug level for ata models.
0: no debug messages
1: verbose messages
3: normal messages (more messages than verbose)
5: debug messages (normal debug messages)
7: flow control messages (debug statemachine flows)
9: low priority message (display everything the code does)
 
dev_type0/1 = <value>
ata device 0 type
0: NO_CONNeCT: none (not connected)
1: FILE : simulated harddisk
2: LOCAL : local system harddisk
 
dev_file0/1 = "<filename>"
filename for simulated ATA device
valid only if dev_type0 == 1
 
dev_size0/1 = <value>
size of simulated hard-disk (in MBytes)
valid only if dev_type0 == 1
 
dev_packet0/1 = <value>
0: simulated ATA device does NOT implement PACKET command feature set
1: simulated ATA device does implement PACKET command feature set
 
FIXME: irq number
*/
 
section ata
natas = 1
 
device 0
baseaddr = 0xc8000000
irq = 21
 
dev_type0 = 1
dev_file0 = "/tmp/sim_atadev0"
dev_size0 = 1
dev_packet0 = 0
 
dev_type1 = 0
dev_file1 = ""
dev_size1 = 0
dev_packet1 = 0
enddevice
end
/trunk/orpmon/common/ctype.c
0,0 → 1,55
/*
ctype.c -- character types
Implements the usual ctype stuff (only valid for ASCII systems)
Copyright (C) 2002 Richard Herveille, rherveille@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
 
#include <ctype.h>
 
const unsigned char __ctype_table[256] =
{
/* only the first 128 characters are really defined 0 1 2 3 4 5 6 7 */
0, __CT_c, __CT_c, __CT_c, __CT_c, __CT_c, __CT_c, __CT_c, /*0 NUL SOH STX ETX EOT ENQ ACK BEL */
__CT_c, __CT_b, __CT_s, __CT_b, __CT_s, __CT_s, __CT_c, __CT_c, /*1 BS HT LF VT FF CR SO SI */
__CT_c, __CT_c, __CT_c, __CT_c, __CT_c, __CT_c, __CT_c, __CT_c, /*2 DLE DC1 DC2 DC3 DC4 NAK SYN ETB */
__CT_c, __CT_c, __CT_c, __CT_c, __CT_c, __CT_c, __CT_c, __CT_c, /*3 CAN EM SUB ESC FS GS RS US */
__CT_b, __CT_p, __CT_p, __CT_p, __CT_p, __CT_p, __CT_p, __CT_p, /*4 SP ! " # $ % & ' */
__CT_p, __CT_p, __CT_p, __CT_p, __CT_p, __CT_p, __CT_p, __CT_p, /*5 ( ) * + , - . / */
__CT_d, __CT_d, __CT_d, __CT_d, __CT_d, __CT_d, __CT_d, __CT_d, /*6 0 1 2 3 4 5 6 7 */
__CT_d, __CT_d, __CT_p, __CT_p, __CT_p, __CT_p, __CT_p, __CT_p, /*7 8 9 : ; < = > ? */
__CT_p, __CT_ux, __CT_ux, __CT_ux, __CT_ux, __CT_ux, __CT_ux, __CT_u, /*8 @ A B C D E F G */
__CT_u, __CT_u, __CT_u, __CT_u, __CT_u, __CT_u, __CT_u, __CT_u, /*9 H I J K L M N O */
__CT_u, __CT_u, __CT_u, __CT_u, __CT_u, __CT_u, __CT_u, __CT_u, /*a P Q R S T U V W */
__CT_u, __CT_u, __CT_u, __CT_p, __CT_p, __CT_p, __CT_p, __CT_p, /*b X Y Z [ \ ] ^ _ */
__CT_p, __CT_lx, __CT_lx, __CT_lx, __CT_lx, __CT_lx, __CT_lx, __CT_l, /*c ` a b c d e f g */
__CT_l, __CT_l, __CT_l, __CT_l, __CT_l, __CT_l, __CT_l, __CT_l, /*d h i j k l m n o */
__CT_l, __CT_l, __CT_l, __CT_l, __CT_l, __CT_l, __CT_l, __CT_l, /*e p q r s t u v w */
__CT_l, __CT_l, __CT_l, __CT_p, __CT_p, __CT_p, __CT_p, __CT_c, /*f x y z { | } ~ DEL */
 
/* The other 128 characters are system dependant */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
/trunk/orpmon/common/common.c
14,13 → 14,10
 
int num_commands = 0;
 
struct command_struct {
const char *name;
const char *params;
const char *help;
int (*func)(int argc, char *argv[]);
} command[MAX_COMMANDS];
command_struct command[MAX_COMMANDS];
 
 
 
void putc (const char c)
{
debug ("putc %i, %i = %c\n", bd.bi_console_type, c, c);
161,7 → 158,7
#else
printf ("\nbender> ");
#endif
 
/* Get characters from UART */
c = getc();
while (c != '\r' && c != '\f' && c != '\n')
179,10 → 176,10
/* Skip leading blanks */
pstr = str;
while (*pstr == ' ' && *pstr != '\0') pstr++;
 
/* Get command from the string */
command_str = pstr;
 
while (1) {
/* Go to next argument */
while (*pstr != ' ' && *pstr != '\0') pstr++;
191,24 → 188,31
while (*pstr == ' ') pstr++;
argv[argc++] = pstr;
}
else
else
break;
}
 
{
int i, found = 0;
 
for (i = 0; i < num_commands; i++)
if (strcmp (command_str, command[i].name) == 0) {
switch (command[i].func (argc, &argv[0])) {
case -1:
printf ("Missing/wrong parameters, usage: %s %s\n", command[i].name, command[i].params);
break;
if (strcmp (command_str, command[i].name) == 0)
{
switch ( command[i].func(argc, &argv[0]) )
{
case -1:
printf ("Missing/wrong parameters, usage: %s %s\n", command[i].name, command[i].params);
break;
}
found = 1;
 
found++;
break;
}
if (!found) printf ("Unknown command. Type 'help' for help.\n");
if (!found)
printf ("Unknown command. Type 'help' for help.\n");
}
 
}
 
#if HELP_ENABLED
230,6 → 234,7
void module_load_init (void);
void tick_init(void);
void module_touch_init (void);
void module_ata_init (void);
 
/* List of all initializations */
void mon_init (void)
256,6 → 261,7
module_camera_init ();
module_load_init ();
module_touch_init ();
module_ata_init ();
 
tick_init();
}
268,18 → 274,21
#if 1
extern unsigned long mycrc32, mysize;
#endif
int_init ();
change_console_type (CONSOLE_TYPE);
mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
 
#if SELF_CHECK
printf ("Self check... ");
if ((t = calc_mycrc32 ())) printf ("FAILED!!!\n");
else printf ("OK\n");
if ((t = calc_mycrc32 ()))
printf ("FAILED!!!\n");
else
printf ("OK\n");
#endif /* SELF_CHECK */
 
mon_init ();
 
if (HELP_ENABLED) register_command ("help", "", "shows this help", help_cmd);
 
#ifdef XESS
/trunk/orpmon/common/Makefile
3,7 → 3,7
 
LIB = common_o.o
 
OBJS = common.o support.o cprintf.o screen.o font.o
OBJS = common.o support.o cprintf.o screen.o font.o ctype.o
SOBJS = or32.o
 
all: $(LIB)
/trunk/orpmon/common/support.c
5,6 → 5,8
#include "common.h"
#include "int.h"
 
#include <ctype.h>
 
volatile unsigned long timestamp = 0;
 
void int_main(void);
166,27 → 168,26
}
}
 
if ((base < 2) || (base > 36)) goto done; /* illegal base */
/* check for illegal base */
if ( !((base < 2) || (base > 36)) )
while (1) {
int digit = 40;
if ((*pos >= '0') && (*pos <= '9')) {
digit = (*pos - '0');
} else if (*pos >= 'a') {
digit = (*pos - 'a' + 10);
} else if (*pos >= 'A') {
digit = (*pos - 'A' + 10);
} else break;
 
while (1) {
int digit = 40;
if ((*pos >= '0') && (*pos <= '9')) {
digit = (*pos - '0');
} else if (*pos >= 'a') {
digit = (*pos - 'a' + 10);
} else if (*pos >= 'A') {
digit = (*pos - 'A' + 10);
} else break;
if (digit >= base) break;
 
if (digit >= base) break;
fail_char = ++pos;
number = number * base + digit;
}
 
fail_char = ++pos;
number = number * base + digit;
}
 
done:
if (endptr) *endptr = fail_char;
return number;
return number;
}
unsigned long get_timer (unsigned long base)
/trunk/orpmon/config.mk
10,7 → 10,7
#
# Specify the path to the tool chain
#
TOOL_PREFIX = /projects/or32-uclinux
TOOL_PREFIX = /tools/or32-uclinux
 
#########################################################################
 
/trunk/orpmon/ram.ld
1,9 → 1,9
MEMORY
{
vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000
ram : ORIGIN = 0x00002000, LENGTH = 0x00200000 - 0x00002000
ram : ORIGIN = 0x00002000, LENGTH = 0x00400000 - 0x00002000
}
 
SECTIONS
{
.vectors :
/trunk/orpmon/Makefile
31,14 → 31,14
 
orpmon.or32: depend subdirs reset.o $(LIBS) Makefile gencrc
$(LD) -Tram.ld -o $@ reset.o $(LIBS) $(LDFLAGS)
$(OBJCOPY) -j .text -O binary $@ $@.tmp
# $(OBJCOPY) -j .text -O binary $@ $@.tmp
#-S -j .vectors -j .text -j .data -j .rodata
./gencrc $@.tmp $@
# ./gencrc $@.tmp $@
 
orpmon-flash.or32: depend subdirs reset-flash.o $(LIBS) Makefile gencrc
$(LD) -Tflash.ld -o $@ reset-flash.o $(LIBS) $(LDFLAGS)
$(OBJCOPY) -j .text -O binary $@ $@.tmp
./gencrc $@.tmp $@
# $(OBJCOPY) -j .text -O binary $@ $@.tmp
# ./gencrc $@.tmp $@
 
gencrc: gencrc.c
$(HOSTCC) -o gencrc -g gencrc.c
/trunk/orpmon/drivers/tick.c
13,6 → 13,18
{
timestamp++;
mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD));
}
}
 
/*
sleep for n timer-ticks
*/
void sleep(unsigned long sleep_time)
{
unsigned long start_time;
 
start_time = timestamp;
while ( (timestamp - start_time) < sleep_time)
; /* do nothing */
}
 

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