URL
https://opencores.org/ocsvn/bluespec-h264/bluespec-h264/trunk
Subversion Repositories bluespec-h264
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- This comparison shows the changes necessary to convert path
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- from Rev 88 to Rev 89
- ↔ Reverse comparison
Rev 88 → Rev 89
/trunk/test-post-synth/test.pl
0,0 → 1,46
#!/usr/bin/perl |
# The MIT License |
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# Copyright (c) 2006-2007 Massachusetts Institute of Technology |
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# Permission is hereby granted, free of charge, to any person obtaining a copy |
# of this software and associated documentation files (the "Software"), to deal |
# in the Software without restriction, including without limitation the rights |
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
# copies of the Software, and to permit persons to whom the Software is |
# furnished to do so, subject to the following conditions: |
# The above copyright notice and this permission notice shall be included in |
# all copies or substantial portions of the Software. |
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
# THE SOFTWARE. |
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#build the code. |
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# build the golden decoder |
`cd ../test/decoder/ldecod && make`; |
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@h264files = `ls ../test/h264`; |
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foreach(@h264files) |
{ |
chomp($_); |
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print $_; |
print " "; |
`cp ../test/h264/$_ input.264`; |
system("wc input.264 | awk \'{printf(\"%08x\\n%08x\\n\", \$3, \$3, \$3, \$3)}\' > input_size.hex"); |
`perl ../test/hexfilegen.pl input.264`; |
system("./simv | grep \"OUT\" | awk \'{print \$2}\' > out.hex"); |
`perl ../test/dehex.pl out.hex out_hw.yuv`; |
`../test/decoder/bin/ldecod.exe -i input.264 -o out_gold.yuv`; |
$out=`diff -q out_gold.yuv out_hw.yuv`; |
print $out; |
print "\n"; |
} |
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/trunk/test-post-synth/Makefile
0,0 → 1,64
#======================================================================= |
# 6.375 Makefile for vcs-sim-rtl |
#----------------------------------------------------------------------- |
# $Id: Makefile,v 1.1 2008-06-26 18:11:24 jamey.hicks Exp $ |
# |
# This makefile will build a rtl simulator and run various tests to |
# verify proper functionality. |
# |
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default : all |
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basedir = ../.. |
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#-------------------------------------------------------------------- |
# Sources |
#-------------------------------------------------------------------- |
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# Library components |
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# Verilog sources |
verilogsrcdir = ../src_verilog |
synthsrcdir = ../dc/current |
srcdir = ../build/ |
vclibdir = /mit/6.375/libs/tsl180/tsl18fs120/verilog/ |
bsclibdir = /mit/6.375/tools/bluespec/Bluespec-2007.03/lib/Verilog/ |
vsrcs = \ |
$(verilogsrcdir)/top.v \ |
$(srcdir)/mkTH.v \ |
$(synthsrcdir)/synthesized.v \ |
/mit/6.375/libs/tsl180/tsl18fs120/distrib/tsl18/v3.0/verilog/tsl18fs120/zero/mtb_verilog.v \ |
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# Globally installed assembly tests |
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VCS = vcs |
VCS_OPTS = -notice -PP -line +v2k -timescale=1ns/1ps |
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VPATH += $(addprefix $(global_bmarkdir)/, $(global_bmarks)) \ |
$(addprefix $(local_bmarkdir)/, $(local_bmarks)) |
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incs += -I. $(addprefix -I$(global_bmarkdir)/, $(global_bmarks)) \ |
$(addprefix -I$(local_bmarkdir)/, $(local_bmarks)) |
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#------------------------------------------------------------ |
# Build the processor simulator |
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vcs_sim = simv |
$(vcs_sim) : $(vsrcs) |
$(VCS) $(VCS_OPTS) +incdir+$(srcdir) +incdir+$(synthsrcdir) -o $(vcs_sim) \ |
-y $(vclibdir) -y $(bsclibdir) +libext+.v+ $(addprefix -v ,$(vlibsrcs)) $(vsrcs) |
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junk += simv* csrc *.vpd vcs.key |
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all : $(vcs_sim) |
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#-------------------------------------------------------------------- |
# Clean up |
#-------------------------------------------------------------------- |
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clean : |
rm -rf $(junk) *~ \#* *.log *.cmd *.daidir |