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/v586/trunk/rtl/tiny_spi.v
0,0 → 1,232
//////////////////////////////////////////////////////////////////////
//// ////
//// tiny_spi.v ////
//// ////
//// This file is part of the TINY SPI IP core project ////
//// http://www.opencores.org/projects/tiny_spi/ ////
//// ////
//// Author(s): ////
//// - Thomas Chou <thomas@wytron.com.tw> ////
//// ////
//// All additional information is avaliable in the README ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module tiny_spi(
// system
input rst_i,
input clk_i,
// memory mapped
input stb_i,
input we_i,
output [31:0] dat_o,
input [31:0] dat_i,
output int_o,
input [2:0] adr_i,
//input cyc_i, // comment out for avalon
//output ack_o, // comment out for avalon
 
// spi
output MOSI,
output SCLK,
input MISO
);
 
parameter BAUD_WIDTH = 8;
parameter BAUD_DIV = 0;
parameter SPI_MODE = 0;
parameter BC_WIDTH = 3;
parameter DIV_WIDTH = BAUD_DIV ? $clog2(BAUD_DIV / 2 - 1) : BAUD_WIDTH;
 
 
reg [7:0] sr8, bb8;
wire [7:0] sr8_sf;
reg [BC_WIDTH - 1:0] bc, bc_next;
reg [DIV_WIDTH - 1:0] ccr;
reg [DIV_WIDTH - 1:0] cc, cc_next;
wire misod;
wire cstb, wstb, bstb, istb;
reg sck;
reg sf, ld;
reg bba; // buffer flag
reg txren, txeen;
wire txr, txe;
wire cpol, cpha;
reg cpolr, cphar;
wire wr;
wire cyc_i; // comment out for wishbone
wire ack_o; // comment out for wishbone
assign cyc_i = 1'b1; // comment out for wishbone
assign ack_o = stb_i & cyc_i; // zero wait
assign wr = stb_i & cyc_i & we_i & ack_o;
assign wstb = wr & (adr_i == 1);
assign istb = wr & (adr_i == 2);
assign cstb = wr & (adr_i == 3);
assign bstb = wr & (adr_i == 4);
assign sr8_sf = { sr8[6:0],misod };
assign dat_o =
(sr8 & {8{(adr_i == 0)}})
| (bb8 & {8{(adr_i == 1)}})
| ({ txr, txe } & {8{(adr_i == 2)}})
;
 
parameter
IDLE = 0,
PHASE1 = 1,
PHASE2 = 2
;
 
reg [1:0] spi_seq, spi_seq_next;
always @(posedge clk_i or posedge rst_i)
if (rst_i)
spi_seq <= IDLE;
else
spi_seq <= spi_seq_next;
 
always @(posedge clk_i)
begin
cc <= cc_next;
bc <= bc_next;
end
 
always @(/*AS*/bba or bc or cc or ccr or cpha or cpol or spi_seq)
begin
sck = cpol;
cc_next = BAUD_DIV ? (BAUD_DIV / 2 - 1) : ccr;
bc_next = bc;
ld = 1'b0;
sf = 1'b0;
 
case (spi_seq)
IDLE:
begin
if (bba)
begin
bc_next = 7;
ld = 1'b1;
spi_seq_next = PHASE2;
end
else
spi_seq_next = IDLE;
end
PHASE2:
begin
sck = (cpol ^ cpha);
if (cc == 0)
spi_seq_next = PHASE1;
else
begin
cc_next = cc - 1;
spi_seq_next = PHASE2;
end
end
PHASE1:
begin
sck = ~(cpol ^ cpha);
if (cc == 0)
begin
bc_next = bc -1;
sf = 1'b1;
if (bc == 0)
begin
if (bba)
begin
bc_next = 7;
ld = 1'b1;
spi_seq_next = PHASE2;
end
else
spi_seq_next = IDLE;
end
else
spi_seq_next = PHASE2;
end
else
begin
cc_next = cc - 1;
spi_seq_next = PHASE1;
end
end
endcase
end // always @ (...
 
always @(posedge clk_i)
begin
if (cstb) // control reg
{ cpolr, cphar } <= dat_i;
else
{ cpolr, cphar } <= { cpolr, cphar };
 
if (istb) // irq enable reg
{ txren, txeen } <= dat_i;
else
{ txren, txeen } <= { txren, txeen };
 
if (bstb) // baud reg
ccr <= dat_i;
else
ccr <= ccr;
 
if (ld) // shift reg
sr8 <= bb8;
else if (sf)
sr8 <= sr8_sf;
else
sr8 <= sr8;
 
if (wstb) // buffer reg
bb8 <= dat_i;
else if (ld)
bb8 <= (spi_seq == IDLE) ? sr8 : sr8_sf;
else
bb8 <= bb8;
end // always @ (posedge clk_i)
 
always @(posedge clk_i or posedge rst_i)
begin
if (rst_i)
bba <= 1'b0;
else if (wstb)
bba <= 1'b1;
else if (ld)
bba <= 1'b0;
else
bba <= bba;
end
 
assign { cpol, cpha } = ((SPI_MODE >= 0) & (SPI_MODE < 4)) ?
SPI_MODE : { cpolr, cphar };
assign txe = (spi_seq == IDLE);
assign txr = ~bba;
assign int_o = (txr & txren) | (txe & txeen);
assign SCLK = sck;
assign MOSI = sr8[7];
assign misod = MISO;
 
endmodule
/v586/trunk/rtl/arithbox.v
0,0 → 1,54
/* verilator lint_off WIDTH */
/* verilator lint_off UNUSED */
/* verilator lint_off COMBDLY */
 
module arithbox (arithop,calc_sz,ci,co,af,ai,sa,sb,opa,opb,resa,cmp);
 
input [3:0] arithop;
input [3:0] calc_sz;
input [31:0] opa,opb;
output reg [31:0] resa;
input ci,ai;
output reg co,af,sa,sb,cmp;
 
wire [4:0] af2,af3,af4,af5;
 
assign af2 = opa[3:0]+opb[3:0];
assign af3 = opa[3:0]+opb[3:0]+ci;
assign af4 = opa[3:0]-opb[3:0];
assign af5 = opa[3:0]-opb[3:0]-ci;
 
always @(*)
case (arithop)
4'b0000 : if (calc_sz==4) begin {co,resa[31:0]} <= opa[31:0] + opb[31:0]; sa<=opa[31]; sb<=opb[31]; af <= af2[4]; cmp <=0; end else
if (calc_sz==2) begin {co,resa[15:0]} <= opa[15:0] + opb[15:0]; sa<=opa[15]; sb<=opb[15]; af <= af2[4]; resa[31:16] <= opa[31:16]; cmp <=0; end else
begin {co,resa[ 7:0]} <= opa[ 7:0] + opb[ 7:0]; sa<=opa[ 7]; sb<=opb[ 7]; af <= af2[4]; resa[31: 8] <= opa[31: 8]; cmp <=0; end // add
4'b0001 : begin resa[31:0] <= opa[31:0] | opb[31:0]; sa<= 1 ; sb<= 0 ; af <= ai ; co <= 0; cmp <=0; end // or
4'b0010 : if (calc_sz==4) begin {co,resa[31:0]} <= opa[31:0] + opb[31:0] + ci; sa<=opa[31]; sb<=opb[31]; af <= af3[4]; cmp <=0; end else
if (calc_sz==2) begin {co,resa[15:0]} <= opa[15:0] + opb[15:0] + ci; sa<=opa[15]; sb<=opb[15]; af <= af3[4]; resa[31:16] <= opa[31:16]; cmp <=0; end else
begin {co,resa[ 7:0]} <= opa[ 7:0] + opb[ 7:0] + ci; sa<=opa[ 7]; sb<=opb[ 7]; af <= af3[4]; resa[31: 8] <= opa[31: 8]; cmp <=0; end // adc
4'b0011 : if (calc_sz==4) begin {co,resa[31:0]} <= opa[31:0] - opb[31:0] - ci; sa<=opa[31]; sb<=~opb[31];af <= af5[4]; cmp <=0; end else
if (calc_sz==2) begin {co,resa[15:0]} <= opa[15:0] - opb[15:0] - ci; sa<=opa[15]; sb<=~opb[15];af <= af5[4]; resa[31:16] <= opa[31:16]; cmp <=0; end else
begin {co,resa[ 7:0]} <= opa[ 7:0] - opb[ 7:0] - ci; sa<=opa[ 7]; sb<=~opb[ 7];af <= af5[4]; resa[31: 8] <= opa[31: 8]; cmp <=0; end // sbc & cmp
4'b0100 : begin resa[31:0] <= opa[31:0] & opb[31:0]; sa<=1 ; sb<= 0 ; af <= ai ; co <= 0; cmp <= 0; end // and
4'b0111 : begin
if (calc_sz==4) begin {co,resa[31:0]} <= opa[31:0] - opb[31:0]; sa<=opa[31]; sb<=~opb[31]; af <= af4[4]; cmp <=1; end else
if (calc_sz==2) begin {co,resa[15:0]} <= opa[15:0] - opb[15:0]; sa<=opa[15]; sb<=~opb[15]; af <= af4[4]; cmp <=1; resa[31:16] <= opa[31:16]; end else
begin {co,resa[ 7:0]} <= opa[ 7:0] - opb[ 7:0]; sa<=opa[ 7]; sb<=~opb[ 7]; af <= af4[4]; cmp <=1; resa[31: 8] <= opa[31: 8]; end // sub
end
4'b0101 : if (calc_sz==4) begin {co,resa[31:0]} <= opa[31:0] - opb[31:0]; sa<=opa[31]; sb<=~opb[31]; af <= af4[4]; cmp <=0; end else
if (calc_sz==2) begin {co,resa[15:0]} <= opa[15:0] - opb[15:0]; sa<=opa[15]; sb<=~opb[15]; af <= af4[4]; cmp <=0; resa[31:16] <= opa[31:16]; end else
begin {co,resa[ 7:0]} <= opa[ 7:0] - opb[ 7:0]; sa<=opa[ 7]; sb<=~opb[ 7]; af <= af4[4]; cmp <=0; resa[31: 8] <= opa[31: 8]; end // sub
4'b0110 : begin resa[31:0] <= opa[31:0] ^ opb[31:0]; sa<= 1 ; sb<= 0 ; af <= ai; co <= 0; cmp <=0; end // xor
default : begin resa[31:0] <= opa[31:0] ; sa <= 0 ; sb<= 0 ; af <= ai; co <= ci; cmp <=1; end
endcase
 
 
endmodule
/v586/trunk/rtl/shiftbox.v
0,0 → 1,93
/* verilator lint_off COMBDLY */
 
module shiftbox (shiftop,calc_sz,ci,co,opa,opb,resa,resb,resa4,resb4,co4);
 
input [3:0] shiftop;
input [3:0] calc_sz;
input [31:0] opa,opb;
output reg [31:0] resa,resb;
output reg [31:0] resa4,resb4;
input ci;
output reg co,co4;
 
always @(*)
case (shiftop)
4'b0000 : if (calc_sz==4) begin resa <= {opa[30:0],opa[31]}; co<=ci; resb<=opb; end else // rol without ci
if (calc_sz==2) begin resa[15:0] <= {opa[14:0],opa[15]}; co<=ci; resb<=opb; resa[31:16]<=opa[31:16]; end else
begin resa[ 7:0] <= {opa[ 6:0],opa[ 7]}; co<=ci; resb<=opb; resa[31: 8]<=opa[31: 8]; end
4'b0001 : if (calc_sz==4) begin resa <= {opa[0],opa[31:1]}; co<=ci; resb<=opb; end else // ror without ci
if (calc_sz==2) begin resa[15:0] <= {opa[0],opa[15:1]}; co<=ci; resb<=opb; resa[31:16]<=opa[31:16]; end else
begin resa[ 7:0] <= {opa[0],opa[ 7:1]}; co<=ci; resb<=opb; resa[31: 8]<=opa[31: 8]; end
4'b0010 : if (calc_sz==4) begin {co,resa[31:0]} <= {opa[31:0],ci}; resb<=opb; end else // rol with ci = rcl
if (calc_sz==2) begin {co,resa[15:0]} <= {opa[15:0],ci}; resb<=opb; resa[31:16]<=opa[31:16]; end else
begin {co,resa[ 7:0]} <= {opa[ 7:0],ci}; resb<=opb; resa[31: 8]<=opa[31: 8]; end
4'b0011 : if (calc_sz==4) begin {co,resa[31:0]} <= {opa[0],ci,opa[31:1]}; resb<=opb; end else // ror with ci = rcr
if (calc_sz==2) begin {co,resa[15:0]} <= {opa[0],ci,opa[15:1]}; resb<=opb; resa[31:16]<=opa[31:16]; end else
begin {co,resa[ 7:0]} <= {opa[0],ci,opa[ 7:1]}; resb<=opb; resa[31: 8]<=opa[31: 8]; end
4'b0100,
4'b0110 : if (calc_sz==4) begin {co,resa[31:0]} <= {opa[31:0],1'b0}; resb<=opb; end else // shl,sal with ci
if (calc_sz==2) begin {co,resa[15:0]} <= {opa[15:0],1'b0}; resb<=opb; resa[31:16]<=opa[31:16]; end else
begin {co,resa[ 7:0]} <= {opa[ 7:0],1'b0}; resb<=opb; resa[31: 8]<=opa[31: 8]; end
4'b0101 : if (calc_sz==4) begin resa[31:0] <= {1'b0,opa[31:1]}; co<=ci; resb<=opb; end else // shr
if (calc_sz==2) begin resa[15:0] <= {1'b0,opa[15:1]}; co<=ci; resb<=opb; resa[31:16]<=opa[31:16]; end else
begin resa[ 7:0] <= {1'b0,opa[ 7:1]}; co<=ci; resb<=opb; resa[31: 8]<=opa[31: 8]; end
 
4'b0111 : if (calc_sz==4) begin resa[31:0] <= {opa[31],opa[31:1]}; co<=ci; resb<=opb; end else // sar
if (calc_sz==2) begin resa[15:0] <= {opa[15],opa[15:1]}; co<=ci; resb<=opb; resa[31:16]<=opa[31:16]; end else
begin resa[ 7:0] <= {opa[ 7],opa[ 7:1]}; co<=ci; resb<=opb; resa[31: 8]<=opa[31: 8]; end
 
4'b1000 : if (calc_sz==4) begin {resb[31:0],co} <= {opa[0],opb[31:0]}; resa[31:0] <= {opa[31],opa[31:1]}; end else // shrd
begin {resb[15:0],co} <= {opa[0],opb[15:0]}; resa[15:0] <= {opa[15],opa[15:1]}; resa[31:16]<=opa[31:16]; resb[31:16]<=opb[31:16]; end
 
4'b1001 : if (calc_sz==4) begin {co,resb[31:0]} <= {opb[31:0],opa[31]}; resa[31:0] <= {opa[30:0],opa[0]}; end else // shld
begin {co,resb[15:0]} <= {opb[15:0],opa[15]}; resa[15:0] <= {opa[14:0],opa[0]}; resa[31:16]<=opa[31:16]; resb[31:16]<=opb[31:16];end
 
default : begin co<=ci; resb<=opb; resa <= opa; end
endcase
 
always @(*)
case (shiftop)
4'b0000 : if (calc_sz==4) begin resa4 <= {opa[27:0],opa[31:28]}; co4<=ci; resb4<=opb; end else // rol without ci
if (calc_sz==2) begin resa4[15:0] <= {opa[11:0],opa[15:12]}; co4<=ci; resb4<=opb; resa4[31:16]<=opa[31:16]; end else
begin resa4[ 7:0] <= {opa[ 3:0],opa[ 7:4]}; co4<=ci; resb4<=opb; resa4[31: 8]<=opa[31: 8]; end
4'b0001 : if (calc_sz==4) begin resa4 <= {opa[3:0],opa[31:4]}; co4<=ci; resb4<=opb; end else // ror without ci
if (calc_sz==2) begin resa4[15:0] <= {opa[3:0],opa[15:4]}; co4<=ci; resb4<=opb; resa4[31:16]<=opa[31:16]; end else
begin resa4[ 7:0] <= {opa[3:0],opa[ 7:4]}; co4<=ci; resb4<=opb; resa4[31: 8]<=opa[31: 8]; end
4'b0010 : if (calc_sz==4) begin {co4,resa4[31:0]} <= {opa[28:0],ci,opa[31:29]}; resb4<=opb; end else // rol with ci = rcl
if (calc_sz==2) begin {co4,resa4[15:0]} <= {opa[12:0],ci,opa[15:13]}; resb4<=opb; resa4[31:16]<=opa[31:16]; end else
begin {co4,resa4[ 7:0]} <= {opa[ 4:0],ci,opa[ 7: 5]}; resb4<=opb; resa4[31: 8]<=opa[31: 8]; end
4'b0011 : if (calc_sz==4) begin {co4,resa4[31:0]} <= {opa[3:0],ci,opa[31:4]}; resb4<=opb; end else // ror with ci = rcr
if (calc_sz==2) begin {co4,resa4[15:0]} <= {opa[3:0],ci,opa[15:4]}; resb4<=opb; resa4[31:16]<=opa[31:16]; end else
begin {co4,resa4[ 7:0]} <= {opa[3:0],ci,opa[ 7:4]}; resb4<=opb; resa4[31: 8]<=opa[31: 8]; end
4'b0100,
4'b0110 : if (calc_sz==4) begin {co4,resa4[31:0]} <= {opa[28:0],4'b0000}; resb4<=opb; end else // shl,sal with ci
if (calc_sz==2) begin {co4,resa4[15:0]} <= {opa[12:0],4'b0000}; resb4<=opb; resa4[31:16]<=opa[31:16]; end else
begin {co4,resa4[ 7:0]} <= {opa[ 4:0],4'b0000}; resb4<=opb; resa4[31: 8]<=opa[31: 8]; end
4'b0101 : if (calc_sz==4) begin resa4[31:0] <= {4'b0000,opa[31:4]}; co4<=ci; resb4<=opb; end else // shr
if (calc_sz==2) begin resa4[15:0] <= {4'b0000,opa[15:4]}; co4<=ci; resb4<=opb; resa4[31:16]<=opa[31:16]; end else
begin resa4[ 7:0] <= {4'b0000,opa[ 7:4]}; co4<=ci; resb4<=opb; resa4[31: 8]<=opa[31: 8]; end
 
4'b0111 : if (calc_sz==4) begin resa4[31:0] <= {opa[31],opa[31],opa[31],opa[31],opa[31:4]}; co4<=ci; resb4<=opb; end else // sar
if (calc_sz==2) begin resa4[15:0] <= {opa[15],opa[15],opa[15],opa[15],opa[15:4]}; co4<=ci; resb4<=opb; resa4[31:16]<=opa[31:16]; end else
begin resa4[ 7:0] <= {opa[ 7],opa[ 7],opa[ 7],opa[ 7],opa[ 7:4]}; co4<=ci; resb4<=opb; resa4[31: 8]<=opa[31: 8]; end
 
4'b1000 : if (calc_sz==4) begin resa4[31:0] <= {opa[31],opa[31],opa[31],opa[31],opa[31:4]}; {resb4[31:0],co4} <= {opa[3:0],opb[31:3]}; end else // shrd
begin resa4[15:0] <= {opa[15],opa[15],opa[15],opa[15],opa[15:4]}; {resb4[15:0],co4} <= {opa[3:0],opb[15:3]}; resa4[31:16]<=opa[31:16]; resb4[31:16]<=opb[31:16]; end
 
4'b1001 : if (calc_sz==4) begin resa4[31:0] <= {opa[27:0],opa[0],opa[0],opa[0],opa[0]}; {co4,resb4[31:0]} <= {opb[28:0],opa[31:28]}; end else // shld
begin resa4[15:0] <= {opa[11:0],opa[0],opa[0],opa[0],opa[0]}; {co4,resb4[15:0]} <= {opb[12:0],opa[15:12]}; resa4[31:16]<=opa[31:16]; resb4[31:16]<=opb[31:16]; end
 
default : begin co4<=ci; resb4<=opb; resa4 <= opa; end
endcase
endmodule

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