OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 883 to Rev 884
    ↔ Reverse comparison
  •

Rev 883 → Rev 884

/trunk/or1ksim/sim-config.h
273,6 → 273,17
int output_cfg; /* Whether sim is to output cfg files */
char script_fn[STR_SIZE]; /* Script file read */
int iprompt; /* Interactive prompt */
int cont_run; /* Continuos run versus single
step tracing switch. */
int cycles; /* Cycles counts fetch stages */
 
int mem_cycles; /* Each cycle has counter of mem_cycles;
this value is joined with cycles
at the end of the cycle; no sim
originated memory accesses should be
performed inbetween. */
int loadcycles; /* Load and store stalls */
int storecycles;
} sim;
 
/* Command line parameters */
288,6 → 299,10
unsigned long ld; /* Load data */
unsigned long sd; /* Store data */
unsigned long lsea; /* Load/Store effective address */
int instructions; /* Instructions executed */
int stalled;
int hazardwait; /* how many cycles were wasted because of hazards */
int supercycles; /* Superscalar cycles */
} cpu;
struct {
/trunk/or1ksim/debug/debug_unit.c
50,9 → 50,6
/* External STALL signal to debug interface */
int in_reset = 0;
 
/* Risc stall state */
int cpu_stalled = 0;
 
/* Current watchpoint state */
unsigned long watchpoints = 0;
 
66,7 → 63,7
development.riscop |= state ? RISCOP_STALL : 0;
if(testsprbits(SPR_DMR1, SPR_DMR1_DXFW)) /* If debugger disabled */
state = 0;
cpu_stalled = state;
runtime.cpu.stalled = state;
}
 
void du_reset()
/trunk/or1ksim/debug/debug_unit.h
85,9 → 85,6
#define RISCOP_STALL 0x00000001
#define RISCOP_RESET 0x00000002
 
/* Risc stall state */
extern int cpu_stalled;
 
/* Resets the debug unit */
void du_reset(void);
 
/trunk/or1ksim/cpu/or32/execute.c
52,9 → 52,7
 
/* Benchmark multi issue execution */
int multissue[20];
int supercycles;
int issued_per_cycle = 4;
int hazardwait = 0;
 
/* Whether break was hit - so we can step over a break */
static int break_just_hit = 0;
84,20 → 82,6
/* CCR (for dependency calculation) */
char ccr_flag[10] = "flag";
 
/* Cycles counts fetch stages */
int cycles;
 
/* Each cycle has counter of mem_cycles; this value is joined with cycles
at the end of the cycle; no sim originated memory accesses should be
performed inbetween. */
int mem_cycles;
 
/* Instructions executed */
int instructions;
 
/* Load and store stalls */
int loadcycles, storecycles;
 
/* Store buffer analysis - stores are accumulated and commited when IO is idle */
static int sbuf_head = 0, sbuf_tail = 0, sbuf_count = 0;
static int sbuf_buf[MAX_SBUF_LEN] = {0};
127,7 → 111,7
return reg[regno];
} else {
printf("\nABORT: read out of registers\n");
cont_run = 0;
runtime.sim.cont_run = 0;
return 0;
}
}
144,7 → 128,7
reg[regno] = value;
} else {
printf("\nABORT: write out of registers\n");
cont_run = 0;
runtime.sim.cont_run = 0;
}
}
 
155,7 → 139,7
{
if (regno < MAX_GPRS) {
#if RAW_RANGE_STATS
int delta = (cycles - raw_stats.reg[regno]);
int delta = (runtime.sim.cycles - raw_stats.reg[regno]);
if ((unsigned long)delta < (unsigned long)MAX_RAW_RANGE)
raw_stats.range[delta]++;
#endif /* RAW_RANGE */
162,7 → 146,7
return reg[regno];
} else {
printf("\nABORT: read out of registers\n");
cont_run = 0;
runtime.sim.cont_run = 0;
return 0;
}
}
187,11 → 171,11
if (regno < MAX_GPRS) {
reg[regno] = value;
#if RAW_RANGE_STATS
raw_stats.reg[regno] = cycles;
raw_stats.reg[regno] = runtime.sim.cycles;
#endif /* RAW_RANGE */
} else {
printf("\nABORT: write out of registers\n");
cont_run = 0;
runtime.sim.cont_run = 0;
}
}
 
282,7 → 266,7
}
break_just_hit = 0;
}
instructions++;
runtime.cpu.instructions++;
pc_phy &= ~0x03;
322,16 → 306,16
 
if (config.cpu.superscalar) {
if ((current->func_unit == it_branch) || (current->func_unit == it_jump))
storecycles += 0;
runtime.sim.storecycles += 0;
if (current->func_unit == it_store)
storecycles += 1;
runtime.sim.storecycles += 1;
if (current->func_unit == it_load)
loadcycles += 1;
runtime.sim.loadcycles += 1;
#if 0
if ((icomplet[0].func_unit == it_load) && check_depend())
loadcycles++;
runtime.sim.loadcycles++;
#endif
/* Pseudo multiple issue benchmark */
341,9 → 325,9
for (i = 0; i < 20; i++)
multissue[i] = 2;
issued_per_cycle = 2;
supercycles++;
runtime.cpu.supercycles++;
if (check_depend())
hazardwait++;
runtime.cpu.hazardwait++;
multissue[it_unknown] = 2;
multissue[it_shift] = 2;
multissue[it_compare] = 1;
379,9 → 363,9
 
/* Store buffer analysis - stores are accumulated and commited when IO is idle */
static inline sbuf_store (int cyc) {
int delta = cycles - sbuf_prev_cycles;
int delta = runtime.sim.cycles - sbuf_prev_cycles;
sbuf_total_cyc += cyc;
sbuf_prev_cycles = cycles;
sbuf_prev_cycles = runtime.sim.cycles;
//printf (">STORE %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);
//printf ("|%i,%i\n", sbuf_total_cyc, sbuf_wait_cyc);
397,7 → 381,7
/* Store buffer is full, take one out */
if (sbuf_count >= config.cpu.sbuf_len) {
sbuf_wait_cyc += sbuf_buf[sbuf_tail];
mem_cycles += sbuf_buf[sbuf_tail];
runtime.sim.mem_cycles += sbuf_buf[sbuf_tail];
sbuf_prev_cycles += sbuf_buf[sbuf_tail];
sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;
sbuf_count--;
411,8 → 395,8
 
/* Store buffer analysis - previous stores should commit, before any load */
static inline sbuf_load () {
int delta = cycles - sbuf_prev_cycles;
sbuf_prev_cycles = cycles;
int delta = runtime.sim.cycles - sbuf_prev_cycles;
sbuf_prev_cycles = runtime.sim.cycles;
//printf (">LOAD %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);
//printf ("|%i,%i\n", sbuf_total_cyc, sbuf_wait_cyc);
428,7 → 412,7
/* Wait for all stores to complete */
while (sbuf_count > 0) {
sbuf_wait_cyc += sbuf_buf[sbuf_tail];
mem_cycles += sbuf_buf[sbuf_tail];
runtime.sim.mem_cycles += sbuf_buf[sbuf_tail];
sbuf_prev_cycles += sbuf_buf[sbuf_tail];
sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;
sbuf_count--;
442,9 → 426,9
unsigned long i = iqueue[0].insn_addr;
 
if (i == 0xffffffff) return;
if (config.sim.exe_log_start <= instructions && (config.sim.exe_log_end <= 0 || instructions <= config.sim.exe_log_end)) {
if (config.sim.exe_log_marker && instructions % config.sim.exe_log_marker == 0) {
fprintf (runtime.sim.fexe_log, "--------------------- %8i instruction ---------------------\n", instructions);
if (config.sim.exe_log_start <= runtime.cpu.instructions && (config.sim.exe_log_end <= 0 || runtime.cpu.instructions <= config.sim.exe_log_end)) {
if (config.sim.exe_log_marker && runtime.cpu.instructions % config.sim.exe_log_marker == 0) {
fprintf (runtime.sim.fexe_log, "--------------------- %8i instruction ---------------------\n", runtime.cpu.instructions);
}
switch (config.sim.exe_log_type) {
case EXE_LOG_HARDWARE:
500,12 → 484,12
char temp[100];
 
dumpmemory(iqueue[0].insn_addr, iqueue[0].insn_addr + 4, 1, 0);
generate_time_pretty (temp, cycles);
printf(" (executed) [time %s, #%i]\n", temp, instructions);
generate_time_pretty (temp, runtime.sim.cycles);
printf(" (executed) [time %s, #%i]\n", temp, runtime.cpu.instructions);
if (config.cpu.superscalar)
printf ("Superscalar CYCLES: %u", supercycles);
printf ("Superscalar CYCLES: %u", runtime.cpu.supercycles);
if (config.cpu.hazards)
printf (" HAZARDWAIT: %u\n", hazardwait);
printf (" HAZARDWAIT: %u\n", runtime.cpu.hazardwait);
else
if (config.cpu.superscalar)
printf ("\n");
552,11 → 536,12
void cpu_reset()
{
int i;
cycles = 0;
instructions = 0;
supercycles = 0;
loadcycles = 0;
storecycles = 0;
runtime.sim.cycles = 0;
runtime.sim.loadcycles = 0;
runtime.sim.storecycles = 0;
runtime.cpu.instructions = 0;
runtime.cpu.supercycles = 0;
runtime.cpu.hazardwait = 0;
for (i = 0; i < MAX_GPRS; i++)
set_reg32 (i, 0);
memset(iqueue, 0, sizeof(iqueue));
589,7 → 574,7
{
if(fetch()) {
printf ("Breakpoint hit.\n");
cont_run = 0; /* memory breakpoint encountered */
runtime.sim.cont_run = 0; /* memory breakpoint encountered */
return 1;
}
decode_execute_wrapper (&iqueue[0]);
/trunk/or1ksim/cpu/or32/insnset.c
38,11 → 38,11
INSTRUCTION (l_sw) {
int old_cyc = 0;
IFF (config.cpu.dependstats) current->func_unit = it_store;
IFF (config.cpu.sbuf_len) old_cyc = mem_cycles;
IFF (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
set_operand32(0, eval_operand32(1, &breakpoint), &breakpoint);
if (config.cpu.sbuf_len) {
int t = mem_cycles;
mem_cycles = old_cyc;
int t = runtime.sim.mem_cycles;
runtime.sim.mem_cycles = old_cyc;
sbuf_store (t - old_cyc);
}
}
49,11 → 49,11
INSTRUCTION (l_sb) {
int old_cyc = 0;
IFF (config.cpu.dependstats) current->func_unit = it_store;
IFF (config.cpu.sbuf_len) old_cyc = mem_cycles;
IFF (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
set_operand8(0, eval_operand32(1, &breakpoint), &breakpoint);
if (config.cpu.sbuf_len) {
int t = mem_cycles;
mem_cycles = old_cyc;
int t = runtime.sim.mem_cycles;
runtime.sim.mem_cycles = old_cyc;
sbuf_store (t- old_cyc);
}
}
60,11 → 60,11
INSTRUCTION (l_sh) {
int old_cyc = 0;
IFF (config.cpu.dependstats) current->func_unit = it_store;
IFF (config.cpu.sbuf_len) old_cyc = mem_cycles;
IFF (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
set_operand16(0, eval_operand32(1, &breakpoint), &breakpoint);
if (config.cpu.sbuf_len) {
int t = mem_cycles;
mem_cycles = old_cyc;
int t = runtime.sim.mem_cycles;
runtime.sim.mem_cycles = old_cyc;
sbuf_store (t - old_cyc);
}
}
169,7 → 169,7
temp3 = eval_operand32(2, &breakpoint);
temp2 = eval_operand32(1, &breakpoint);
temp1 = temp2 / temp3;
/* cycles += 16; */
/* runtime.sim.cycles += 16; */
set_operand32(0, set_ov_flag (temp1), &breakpoint);
}
INSTRUCTION (l_sll) {
177,7 → 177,7
IFF (config.cpu.dependstats) current->func_unit = it_shift;
if ((signed)eval_operand32(1, &breakpoint) < 0)
sign = -1;
/* cycles += 2; */
/* runtime.sim.cycles += 2; */
set_operand32(0, set_ov_flag (eval_operand32(1, &breakpoint) << eval_operand32(2, &breakpoint)), &breakpoint);
}
INSTRUCTION (l_sra) {
186,12 → 186,12
if ((signed)eval_operand32(1, &breakpoint) < 0)
sign = -1;
/* cycles += 2; */
/* runtime.sim.cycles += 2; */
set_operand32(0, set_ov_flag ((signed)eval_operand32(1, &breakpoint) >> eval_operand32(2, &breakpoint)), &breakpoint);
}
INSTRUCTION (l_srl) {
IFF (config.cpu.dependstats) current->func_unit = it_shift;
/* cycles += 2; */
/* runtime.sim.cycles += 2; */
set_operand32(0, set_ov_flag (eval_operand32(1, &breakpoint) >> eval_operand32(2, &breakpoint)), &breakpoint);
}
INSTRUCTION (l_bf) {
239,9 → 239,9
struct mem_entry *entry;
struct label_entry *tmp;
if (verify_memoryarea(pcdelay) && (tmp = get_label (pcdelay)))
fprintf (runtime.sim.fprof, "+%08X %08X %08X %s\n", cycles, pc + 8, pcdelay, tmp->name);
fprintf (runtime.sim.fprof, "+%08X %08X %08X %s\n", runtime.sim.cycles, pc + 8, pcdelay, tmp->name);
else
fprintf (runtime.sim.fprof, "+%08X %08X %08X @%08X\n", cycles, pc + 8, pcdelay, pcdelay);
fprintf (runtime.sim.fprof, "+%08X %08X %08X @%08X\n", runtime.sim.cycles, pc + 8, pcdelay, pcdelay);
}
}
INSTRUCTION (l_jalr) {
255,7 → 255,7
pcdelay = eval_operand32(0, &breakpoint);
next_delay_insn = 1;
if (config.sim.profile)
fprintf (runtime.sim.fprof, "-%08X %08X\n", cycles, pcdelay);
fprintf (runtime.sim.fprof, "-%08X %08X\n", runtime.sim.cycles, pcdelay);
}
INSTRUCTION (l_rfe) {
IFF (config.cpu.dependstats) current->func_unit = it_exception;
274,7 → 274,7
if (config.debug.gdb_enabled)
set_stall_state (1);
else
cont_run = 0;
runtime.sim.cont_run = 0;
break;
case NOP_PRINTF:
stackaddr = evalsim_reg32(4);
388,7 → 388,7
mtspr(regno, value);
else {
printf("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
cont_run = 0;
runtime.sim.cont_run = 0;
}
}
INSTRUCTION (l_mfspr) {
405,7 → 405,7
else {
set_operand32(0, 0, &breakpoint);
printf("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
cont_run = 0;
runtime.sim.cont_run = 0;
}
}
INSTRUCTION (l_sys) {
/trunk/or1ksim/cpu/common/stats.c
197,10 → 197,7
} else
printf("No DMMU. Set UPR[DMP]\n");
{
extern int loadcycles, storecycles;
printf("Additional LOAD CYCLES: %u STORE CYCLES: %u\n", loadcycles, storecycles);
}
printf("Additional LOAD CYCLES: %u STORE CYCLES: %u\n", runtime.sim.loadcycles, runtime.sim.storecycles);
}
 
void printstats(int which)
276,11 → 273,11
extern int sbuf_total_cyc, sbuf_wait_cyc;
printf ("stats 6: Store buffer analysis\n");
printf ("Using store buffer of length %i.\n", config.cpu.sbuf_len);
printf ("Number of total memory store cycles: %i/%i\n", sbuf_total_cyc, cycles + sbuf_total_cyc - sbuf_wait_cyc);
printf ("Number of total memory store cycles: %i/%i\n", sbuf_total_cyc, runtime.sim.cycles + sbuf_total_cyc - sbuf_wait_cyc);
printf ("Number of cycles waiting for memory stores: %i\n", sbuf_wait_cyc);
printf ("Number of memory cycles spared: %i\n", sbuf_total_cyc - sbuf_wait_cyc);
printf ("Store speedup %3.2f%%, total speedup %3.2f%%\n", 100.*(sbuf_total_cyc - sbuf_wait_cyc)/sbuf_total_cyc,
100.*(sbuf_total_cyc - sbuf_wait_cyc) / (cycles + sbuf_total_cyc - sbuf_wait_cyc));
100.*(sbuf_total_cyc - sbuf_wait_cyc) / (runtime.sim.cycles + sbuf_total_cyc - sbuf_wait_cyc));
} else
printf ("Store buffer analysis disabled. Enable it to see analysis results.\n");
break;
/trunk/or1ksim/cpu/common/abstract.c
61,9 → 61,6
/* Virtual address of current access. */
unsigned long cur_vadd;
 
/* Temporary variable, which specifies how many cycles did the memory acces require */
extern int mem_cycles;
 
/* Calculates bit mask to fit the data */
unsigned long bit_mask (unsigned long data) {
int i = 0;
175,7 → 172,7
switch(cur_area->granularity) {
case 4:
temp = cur_area->readfunc(memaddr);
mem_cycles += cur_area->delayr;
runtime.sim.mem_cycles += cur_area->delayr;
break;
case 1:
temp = cur_area->readfunc(memaddr) << 24;
182,12 → 179,12
temp |= cur_area->readfunc(memaddr + 1) << 16;
temp |= cur_area->readfunc(memaddr + 2) << 8;
temp |= cur_area->readfunc(memaddr + 3);
mem_cycles += cur_area->delayr * 4;
runtime.sim.mem_cycles += cur_area->delayr * 4;
break;
case 2:
temp = cur_area->readfunc(memaddr) << 16;
temp |= cur_area->readfunc(memaddr + 2);
mem_cycles += cur_area->delayr * 2;
runtime.sim.mem_cycles += cur_area->delayr * 2;
break;
}
}
203,11 → 200,11
case 1:
temp = cur_area->readfunc(memaddr) << 8;
temp |= cur_area->readfunc(memaddr + 1);
mem_cycles += cur_area->delayr * 2;
runtime.sim.mem_cycles += cur_area->delayr * 2;
break;
case 2:
temp = cur_area->readfunc(memaddr);
mem_cycles += cur_area->delayr;
runtime.sim.mem_cycles += cur_area->delayr;
break;
case 4:
temp = evalsim_mem32 (memaddr & ~3ul);
229,7 → 226,7
switch(cur_area->granularity) {
case 1:
temp = cur_area->readfunc(memaddr);
mem_cycles += cur_area->delayr;
runtime.sim.mem_cycles += cur_area->delayr;
break;
case 2:
temp = evalsim_mem16 (memaddr & ~1ul);
415,7 → 412,7
switch(cur_area->granularity) {
case 4:
cur_area->writefunc(memaddr, value);
mem_cycles += cur_area->delayw;
runtime.sim.mem_cycles += cur_area->delayw;
break;
case 1:
cur_area->writefunc(memaddr , (value >> 24) & 0xFF);
422,12 → 419,12
cur_area->writefunc(memaddr + 1, (value >> 16) & 0xFF);
cur_area->writefunc(memaddr + 2, (value >> 8) & 0xFF);
cur_area->writefunc(memaddr + 3, (value ) & 0xFF);
mem_cycles += cur_area->delayw * 4;
runtime.sim.mem_cycles += cur_area->delayw * 4;
break;
case 2:
cur_area->writefunc(memaddr, (value >> 16) & 0xFFFF);
cur_area->writefunc(memaddr + 2, value & 0xFFFF);
mem_cycles += cur_area->delayw * 2;
runtime.sim.mem_cycles += cur_area->delayw * 2;
break;
}
} else {
444,11 → 441,11
case 1:
cur_area->writefunc(memaddr, (value >> 8) & 0xFF);
cur_area->writefunc(memaddr + 1, value & 0xFF);
mem_cycles += cur_area->delayw * 2;
runtime.sim.mem_cycles += cur_area->delayw * 2;
break;
case 2:
cur_area->writefunc(memaddr, value & 0xFFFF);
mem_cycles += cur_area->delayw;
runtime.sim.mem_cycles += cur_area->delayw;
break;
case 4:
temp = evalsim_mem32 (memaddr & ~3ul);
470,7 → 467,7
switch (cur_area->granularity) {
case 1:
cur_area->writefunc(memaddr, value);
mem_cycles += cur_area->delayw;
runtime.sim.mem_cycles += cur_area->delayw;
break;
case 2:
temp = evalsim_mem16 (memaddr & ~1ul);
/trunk/or1ksim/cpu/or1k/sprs.c
27,7 → 27,6
#include "abstract.h"
#include "sim-config.h"
 
extern int cont_run; /* defined in toplevel.c */
extern int flag;
 
sprword sprs[MAX_SPRS];
92,13 → 91,13
case 0xFFFF:
fclose(fo);
printf("Audio closed.\n");
cont_run = 0;
runtime.sim.cont_run = 0;
break;
case SPR_PMR:
/* PMR[SDF] and PMR[DCGE] are ignored completely. */
if (value & SPR_PMR_SUME) {
printf ("SUSPEND: PMR[SUME] bit was set.\n");
cont_run = 0;
runtime.sim.cont_run = 0;
}
break;
default:
/trunk/or1ksim/tick/tick.c
42,8 → 42,6
/* TT Mode Register */
unsigned long ttmr;
 
extern int cycles;
 
/* Reset. It initializes TTCR register. */
void tick_reset()
{
62,8 → 60,8
case 1:
if (!param) {
sprs[SPR_TTCR] = ttcr = 0;
cycles_start = cycles - ttcr;
SCHED_ADD(tick_job, 0, cycles + (ttmr & SPR_TTMR_PERIOD) - ttcr);
cycles_start = runtime.sim.cycles - ttcr;
SCHED_ADD(tick_job, 0, runtime.sim.cycles + (ttmr & SPR_TTMR_PERIOD) - ttcr);
}
case 2:
if (ttmr & SPR_TTMR_IE) {
73,7 → 71,7
else
/* If TEE is currently not set we have to pend tick exception
by rescheduling. */
SCHED_ADD(tick_job, 1, cycles + 1);
SCHED_ADD(tick_job, 1, runtime.sim.cycles + 1);
}
break;
}
89,8 → 87,8
SCHED_FIND_REMOVE(tick_job, 0);
SCHED_FIND_REMOVE(tick_job, 1);
if (mode == 1 || mode == 2) {
SCHED_ADD(tick_job, 0, cycles + (ttmr & SPR_TTMR_PERIOD) - ttcr);
cycles_start = cycles - ttcr;
SCHED_ADD(tick_job, 0, runtime.sim.cycles + (ttmr & SPR_TTMR_PERIOD) - ttcr);
cycles_start = runtime.sim.cycles - ttcr;
}
}
 
106,10 → 104,10
break;
case 1: /* Timer should auto restart */
sprs[SPR_TTCR] = ttcr = 0;
cycles_start = cycles;
cycles_start = runtime.sim.cycles;
SCHED_FIND_REMOVE(tick_job, 0);
SCHED_FIND_REMOVE(tick_job, 1);
SCHED_ADD(tick_job, 0, cycles + (ttmr & SPR_TTMR_PERIOD) - ttcr);
SCHED_ADD(tick_job, 0, runtime.sim.cycles + (ttmr & SPR_TTMR_PERIOD) - ttcr);
break;
case 2: /* Stop the timer when match */
SCHED_FIND_REMOVE(tick_job, 0);
122,6 → 120,6
 
unsigned long spr_read_ttcr ()
{
/*debug (7, "ttcr ---- %08x\n", cycles - cycles_start);*/
return cycles - cycles_start;
/*debug (7, "ttcr ---- %08x\n", runtime.sim.cycles - cycles_start);*/
return runtime.sim.cycles - cycles_start;
}
/trunk/or1ksim/cache/dcache_model.c
73,7 → 73,6
int set, way = -1;
int i;
unsigned long tagaddr;
extern int mem_cycles;
unsigned long tmp;
 
if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
104,7 → 103,7
if (dc[set].way[i].lru > dc[set].way[way].lru)
dc[set].way[i].lru--;
dc[set].way[way].lru = config.dc.ustates - 1;
mem_cycles += config.dc.load_hitdelay;
runtime.sim.mem_cycles += config.dc.load_hitdelay;
 
tmp = dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
if (width == 4)
142,7 → 141,7
if (dc[set].way[i].lru)
dc[set].way[i].lru--;
dc[set].way[minway].lru = config.dc.ustates - 1;
mem_cycles += config.dc.load_missdelay;
runtime.sim.mem_cycles += config.dc.load_missdelay;
 
tmp = dc[set].way[minway].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
if (width == 4)
174,7 → 173,6
int set, way = -1;
int i;
unsigned long tagaddr;
extern int mem_cycles;
unsigned long tmp;
 
if (width == 4)
207,7 → 205,7
if (dc[set].way[i].lru > dc[set].way[way].lru)
dc[set].way[i].lru--;
dc[set].way[way].lru = config.dc.ustates - 1;
mem_cycles += config.dc.store_hitdelay;
runtime.sim.mem_cycles += config.dc.store_hitdelay;
 
tmp = dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
if (width == 4)
247,7 → 245,7
if (dc[set].way[i].lru)
dc[set].way[i].lru--;
dc[set].way[minway].lru = config.dc.ustates - 1;
mem_cycles += config.dc.store_missdelay;
runtime.sim.mem_cycles += config.dc.store_missdelay;
}
}
 
/trunk/or1ksim/cache/icache_model.c
74,7 → 74,6
int set, way = -1;
int i;
unsigned long tagaddr;
extern int mem_cycles;
 
/* ICache simulation enabled/disabled. */
if ((!testsprbits(SPR_UPR, SPR_UPR_ICP)) || (!testsprbits(SPR_SR, SPR_SR_ICE)) || insn_ci)
97,7 → 96,7
if (ic[set].way[i].lru > ic[set].way[way].lru)
ic[set].way[i].lru--;
ic[set].way[way].lru = config.ic.ustates - 1;
mem_cycles += config.ic.hitdelay;
runtime.sim.mem_cycles += config.ic.hitdelay;
return (ic[set].way[way].line[(fetchaddr & (config.ic.blocksize - 1)) >> 2]);
}
else { /* No, we didn't. */
125,7 → 124,7
if (ic[set].way[i].lru)
ic[set].way[i].lru--;
ic[set].way[minway].lru = config.ic.ustates - 1;
mem_cycles += config.ic.missdelay;
runtime.sim.mem_cycles += config.ic.missdelay;
return (ic[set].way[minway].line[(fetchaddr & (config.ic.blocksize - 1)) >> 2]);
}
}
/trunk/or1ksim/peripheral/eth.c
304,7 → 304,7
< sizeof(eth->rx.packet_length) ) {
/* TODO: just do what real ethernet would do (some kind of error state) */
debug (4, "eth_start_rx(): File does not have a packet ready for RX (len = %d)\n", eth->rx.packet_length );
cont_run = 0;
runtime.sim.cont_run = 0;
break;
}
 
721,7 → 721,7
return eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4];
printf( "eth_read32( 0x%08lX ): Illegal address\n", addr + eth->baseaddr );
cont_run = 0;
runtime.sim.cont_run = 0;
return 0;
}
/* ========================================================================= */
777,7 → 777,7
}
printf( "eth_write32( 0x%08lX ): Illegal address\n", addr + eth->baseaddr );
cont_run = 0;
runtime.sim.cont_run = 0;
return;
}
/* ========================================================================= */
/trunk/or1ksim/peripheral/ps2kbd.c
149,7 → 149,7
break;
default:
fprintf (stderr, "Write out of keyboard space (0x%08x)!\n", addr);
cont_run = 0;
runtime.sim.cont_run = 0;
break;
}
}
218,7 → 218,7
return 0;
default:
fprintf (stderr, "Read out of keyboard space (0x%08x)!\n", addr);
cont_run = 0;
runtime.sim.cont_run = 0;
return 0;
}
}
238,7 → 238,7
if (config.sim.verbose && kbd_int)
printf("Keyboard Interrupt.... kbd_kresp %x kbd_buf_count %x \n", kbd_kresp, kbd_buf_count);
if (kbd_int) report_interrupt(config.kbd.irq);
SCHED_ADD(kbd_job, 0, cycles + kbd_slowdown);
SCHED_ADD(kbd_job, 0, runtime.sim.cycles + kbd_slowdown);
}
 
/* Reset all VGAs */
259,7 → 259,7
}
kbd_slowdown = (long) ((config.sim.system_kfreq * 1000.) / KBD_BAUD_RATE);
if (kbd_slowdown <= 0) kbd_slowdown = 1;
if (config.kbd.enabled) SCHED_ADD(kbd_job, 0, cycles + kbd_slowdown);
if (config.kbd.enabled) SCHED_ADD(kbd_job, 0, runtime.sim.cycles + kbd_slowdown);
}
}
 
/trunk/or1ksim/peripheral/fb.c
56,7 → 56,7
a /= 4;
if (a < 0 || a >= 256) {
fprintf (stderr, "Write out of palette buffer (0x%08x)!\n", addr);
cont_run = 0;
runtime.sim.cont_run = 0;
} else pal[a] = value;
break;
}
78,7 → 78,7
a /= 4;
if (a < 0 || a >= 256) {
fprintf (stderr, "Read out of palette buffer (0x%08x)!\n", addr);
cont_run = 0;
runtime.sim.cont_run = 0;
return 0;
} else return pal[a];
}
258,11 → 258,11
else fb_dump_image8 (temp);
fb_pic++;
}
SCHED_ADD(fb_job, 0, cycles + config.fb.refresh_rate - config.fb.refresh_rate / REFRESH_DIVIDER);
SCHED_ADD(fb_job, 0, runtime.sim.cycles + config.fb.refresh_rate - config.fb.refresh_rate / REFRESH_DIVIDER);
fb_in_refresh = 0;
} else {
fb_refresh_count++;
SCHED_ADD(fb_job, 1, cycles + config.fb.refresh_rate / REFRESH_DIVIDER);
SCHED_ADD(fb_job, 1, runtime.sim.cycles + config.fb.refresh_rate / REFRESH_DIVIDER);
}
}
282,6 → 282,6
 
if (config.fb.baseaddr)
register_memoryarea(config.fb.baseaddr, FB_PAL + 256*4, 4, fb_read32, fb_write32);
SCHED_ADD(fb_job, 0, cycles + config.fb.refresh_rate);
SCHED_ADD(fb_job, 0, runtime.sim.cycles + config.fb.refresh_rate);
}
}
/trunk/or1ksim/peripheral/dma.c
121,7 → 121,7
/* verify we found a controller */
if ( dma == NULL ) {
fprintf( stderr, "dma_read32( 0x%08lX ): Out of range\n", addr );
cont_run = 0;
runtime.sim.cont_run = 0;
return 0;
}
 
129,7 → 129,7
 
if ( addr % 4 != 0 ) {
fprintf( stderr, "dma_read32( 0x%08lX ): Not register-aligned\n", addr + dma->baseaddr );
cont_run = 0;
runtime.sim.cont_run = 0;
return 0;
}
 
143,7 → 143,7
case DMA_INT_SRC_B: return dma->regs.int_src_b;
default:
fprintf( stderr, "dma_read32( 0x%08lX ): Illegal register\n", addr + dma->baseaddr );
cont_run = 0;
runtime.sim.cont_run = 0;
return 0;
}
} else {
195,7 → 195,7
/* verify we found a controller */
if ( dma == NULL ) {
fprintf( stderr, "dma_write32( 0x%08lX ): Out of range\n", addr );
cont_run = 0;
runtime.sim.cont_run = 0;
return;
}
 
203,7 → 203,7
 
if ( addr % 4 != 0 ) {
fprintf( stderr, "dma_write32( 0x%08lX, 0x%08lX ): Not register-aligned\n", addr + dma->baseaddr, value );
cont_run = 0;
runtime.sim.cont_run = 0;
return;
}
 
221,7 → 221,7
case DMA_INT_SRC_B: dma->regs.int_src_b = value; break;
default:
fprintf( stderr, "dma_write32( 0x%08lX ): Illegal register\n", addr + dma->baseaddr );
cont_run = 0;
runtime.sim.cont_run = 0;
return;
}
} else {
/trunk/or1ksim/peripheral/vga.c
50,7 → 50,7
if (found < 0) {
fprintf( stderr, "vga_write32( 0x%08lX ): Out of range\n", addr);
cont_run = 0;
runtime.sim.cont_run = 0;
return;
}
 
71,7 → 71,7
vga[found].palette[1][addr - VGA_CLUTB] = value & 0x00ffffff;
} else {
fprintf( stderr, "vga_write32( 0x%08lX, 0x%08lX ): Out of range\n", addr + config.vgas[found].baseaddr, value);
cont_run = 0;
runtime.sim.cont_run = 0;
return;
}
break;
93,7 → 93,7
if (found < 0) {
fprintf( stderr, "vga_read32( 0x%08lX ): Out of range\n", addr);
cont_run = 0;
runtime.sim.cont_run = 0;
return 0;
}
 
114,7 → 114,7
return vga[found].palette[1][addr - VGA_CLUTB];
} else {
fprintf( stderr, "vga_read32( 0x%08lX ): Out of range\n", addr);
cont_run = 0;
runtime.sim.cont_run = 0;
return 0;
}
break;
224,7 → 224,7
sprintf (temp, "%s%04i.bmp", config.vgas[param].filename, vga[param].pics++);
vga_dump_image (temp, param);
SCHED_ADD(vga_job, param, cycles + config.vgas[param].refresh_rate);
SCHED_ADD(vga_job, param, runtime.sim.cycles + config.vgas[param].refresh_rate);
}
 
/* Reset all VGAs */
249,6 → 249,6
 
if (config.vgas[i].baseaddr)
register_memoryarea(config.vgas[i].baseaddr, VGA_ADDR_SPACE, 4, vga_read32, vga_write32);
SCHED_ADD(vga_job, i, cycles + config.vgas[i].refresh_rate);
SCHED_ADD(vga_job, i, runtime.sim.cycles + config.vgas[i].refresh_rate);
}
}
/trunk/or1ksim/peripheral/16450.c
339,7 → 339,7
int retval;
/* Schedule for later */
SCHED_ADD (uart_clock16, i, cycles + UART_CLOCK_DIVIDER);
SCHED_ADD (uart_clock16, i, runtime.sim.cycles + UART_CLOCK_DIVIDER);
/* If VAPI is not selected, UART communicates with two file streams;
if VAPI is selected, we use VAPI streams. */
600,7 → 600,7
uarts[i].vapi.cur_break = uarts[i].vapi.cur_break_cnt = uarts[i].vapi.next_break = 0;
uarts[i].vapi.next_break_cnt = -1;
printf ("%i\n", i);
SCHED_ADD (uart_clock16, i, cycles + UART_CLOCK_DIVIDER);
SCHED_ADD (uart_clock16, i, runtime.sim.cycles + UART_CLOCK_DIVIDER);
}
}
 
/trunk/or1ksim/mmu/dmmu.c
36,7 → 36,6
int i;
unsigned long tagaddr;
unsigned long vpn, ppn;
extern int mem_cycles;
 
if (!(mfspr(SPR_SR) & SPR_SR_DME) || !testsprbits(SPR_UPR, SPR_UPR_DMP)) {
data_ci = (virtaddr >= 0x80000000);
79,7 → 78,7
/* Check if page is cache inhibited */
data_ci = (mfspr(SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;
 
mem_cycles += config.dmmu.hitdelay;
runtime.sim.mem_cycles += config.dmmu.hitdelay;
ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize;
return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);
}
104,7 → 103,7
except_handle(EXCEPT_DTLBMISS, virtaddr);
/* if tlb refill implemented in HW */
/* return getsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN) * config.dmmu.pagesize + (virtaddr % config.dmmu.pagesize); */
mem_cycles += config.dmmu.missdelay;
runtime.sim.mem_cycles += config.dmmu.missdelay;
return 0;
}
}
/trunk/or1ksim/mmu/immu.c
36,8 → 36,7
int i;
unsigned long tagaddr;
unsigned long vpn, ppn;
extern int mem_cycles;
 
if (!(mfspr(SPR_SR) & SPR_SR_IME) || !(testsprbits(SPR_UPR, SPR_UPR_IMP))) {
insn_ci = (virtaddr >= 0x80000000);
return virtaddr;
77,7 → 76,7
/* Check if page is cache inhibited */
insn_ci = (mfspr(SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_CI) == SPR_ITLBTR_CI;
 
mem_cycles += config.immu.hitdelay;
runtime.sim.mem_cycles += config.immu.hitdelay;
ppn = mfspr(SPR_ITLBTR_BASE(way) + set) / config.immu.pagesize;
return (ppn * config.immu.pagesize) + (virtaddr % config.immu.pagesize);
}
102,7 → 101,7
except_handle(EXCEPT_ITLBMISS, virtaddr);
/* if tlb refill implemented in HW */
/* return getsprbits(SPR_ITLBTR_BASE(minway) + set, SPR_ITLBTR_PPN) * config.immu.pagesize + (virtaddr % config.immu.pagesize); */
mem_cycles += config.immu.missdelay;
runtime.sim.mem_cycles += config.immu.missdelay;
return 0;
}
}
/trunk/or1ksim/toplevel.c
60,11 → 60,8
#include "atahost.h"
 
/* CVS revision number. */
const char rcsrev[] = "$Revision: 1.88 $";
const char rcsrev[] = "$Revision: 1.89 $";
 
/* Continuos run versus single step tracing switch. */
int cont_run;
 
/* History of execution */
int histexec[HISTEXEC_LEN];
 
109,7 → 106,7
void ctrl_c(signum)
int signum;
{
cont_run = cpu_stalled ? 0 : 1;
runtime.sim.cont_run = runtime.cpu.stalled ? 0 : 1;
runtime.sim.iprompt = 1;
set_stall_state (0);
signal(SIGINT, ctrl_c);
204,7 → 201,7
fprintf(stderr, "ERROR: Problems opening profile file.\n");
exit (1);
} else
fprintf(runtime.sim.fprof, "+00000000 FFFFFFFF FFFFFFFF total\n");
fprintf(runtime.sim.fprof, "+00000000 FFFFFFFF FFFFFFFF [outside functions]\n");
}
if (config.sim.mprofile) {
359,8 → 356,7
void sim_done ()
{
if (config.sim.profile) {
extern int cycles;
fprintf(runtime.sim.fprof,"-%08X FFFFFFFF\n", cycles);
fprintf(runtime.sim.fprof,"-%08X FFFFFFFF\n", runtime.sim.cycles);
fclose(runtime.sim.fprof);
}
383,7 → 379,7
param = SCHED_PEEK().param;
SCHED_REMOVE();
func (param);
} while (cycles >= SCHED_PEEK().time);
} while (runtime.sim.cycles >= SCHED_PEEK().time);
}
 
/* Main function */
446,9 → 442,6
sim_init ();
signal(SIGINT, ctrl_c);
 
#warning REMOVE ME!
main_cuc (runtime.sim.filename);
while(1) {
if (runtime.sim.iprompt) {
if (config.debug.gdb_enabled)
515,7 → 508,7
help();
else
if (strcmp(item1, "t") == 0) { /* trace */
cont_run = 1;
runtime.sim.cont_run = 1;
} else
if (strcmp(item1, "dm") == 0) { /* dump memory */
char item2[20];
663,12 → 656,12
hush = 1;
else
hush = 0;
cont_run = strtol(item2, NULL, 0);
runtime.sim.cont_run = strtol(item2, NULL, 0);
} else
if(!strcmp(item1, "stall")) { /* Added by CZ 210801 */
set_stall_state (1);
runtime.sim.iprompt = 0;
cont_run = -1;
runtime.sim.cont_run = -1;
hush = 1;
} else
if (strcmp(item1, "stats") == 0) { /* stats */
719,17 → 712,15
}
 
/* MM: 'run -1' means endless execution. */
while(cont_run) {
extern int mem_cycles;
 
while(runtime.sim.cont_run) {
IFF (config.debug.enabled) {
if (cpu_stalled) {
if (runtime.cpu.stalled) {
if(config.debug.gdb_enabled) {
BlockJTAG();
HandleServerSocket(false);
} else {
fprintf (stderr, "WARNING: CPU stalled and gdb connection not enabled.");
cont_run = 0;
runtime.sim.cont_run = 0;
}
continue;
}
738,9 → 729,9
/* Each cycle has counter of mem_cycles; this value is joined with cycles
at the end of the cycle; no sim originated memory accesses should be
performed inbetween. */
mem_cycles = 0;
runtime.sim.mem_cycles = 0;
if (!config.pm.enabled || !testsprbits(SPR_PMR, SPR_PMR_DME | SPR_PMR_SME)) {
if (cont_run > 0) cont_run--;
if (runtime.sim.cont_run > 0) runtime.sim.cont_run--;
pic_clock ();
if (cpu_clock ()) break;
if (config.dc.enabled) dc_clock();
755,8 → 746,8
IFF(config.debug.enabled)
if (testsprbits(SPR_DMR1, SPR_DMR1_ST)) set_stall_state (1);
 
cycles += mem_cycles;
if (cycles >= SCHED_PEEK().time) do_scheduler ();
runtime.sim.cycles += runtime.sim.mem_cycles;
if (runtime.sim.cycles >= SCHED_PEEK().time) do_scheduler ();
if (!hush) dumpreg();
}
hush = 0;
/trunk/or1ksim/support/sched.c
39,3 → 39,4
{
SCHED_INIT ();
}
#warning Scheduler should continue from previous cycles not current ones
/trunk/or1ksim/support/sched.h
64,7 → 64,7
/* Adds new job to the queue */
#define SCHED_ADD(job_func, job_param, job_time) {\
int ___i;\
if (SCHED_DEBUG > 0) printf ("%s@%i:SCHED_ADD(func %x, param %i, time %i)\n", __FUNCTION__, cycles, (job_func), (job_param), (job_time));\
if (SCHED_DEBUG > 0) printf ("%s@%i:SCHED_ADD(func %x, param %i, time %i)\n", __FUNCTION__, runtime.sim.cycles, (job_func), (job_param), (job_time));\
SCHED_PRINT_JOBS();\
if (SCHED_DEBUG > 1) printf ("--------\n");\
___i = scheduler.size++;\
79,7 → 79,7
#define SCHED_REMOVE_ITEM(index) {\
struct sched_entry *tmp;\
int ___i = (index), ___j;\
if (SCHED_DEBUG > 0) printf ("%s@%i:SCHED_REMOVE%i(time %i)\n", __FUNCTION__, cycles, (index), scheduler.heap[___i].time); \
if (SCHED_DEBUG > 0) printf ("%s@%i:SCHED_REMOVE%i(time %i)\n", __FUNCTION__, runtime.sim.cycles, (index), scheduler.heap[___i].time); \
SCHED_PRINT_JOBS();\
if (SCHED_DEBUG > 1) printf ("--------\n");\
tmp = &scheduler.heap[--scheduler.size];\
/trunk/or1ksim/support/simprintf.c
74,7 → 74,6
char *fmtstrend;
char *fmtstrpart = fmtstr;
int tee_exe_log;
extern long instructions;
#if STACK_ARGS
argaddr = stackaddr;
82,7 → 81,7
argaddr = 3;
#endif
tee_exe_log = (config.sim.exe_log && (config.sim.exe_log_type == EXE_LOG_SOFTWARE || config.sim.exe_log_type == EXE_LOG_SIMPLE)
&& config.sim.exe_log_start <= instructions && (config.sim.exe_log_end <= 0 || instructions <= config.sim.exe_log_end));
&& config.sim.exe_log_start <= runtime.cpu.instructions && (config.sim.exe_log_end <= 0 || runtime.cpu.instructions <= config.sim.exe_log_end));
if (tee_exe_log)
fprintf (runtime.sim.fexe_log, "SIMPRINTF: ");

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