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URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

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Rev 89 → Rev 90

/trunk/bench/verilog/dbg_tb.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.18 2004/01/07 11:59:48 mohor
// temp4 version.
//
// Revision 1.17 2004/01/06 17:14:59 mohor
// temp3 version.
//
332,7 → 335,7
// debug_wishbone(`WB_READ16, 1'b0, 32'h12345678, 16'h4, 32'h86156251, result, "abc 4"); // {command, ready, addr, length, crc, result, text}
// debug_wishbone(`WB_READ16, 1'b0, 32'h1234567a, 16'h4, 32'h85a43b5f, result, "abc 5"); // {command, ready, addr, length, crc, result, text}
//
debug_wishbone(`WB_READ32, 1'b0, 32'h12345678, 16'h4, 32'hc9420a40, result, "abc"); // {command, ready, addr, length, crc, result, text}
debug_wishbone(`WB_READ32, 1'b0, 32'h12345678, 16'h4, 32'hc9420a40, result, "read32 1"); // {command, ready, addr, length, crc, result, text}
//
// debug_wishbone(`WB_READ16, 1'b0, 32'h12345679, 16'h4, 32'h87cdced6, result, "abc 6"); // {command, ready, addr, length, crc, result, text}
 
339,15 → 342,15
#10000;
// xxx(4'b1001, 32'he579b242);
 
debug_wishbone(`WB_READ32, 1'b1, 32'h12345678, 16'h4, 32'hc9420a40, result, "pac 1"); // {command, ready, addr, length, crc, result, text}
debug_wishbone(`WB_READ32, 1'b1, 32'h12345678, 16'h4, 32'hc9420a40, result, "read32 2"); // {command, ready, addr, length, crc, result, text}
 
#10000;
wb_slave.cycle_response(`ACK_RESPONSE, 8'h55, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 16'h4, 32'hc935a962, result, "pac 2"); // {command, ready, addr, length, crc, result, text}
debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 16'h4, 32'hc935a962, result, "read32 3"); // {command, ready, addr, length, crc, result, text}
 
#10000;
wb_slave.cycle_response(`ERR_RESPONSE, 8'h03, 8'h2); // (`ERR_RESPONSE, wbs_waits, wbs_retries);
debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 16'h4, 32'hc935a962, result, "pac 3"); // {command, ready, addr, length, crc, result, text}
debug_wishbone(`WB_READ32, 1'b1, 32'h12346668, 16'h4, 32'hc935a962, result, "read32 4"); // {command, ready, addr, length, crc, result, text}
 
#10000;
debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 32'hc7b0424d, result, "status 1"); // {command, ready, addr, length, crc, result, text}
357,29 → 360,35
 
#10000;
wb_slave.cycle_response(`ACK_RESPONSE, 8'h4a, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
debug_wishbone(`WB_READ32, 1'b1, 32'h12347778, 16'hc, 32'hd9ce3bbe, result, "rst_status"); // {command, ready, addr, length, crc, result, text}
debug_wishbone(`WB_READ32, 1'b1, 32'h12347778, 16'hc, 32'hd9ce3bbe, result, "read32 5"); // {command, ready, addr, length, crc, result, text}
 
#10000;
debug_wishbone(`WB_WRITE32, 1'b0, 32'h12346668, 16'h8, 32'hc5a58ff5, result, "write 32 bit len8"); // {command, ready, addr, length, crc, result, text}
debug_wishbone(`WB_WRITE32, 1'b0, 32'h12346668, 16'h8, 32'hc5a58ff5, result, "wr32 len8"); // {command, ready, addr, length, crc, result, text}
 
#10000;
debug_wishbone(`WB_WRITE16, 1'b0, 32'h12344446, 16'h8, 32'hed029606, result, "write 16 bit len8"); // {command, ready, addr, length, crc, result, text}
debug_wishbone(`WB_WRITE16, 1'b0, 32'h12344446, 16'h8, 32'hed029606, result, "wr16 len8"); // {command, ready, addr, length, crc, result, text}
 
#10000;
debug_wishbone(`WB_WRITE8, 1'b0, 32'h12344446, 16'h8, 32'h3cfb2e35, result, "write 8 bit len8"); // {command, ready, addr, length, crc, result, text}
debug_wishbone(`WB_WRITE8, 1'b0, 32'h12344446, 16'h8, 32'h3cfb2e35, result, "wr8 len8"); // {command, ready, addr, length, crc, result, text}
 
#10000;
debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 32'h4c3fb42a, result, "go 1"); // {command, ready, addr, length, crc, result, text}
debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 32'h5e9dd377, result, "go 1"); // {command, ready, addr, length, crc, result, text}
 
#10000;
debug_wishbone(`WB_READ32, 1'b1, 32'h12340100, 16'hc, 32'h8bbeb90d, result, "read32 len c"); // {command, ready, addr, length, crc, result, text}
debug_wishbone(`WB_READ32, 1'b1, 32'h12340100, 16'hc, 32'h8bbeb90d, result, "read32 6"); // {command, ready, addr, length, crc, result, text}
 
#10000;
debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 32'hd4b43491, result, "go read32"); // {command, ready, addr, length, crc, result, text}
debug_wishbone(`WB_READ16, 1'b1, 32'h12340102, 16'he, 32'hcedab37c, result, "read16 7"); // {command, ready, addr, length, crc, result, text}
 
#10000;
debug_wishbone(`WB_READ8, 1'b1, 32'h1234010e, 16'h6, 32'h308c30d3, result, "read8 8"); // {command, ready, addr, length, crc, result, text}
 
#10000;
debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 32'hd4b43491, result, "go 2"); // {command, ready, addr, length, crc, result, text}
 
 
 
 
/*
// Testing read and write to CPU0 registers
#10000;
468,7 → 477,7
tdi_pad_i<=#1 instr[i]; // last shift
tms_pad_i<=#1 1; // going out of shiftIR
gen_clk(1);
tdi_pad_i<=#1 'hz; // tri-state
tdi_pad_i<=#1 'hz; // tri-state
gen_clk(1);
tms_pad_i<=#1 0;
gen_clk(1); // we are in RunTestIdle
769,8 → 778,9
task debug_wishbone_go;
input [2:0] command;
input [31:0] crc;
integer i, j;
integer i;
reg [4:0] pointer;
begin
$display("(%0t) Task debug_wishbone_go (previous command was %0s): ", $time, last_wb_cmd_text);
 
791,15 → 801,17
 
if ((last_wb_cmd == `WB_WRITE8) | (last_wb_cmd == `WB_WRITE16) | (last_wb_cmd == `WB_WRITE32)) // When WB_WRITEx was previously activated, data needs to be shifted.
begin
for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.len << 3); i=i+32)
for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.len << 3); i=i+1)
begin
$display("wb_data = 0x%x", wb_data);
for (j=31; j>=0; j=j-1)
if (!(i%32))
begin
tdi_pad_i<=#1 wb_data[j];
gen_clk(1);
wb_data = wb_data + 32'h11111111;
$display("\t\twb_data = 0x%x", wb_data);
end
wb_data = wb_data + 32'h11111111;
pointer = 31-i[4:0];
tdi_pad_i<=#1 wb_data[pointer];
gen_clk(1);
 
end
end
 
810,6 → 822,20
gen_clk(1);
end
 
 
 
 
if ((last_wb_cmd == `WB_READ8) | (last_wb_cmd == `WB_READ16) | (last_wb_cmd == `WB_READ32)) // When WB_WRITEx was previously activated, data needs to be shifted.
begin
$display("\t\tGenerating %0d clocks to read %0d data bytes.", dbg_tb.i_dbg_top.i_dbg_wb.len << 3, dbg_tb.i_dbg_top.i_dbg_wb.len);
for (i=0; i<(dbg_tb.i_dbg_top.i_dbg_wb.len << 3); i=i+1)
begin
tdi_pad_i<=#1 1'hz;
gen_clk(1);
end
end
 
 
gen_clk(`STATUS_LEN); // Generating 4 clocks to read out status.
 
for(i=0; i<`CRC_LEN -1; i=i+1) // Getting in the CRC
839,241 → 865,9
 
 
 
// Reads the CPU register and latches the data so it is ready for reading
task ReadCPURegister;
input [31:0] Address;
input [7:0] crc;
integer i;
begin
$display("(%0t) Task ReadCPURegister", $time);
tms_pad_i<=#1 1;
gen_clk(1);
tms_pad_i<=#1 0;
gen_clk(2); // we are in shiftDR
 
for(i=0; i<32; i=i+1)
begin
tdi_pad_i<=#1 Address[i]; // Shifting address
gen_clk(1);
end
 
tdi_pad_i<=#1 0; // shifting RW bit = read
gen_clk(1);
 
for(i=0; i<32; i=i+1)
begin
tdi_pad_i<=#1 0; // Shifting data. Data is not important in read cycle.
gen_clk(1);
end
 
// for(i=0; i<`CRC_LEN -1; i=i+1)
for(i=0; i<`CRC_LEN; i=i+1) // crc is 9 bit long
begin
tdi_pad_i<=#1 crc[i]; // Shifting CRC.
gen_clk(1);
end
 
// tdi_pad_i<=#1 crc[i]; // Shifting last bit of CRC.
tdi_pad_i<=#1 1'b0; // crc[i]; // Shifting last bit of CRC.
tms_pad_i<=#1 1; // going out of shiftIR
gen_clk(1);
tdi_pad_i<=#1 'hz; // Tristate TDI.
gen_clk(1);
 
tms_pad_i<=#1 0;
gen_clk(1); // we are in RunTestIdle
end
endtask
 
 
// Write the CPU register
task WriteCPURegister;
input [31:0] data;
input [31:0] Address;
input [`CRC_LEN -1:0] crc;
integer i;
begin
$display("(%0t) Task WriteCPURegister", $time);
tms_pad_i<=#1 1;
gen_clk(1);
tms_pad_i<=#1 0;
gen_clk(2); // we are in shiftDR
 
for(i=0; i<32; i=i+1)
begin
tdi_pad_i<=#1 Address[i]; // Shifting address
gen_clk(1);
end
 
tdi_pad_i<=#1 1; // shifting RW bit = write
gen_clk(1);
 
for(i=0; i<32; i=i+1)
begin
tdi_pad_i<=#1 data[i]; // Shifting data
gen_clk(1);
end
 
// for(i=0; i<`CRC_LEN -1; i=i+1)
for(i=0; i<`CRC_LEN; i=i+1) // crc is 9 bit long
begin
tdi_pad_i<=#1 crc[i]; // Shifting CRC
gen_clk(1);
end
 
// tdi_pad_i<=#1 crc[i]; // shifting last bit of CRC
tdi_pad_i<=#1 1'b0; // crc[i]; // shifting last bit of CRC
tms_pad_i<=#1 1; // going out of shiftIR
gen_clk(1);
tdi_pad_i<=#1 'hz; // tristate TDI
gen_clk(1);
 
tms_pad_i<=#1 0;
gen_clk(1); // we are in RunTestIdle
 
gen_clk(10); // Generating few clock cycles needed for the write operation to accomplish
end
endtask
 
 
// Reads the register and latches the data so it is ready for reading
task ReadRegister;
input [4:0] Address;
input [7:0] crc;
integer i;
begin
$display("(%0t) Task ReadRegister", $time);
tms_pad_i<=#1 1;
gen_clk(1);
tms_pad_i<=#1 0;
gen_clk(2); // we are in shiftDR
 
for(i=0; i<5; i=i+1)
begin
tdi_pad_i<=#1 Address[i]; // Shifting address
gen_clk(1);
end
 
tdi_pad_i<=#1 0; // shifting RW bit = read
gen_clk(1);
 
for(i=0; i<32; i=i+1)
begin
tdi_pad_i<=#1 0; // Shifting data. Data is not important in read cycle.
gen_clk(1);
end
 
// for(i=0; i<`CRC_LEN -1; i=i+1)
for(i=0; i<`CRC_LEN; i=i+1) // crc is 9 bit long
begin
tdi_pad_i<=#1 crc[i]; // Shifting CRC. CRC is not important in read cycle.
gen_clk(1);
end
 
// tdi_pad_i<=#1 crc[i]; // Shifting last bit of CRC.
tdi_pad_i<=#1 1'b0; // crc[i]; // Shifting last bit of CRC.
tms_pad_i<=#1 1; // going out of shiftIR
gen_clk(1);
tdi_pad_i<=#1 'hz; // Tri state TDI
gen_clk(1);
tms_pad_i<=#1 0;
gen_clk(1); // we are in RunTestIdle
 
gen_clk(10); // Generating few clock cycles needed for the read operation to accomplish
end
endtask
 
// Write the register
task WriteRegister;
input [31:0] data;
input [4:0] Address;
input [`CRC_LEN -1:0] crc;
integer i;
begin
$display("(%0t) Task WriteRegister", $time);
tms_pad_i<=#1 1;
gen_clk(1);
tms_pad_i<=#1 0;
gen_clk(2); // we are in shiftDR
 
for(i=0; i<5; i=i+1)
begin
tdi_pad_i<=#1 Address[i]; // Shifting address
gen_clk(1);
end
 
tdi_pad_i<=#1 1; // shifting RW bit = write
gen_clk(1);
 
for(i=0; i<32; i=i+1)
begin
tdi_pad_i<=#1 data[i]; // Shifting data
gen_clk(1);
end
// for(i=0; i<`CRC_LEN -1; i=i+1)
for(i=0; i<`CRC_LEN; i=i+1) // crc is 9 bit long
begin
tdi_pad_i<=#1 crc[i]; // Shifting CRC
gen_clk(1);
end
 
// tdi_pad_i<=#1 crc[i]; // Shifting last bit of CRC
tdi_pad_i<=#1 1'b0; // crc[i]; // Shifting last bit of CRC
tms_pad_i<=#1 1; // going out of shiftIR
gen_clk(1);
tdi_pad_i<=#1 'hz; // Tri state TDI
gen_clk(1);
 
tms_pad_i<=#1 0;
gen_clk(1); // we are in RunTestIdle
 
gen_clk(5); // Extra clocks needed for operations to finish
 
end
endtask
 
/*
task EnableWishboneSlave;
begin
$display("(%0t) Task EnableWishboneSlave", $time);
while(1)
begin
@ (posedge Mclk);
if(wb_stb_i & wb_cyc_i) // WB access
// wait (wb_stb_i & wb_cyc_i) // WB access
begin
@ (posedge Mclk);
@ (posedge Mclk);
@ (posedge Mclk);
#1 wb_ack_o = 1;
if(~wb_we_i) // read
wb_dat_o = 32'hbeefdead;
wb_dat_o = {wb_adr_i[3:0], wb_adr_i[7:4], wb_adr_i[11:8], wb_adr_i[15:12],
wb_adr_i[19:16], wb_adr_i[23:20], wb_adr_i[27:24], wb_adr_i[31:28]};
if(wb_we_i & wb_stb_i & wb_cyc_i) // write
$display("\nWISHBONE write data=%0h, Addr=%0h", wb_dat_i, wb_adr_i);
if(~wb_we_i & wb_stb_i & wb_cyc_i) // read
$display("\nWISHBONE read data=%0h, Addr=%0h", wb_dat_o, wb_adr_i);
end
@ (posedge Mclk);
#1 wb_ack_o = 0;
wb_dat_o = 32'h0;
end
 
end
endtask
*/
 
 
 
 
 
/**********************************************************************************
* *
* Printing the information to the screen *
1095,87 → 889,7
end
 
 
// Print selected chain
/*
always @ (posedge tck_pad_i)
begin
if(dbg_tb.i_tap_top.chain_select & dbg_tb.i_dbg_top.update_dr_q)
case(dbg_tb.i_dbg_top.Chain[`CHAIN_ID_LENGTH-1:0])
`GLOBAL_BS_CHAIN : $write("\nChain GLOBAL_BS_CHAIN");
`CPU_DEBUG_CHAIN_0 : $write("\nChain CPU_DEBUG_CHAIN_0");
`CPU_DEBUG_CHAIN_1 : $write("\nChain CPU_DEBUG_CHAIN_1");
`CPU_DEBUG_CHAIN_2 : $write("\nChain CPU_DEBUG_CHAIN_2");
`CPU_DEBUG_CHAIN_3 : $write("\nChain CPU_DEBUG_CHAIN_3");
`CPU_TEST_CHAIN : $write("\nChain CPU_TEST_CHAIN");
`TRACE_TEST_CHAIN : $write("\nChain TRACE_TEST_CHAIN");
`REGISTER_SCAN_CHAIN : $write("\nChain REGISTER_SCAN_CHAIN");
`WISHBONE_SCAN_CHAIN : $write("\nChain WISHBONE_SCAN_CHAIN");
endcase
end
*/
 
// print CPU registers read/write
/*
always @ (posedge Mclk)
begin
if(dbg_tb.i_dbg_top.CPUAccess0 & ~dbg_tb.i_dbg_top.CPUAccess_q & dbg_tb.i_dbg_top.RW)
$write("\n\t\tWrite to CPU Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[31:0], dbg_tb.i_dbg_top.DataOut[31:0]);
else
if(dbg_tb.i_dbg_top.CPUAccess_q & ~dbg_tb.i_dbg_top.CPUAccess_q2 & ~dbg_tb.i_dbg_top.RW)
$write("\n\t\tRead from CPU Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[31:0], dbg_tb.i_dbg_top.cpu_data_i[31:0]);
end
*/
 
// print registers read/write
/*
always @ (posedge Mclk)
begin
if(dbg_tb.i_dbg_top.RegAccess_q & ~dbg_tb.i_dbg_top.RegAccess_q2)
begin
if(dbg_tb.i_dbg_top.RW)
$write("\n\t\tWrite to Register (addr=0x%h, data=0x%h)", dbg_tb.i_dbg_top.ADDR[4:0], dbg_tb.i_dbg_top.DataOut[31:0]);
else
$write("\n\t\tRead from Register (addr=0x%h, data=0x%h). This data will be shifted out on next read request.", dbg_tb.i_dbg_top.ADDR[4:0], dbg_tb.i_dbg_top.RegDataIn[31:0]);
end
end
*/
 
// print CRC error
/*
`ifdef TRACE_ENABLED
wire CRCErrorReport = ~(dbg_tb.i_dbg_top.CrcMatch & (dbg_tb.i_dbg_top.chain_select | dbg_tb.i_dbg_top.debug_select & register_scan_chain | dbg_tb.i_dbg_top.debug_select & (cpu_debug_scan_chain0 | cpu_debug_scan_chain1 | cpu_debug_scan_chain2 | cpu_debug_scan_chain3) | dbg_tb.i_dbg_top.debug_select & dbg_tb.i_dbg_top.TraceTestScanChain | dbg_tb.i_dbg_top.debug_select & wishbone_scan_chain));
`else // TRACE_ENABLED not enabled
wire CRCErrorReport = ~(dbg_tb.i_dbg_top.CrcMatch & (dbg_tb.i_tap_top.chain_select | dbg_tb.i_tap_top.debug_select & register_scan_chain | dbg_tb.i_tap_top.debug_select & (cpu_debug_scan_chain0 | cpu_debug_scan_chain1 | cpu_debug_scan_chain2 | cpu_debug_scan_chain3) | dbg_tb.i_tap_top.debug_select & wishbone_scan_chain));
`endif
*/
 
/*
// print crc
always @ (posedge P_TCK)
begin
if(dbg_tb.i_tap_top.update_dr & ~dbg_tb.i_tap_top.idcode_select)
begin
if(dbg_tb.i_tap_top.chain_select)
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[11:4], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LEN -1:0]);
else
if(register_scan_chain & ~dbg_tb.i_tap_top.chain_select)
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[45:38], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LEN -1:0]);
else
if((cpu_debug_scan_chain0 | cpu_debug_scan_chain1 | cpu_debug_scan_chain2 | cpu_debug_scan_chain3) & ~dbg_tb.i_tap_top.chain_select)
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[72:65], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LEN -1:0]);
if(wishbone_scan_chain & ~dbg_tb.i_tap_top.chain_select)
$write("\t\tCrcIn=0x%h, CrcOut=0x%h", dbg_tb.i_dbg_top.JTAG_DR_IN[72:65], dbg_tb.i_dbg_top.CalculatedCrcOut[`CRC_LEN -1:0]);
 
if(CRCErrorReport)
begin
$write("\n\t\t\t\tCrc Error when receiving data (read or write) !!! CrcIn should be: 0x%h\n", dbg_tb.i_dbg_top.CalculatedCrcIn);
#1000 $stop;
end
$display("\n");
end
end
*/
 
// Print shifted IDCode
reg [31:0] tmp_data;
always @ (posedge tck_pad_i)
1274,10 → 988,51
begin
$display("\t\tCRC ERROR !!!");
$display("\t\tCRC needed (%0s) = 0x%0x , shifted_in = 0x%0x", test_text, tmp_crc, shifted_in_crc);
$stop;
end
end
 
 
 
// Detecting errors in counters
always @ (dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt or
dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt_end or
dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt or
dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_end or
dbg_tb.i_dbg_top.i_dbg_wb.data_cnt or
dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_end or
dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt_en or
dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_en or
dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_en or
dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_en or
dbg_tb.i_dbg_top.i_dbg_wb.status_cnt1
//dbg_tb.i_dbg_top.i_dbg_wb.status_cnt2 or
//dbg_tb.i_dbg_top.i_dbg_wb.status_cnt3 or
//dbg_tb.i_dbg_top.i_dbg_wb.status_cnt4
// dbg_tb.i_dbg_top.i_dbg_wb. or
)
begin
if ((~dbg_tb.i_dbg_top.i_dbg_wb.cmd_cnt_end) & (
dbg_tb.i_dbg_top.i_dbg_wb.addr_len_cnt_en |
dbg_tb.i_dbg_top.i_dbg_wb.data_cnt_en |
dbg_tb.i_dbg_top.i_dbg_wb.crc_cnt_en |
dbg_tb.i_dbg_top.i_dbg_wb.status_cnt1
)
)
begin
$display("\n\n\t\t(%0t) ERROR in counters !!!", $time);
#10000;
$stop;
end
 
 
 
end
 
 
 
 
 
endmodule // dbg_tb
 
 
/trunk/rtl/verilog/dbg_wb_defines.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2004/01/06 17:15:19 mohor
// temp3 version.
//
// Revision 1.1 2003/12/23 15:09:04 mohor
// New directory structure. New version of the debug interface.
//
63,13 → 66,9
 
// Length of status
`define STATUS_LEN 4
`define STATUS_CNT 3
 
 
 
 
 
 
// Enable TRACE
//`define TRACE_ENABLED // Uncomment this define to activate the trace
 
/trunk/rtl/verilog/dbg_wb.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2004/01/07 11:58:56 mohor
// temp4 version.
//
// Revision 1.5 2004/01/06 17:15:19 mohor
// temp3 version.
//
132,29 → 135,32
reg [31:0] wb_dat_o;
reg [3:0] wb_sel_o;
 
reg [3:0] wb_sel_old;
reg tdo_o;
 
reg [50:0] dr;
wire enable;
wire cmd_cnt_en;
reg [1:0] cmd_cnt;
wire cmd_cnt_end;
reg cmd_cnt_end_q;
wire addr_len_cnt_en;
reg [5:0] addr_len_cnt;
reg [5:0] addr_len_cnt_limit;
wire addr_len_cnt_end;
wire crc_cnt_en;
reg [5:0] crc_cnt;
wire crc_cnt_end;
reg crc_cnt_end_q;
wire data_cnt_en;
reg [18:0] data_cnt;
reg [18:0] data_cnt_limit;
wire data_cnt_end;
reg data_cnt_end_q;
reg status_reset_en;
 
reg crc_match_reg;
 
reg [`STATUS_CNT -1:0] status_cnt;
// reg [31:0] data_tck;
 
 
reg [2:0] cmd, cmd_old;
reg [31:0] adr;
reg [15:0] len;
167,36 → 173,66
reg start_wb_wr;
reg start_wb_wr_q;
 
reg cmd_write;
reg cmd_read;
reg cmd_go;
reg dr_write_latched;
reg dr_read_latched;
reg dr_go_latched;
 
wire status_cnt_end;
 
wire byte, half, long;
reg byte_q, half_q, long_q;
//wire previous_cmd_read;
wire previous_cmd_write;
wire cmd_read;
wire cmd_write;
wire cmd_go;
wire cmd_old_read;
 
reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;
 
 
assign enable = wishbone_ce_i & shift_dr_i;
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end); // igor !!! Add something so CRC is calculated when data is read from WB
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
 
 
//always @ (posedge tck_i)
//begin
// if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
// dr <= #1 {dr[49:0], tdi_i};
//end
 
 
always @ (posedge tck_i)
begin
if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
/* if (cmd_old_read & cmd_go)
begin
case (cmd_old) // synthesis parallel_case full_case
`WB_READ8 : begin
if(byte & (~byte_q))
dr[31:24] <= #1 input_data[]; mama
else
dr <= #1 dr<<1;
end
`WB_READ16: begin
if(half & (~half_q))
start_rd_tck <= #1 1'b1;
else
start_rd_tck <= #1 1'b0;
end
`WB_READ32: begin
if(long & (~long_q))
start_rd_tck <= #1 1'b1;
else
start_rd_tck <= #1 1'b0;
end
endcase
end
else*/ if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
dr <= #1 {dr[49:0], tdi_i};
end
 
 
//always @ (posedge tck_i)
//begin
// if (enable & (data_cnt_end)) // Igor !!! perhaps not needed data_cnt_end
// data_tck <= #1 {data_tck[30:0], tdi_i};
//end
assign cmd_cnt_en = enable & (~cmd_cnt_end);
 
 
always @ (posedge tck_i or posedge trst_i)
begin
if (trst_i)
203,11 → 239,13
cmd_cnt <= #1 'h0;
else if (update_dr_i)
cmd_cnt <= #1 'h0;
else if (enable & (~cmd_cnt_end))
else if (cmd_cnt_en)
cmd_cnt <= #1 cmd_cnt + 1'b1;
end
 
 
assign addr_len_cnt_en = enable & cmd_cnt_end & (~addr_len_cnt_end);
 
always @ (posedge tck_i or posedge trst_i)
begin
if (trst_i)
214,11 → 252,13
addr_len_cnt <= #1 'h0;
else if (update_dr_i)
addr_len_cnt <= #1 'h0;
else if (enable & cmd_cnt_end & (~addr_len_cnt_end))
else if (addr_len_cnt_en)
addr_len_cnt <= #1 addr_len_cnt + 1'b1;
end
 
 
assign data_cnt_en = enable & cmd_cnt_end & (~data_cnt_end);
 
always @ (posedge tck_i or posedge trst_i)
begin
if (trst_i)
225,8 → 265,7
data_cnt <= #1 'h0;
else if (update_dr_i)
data_cnt <= #1 'h0;
// else if (enable & cmd_cnt_end & (~data_cnt_end)) // igor !!! add something that will count output data
else if (enable & (~data_cnt_end) & cmd_go & ((cmd_cnt_end & previous_cmd_write | crc_cnt_end & cmd_read)))
else if (data_cnt_en)
data_cnt <= #1 data_cnt + 1'b1;
end
 
246,9 → 285,12
 
 
 
//assign previous_cmd_read = (cmd == `WB_READ8) | (cmd == `WB_READ16) | (cmd == `WB_READ32);
assign previous_cmd_write = (cmd == `WB_WRITE8) | (cmd == `WB_WRITE16) | (cmd == `WB_WRITE32);
assign cmd_read = (cmd == `WB_READ8) | (cmd == `WB_READ16) | (cmd == `WB_READ32);
assign cmd_write = (cmd == `WB_WRITE8) | (cmd == `WB_WRITE16) | (cmd == `WB_WRITE32);
assign cmd_go = cmd == `WB_GO;
assign cmd_old_read = (cmd_old == `WB_READ8) | (cmd_old == `WB_READ16) | (cmd_old == `WB_READ32);
 
 
wire dr_read;
wire dr_write;
wire dr_go;
263,9 → 305,9
always @ (posedge tck_i)
begin
if (update_dr_i)
cmd_read <= #1 1'b0;
dr_read_latched <= #1 1'b0;
else if (cmd_cnt_end & (~cmd_cnt_end_q))
cmd_read <= #1 dr_read;
dr_read_latched <= #1 dr_read;
end
 
 
272,9 → 314,9
always @ (posedge tck_i)
begin
if (update_dr_i)
cmd_write <= #1 1'b0;
dr_write_latched <= #1 1'b0;
else if (cmd_cnt_end & (~cmd_cnt_end_q))
cmd_write <= #1 dr_write;
dr_write_latched <= #1 dr_write;
end
 
 
281,51 → 323,53
always @ (posedge tck_i)
begin
if (update_dr_i)
cmd_go <= #1 1'b0;
dr_go_latched <= #1 1'b0;
else if (cmd_cnt_end & (~cmd_cnt_end_q))
cmd_go <= #1 dr_go;
dr_go_latched <= #1 dr_go;
end
 
 
 
always @ (cmd_cnt_end or cmd_cnt_end_q or dr)
always @ (posedge tck_i)
begin
if (cmd_cnt_end & (~cmd_cnt_end_q))
if (cmd_cnt == 2'h2)
begin
// (current command is WB_STATUS or WB_GO)
if (dr_status | dr_go)
if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO)
addr_len_cnt_limit = 6'd0;
// (current command is WB_WRITEx or WB_READx)
else
else // (current command is WB_WRITEx or WB_READx)
addr_len_cnt_limit = 6'd48;
end
end
 
 
always @ (cmd_cnt_end or cmd_cnt_end_q or dr or previous_cmd_write or len)
always @ (posedge tck_i)
begin
if (cmd_cnt_end & (~cmd_cnt_end_q))
if (cmd_cnt == 2'h2)
begin
// (current command is WB_GO and previous command is WB_WRITEx)
if (dr_go & previous_cmd_write)
if (dr[1] & (~dr[0]) & (~tdi_i) & cmd_write) // current command is WB_GO and previous command is WB_WRITEx)
data_cnt_limit = (len<<3);
else
data_cnt_limit = 19'h0;
end
else if (crc_cnt == 6'd31)
begin
if (dr_go_latched & cmd_read) // current command is WB_GO and previous command is WB_READx)
data_cnt_limit = (len<<3);
else
data_cnt_limit = 19'h0;
end
end
 
 
assign crc_cnt_en = enable & cmd_cnt_end & addr_len_cnt_end & data_cnt_end & (~crc_cnt_end);
 
// crc counter
always @ (posedge tck_i or posedge trst_i)
begin
if (trst_i)
crc_cnt <= #1 'h0;
// else if(enable & addr_len_cnt_end & (~crc_cnt_end))
else if(enable & cmd_cnt_end & addr_len_cnt_end & data_cnt_end & (~crc_cnt_end))
else if(crc_cnt_en)
crc_cnt <= #1 crc_cnt + 1'b1;
else if (update_dr_i)
crc_cnt <= #1 'h0;
332,7 → 376,6
end
 
assign cmd_cnt_end = cmd_cnt == 2'h3;
//assign addr_len_cnt_end = addr_len_cnt == 6'd48;
assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;
assign crc_cnt_end = crc_cnt == 6'd32;
assign data_cnt_end = (data_cnt == data_cnt_limit);
339,24 → 382,54
 
always @ (posedge tck_i)
begin
crc_cnt_end_q <= #1 crc_cnt_end;
cmd_cnt_end_q <= #1 cmd_cnt_end;
crc_cnt_end_q <= #1 crc_cnt_end;
cmd_cnt_end_q <= #1 cmd_cnt_end;
data_cnt_end_q <= #1 data_cnt_end;
end
 
// status counter
 
 
always @ (posedge tck_i or posedge trst_i)
begin
if (trst_i)
status_cnt <= #1 'h0;
else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
status_cnt <= #1 status_cnt + 1'b1;
status_cnt1 <= #1 1'b0;
else if (update_dr_i)
status_cnt <= #1 'h0;
status_cnt1 <= #1 1'b0;
else if (data_cnt_end & (~data_cnt_end_q) & cmd_old_read & dr_go_latched |
crc_cnt_end & (~crc_cnt_end_q) & (~(cmd_read & dr_go_latched)) // cmd is not changed, yet.
)
status_cnt1 <= #1 1'b1;
end
 
assign status_cnt_end = status_cnt == `STATUS_LEN;
 
always @ (posedge tck_i or posedge trst_i)
begin
if (trst_i)
begin
status_cnt2 <= #1 1'b0;
status_cnt3 <= #1 1'b0;
status_cnt4 <= #1 1'b0;
end
else if (update_dr_i)
begin
status_cnt2 <= #1 1'b0;
status_cnt3 <= #1 1'b0;
status_cnt4 <= #1 1'b0;
end
else
begin
status_cnt2 <= #1 status_cnt1;
status_cnt3 <= #1 status_cnt2;
status_cnt4 <= #1 status_cnt3;
end
end
 
 
 
 
assign status_cnt_end = status_cnt4;
reg [`STATUS_LEN -1:0] status;
//reg address_unaligned;
 
reg wb_error, wb_error_sync, wb_error_tck;
reg wb_overrun, wb_overrun_sync, wb_overrun_tck;
371,12 → 444,16
reg busy_sync;
reg [799:0] TDO_WISHBONE;
 
 
 
always @ (posedge tck_i or posedge trst_i)
begin
if (trst_i)
status <= #1 'h0;
else if(crc_cnt_end & (~crc_cnt_end_q))
else if(crc_cnt_end & (~crc_cnt_end_q) & (~dr_read_latched))
status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,
else if (data_cnt_end & (~data_cnt_end_q) & dr_read_latched)
status <= #1 {crc_match_reg, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,
else if (shift_dr_i & (~status_cnt_end))
status <= #1 {status[0], status[`STATUS_LEN -1:1]};
end
388,7 → 465,7
 
 
 
always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck)
always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck or cmd_read or data_cnt_end or data_cnt_end_q or crc_match_reg or dr_read_latched)
begin
if (pause_dr_i)
begin
395,13 → 472,18
tdo_o = busy_tck;
TDO_WISHBONE = "busy_tck";
end
else if (crc_cnt_end & (~crc_cnt_end_q))
else if (crc_cnt_end & (~crc_cnt_end_q) & (~(dr_go_latched & cmd_read))) // cmd is updated not updated, yet
begin
tdo_o = crc_match_i;
TDO_WISHBONE = "crc_match_i";
end
else if (crc_cnt_end)
else if (data_cnt_end & (~data_cnt_end_q) & dr_go_latched & cmd_old_read) // cmd is already updated
begin
tdo_o = crc_match_reg;
TDO_WISHBONE = "crc_match_reg";
end
else if (crc_cnt_end & (~(dr_go_latched & cmd_old_read)) | data_cnt_end & dr_go_latched & cmd_old_read) // cmd is already updated
begin
tdo_o = status[0];
TDO_WISHBONE = "status";
end
417,21 → 499,40
 
always @ (posedge tck_i)
begin
if(crc_cnt_end & (~crc_cnt_end_q))
crc_match_reg <= #1 crc_match_i;
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
if (trst_i)
begin
cmd <= #1 'h0;
cmd_old <= #1 'h0;
end
else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
begin
if (dr_write_latched | dr_read_latched)
cmd <= #1 dr[50:48];
else
cmd <= #1 dr[2:0];
 
cmd_old <= #1 cmd;
end
end
 
 
always @ (posedge tck_i)
begin
if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
begin
if (cmd_write | cmd_read)
if (dr_write_latched | dr_read_latched)
begin
cmd <= #1 dr[50:48];
adr <= #1 dr[47:16];
len <= #1 dr[15:0];
set_addr <= #1 1'b1;
end
else
begin
cmd <= #1 dr[2:0];
end
 
cmd_old <= #1 cmd;
end
else
set_addr <= #1 1'b0;
441,8 → 542,31
// Start wishbone read cycle
always @ (posedge tck_i)
begin
if (set_addr & cmd_read)
if (set_addr & dr_read_latched)
start_rd_tck <= #1 1'b1;
else if (cmd_old_read & cmd_go & crc_cnt_end_q & (~data_cnt_end))
begin
case (cmd_old) // synthesis parallel_case full_case
`WB_READ8 : begin
if(byte & (~byte_q))
start_rd_tck <= #1 1'b1;
else
start_rd_tck <= #1 1'b0;
end
`WB_READ16: begin
if(half & (~half_q))
start_rd_tck <= #1 1'b1;
else
start_rd_tck <= #1 1'b0;
end
`WB_READ32: begin
if(long & (~long_q))
start_rd_tck <= #1 1'b1;
else
start_rd_tck <= #1 1'b0;
end
endcase
end
else
start_rd_tck <= #1 1'b0;
end
452,7 → 576,7
// Start wishbone write cycle
always @ (posedge tck_i)
begin
if (cmd_go & previous_cmd_write)
if (dr_go_latched & cmd_write)
begin
case (cmd) // synthesis parallel_case full_case
`WB_WRITE8 : begin
538,21 → 662,11
end
end
 
`define WB_STATUS 3'h0 // igor !!! Delete this lines
`define WB_WRITE8 3'h1 // igor !!! Delete this lines
`define WB_WRITE16 3'h2 // igor !!! Delete this lines
`define WB_WRITE32 3'h3 // igor !!! Delete this lines
`define WB_GO 3'h4 // igor !!! Delete this lines
`define WB_READ8 3'h5 // igor !!! Delete this lines
`define WB_READ16 3'h6 // igor !!! Delete this lines
`define WB_READ32 3'h7 // igor !!! Delete this lines
 
 
 
 
 
 
 
// adr byte | short | long
// 0 1000 1100 1111
// 1 0100 err err
576,43 → 690,15
end
 
 
 
 
/*
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
wb_dat_o[31:0] <= #1 32'h0;
else if (start_wb_wr & (~start_wb_wr_q))
begin
if (cmd[1:0] == 2'd1) // 8-bit access
wb_dat_o[31:0] <= #1 {4{8'h0}};
else if (cmd[1:0] == 2'd2) // 16-bit access
wb_dat_o[31:0] <= #1 {2{16'h0}};
else
wb_dat_o[31:0] <= #1 32'h0; //32-bit access
end
wb_sel_old <= #1 4'h0;
else if (wb_ack_i)
wb_sel_old <= #1 wb_sel_o;
end
*/
 
//always @ (wb_adr_o or cmd)
//begin
// wb_sel_o[0] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
// (cmd[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
// wb_sel_o[1] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1] ^ cmd[0]) & (wb_adr_o[1:0] == 2'b10);
// wb_sel_o[2] = (cmd[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
// wb_sel_o[3] = (wb_adr_o[1:0] == 2'b00);
//end
 
 
 
// always @ (dr)
// begin
// address_unaligned = (dr[1:0] == 2'b11) & (dr[4:3] > 2'b00) | (dr[1:0] == 2'b10) & (dr[3]);
// end
 
 
assign wb_we_o = ~cmd[2]; // Status or write (for simpler logic status is allowed)
assign wb_cab_o = 1'b0;
assign wb_stb_o = wb_cyc_o;

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