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Rev 894 → Rev 895

/trunk/or1200/rtl/verilog/or1200_du.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/03/14 00:30:24 lampret
// Added alternative for critical path in DU.
//
// Revision 1.5 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
94,9 → 97,11
module or1200_du(
// RISC Internal Interface
clk, rst,
dcpu_cycstb_i, dcpu_we_i,
icpu_cycstb_i, ex_freeze, branch_op, ex_insn, du_dsr,
du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write, du_except,
dcpu_cycstb_i, dcpu_we_i, icpu_cycstb_i,
ex_freeze, branch_op, ex_insn,
spr_dat_npc, rf_dataw,
du_dsr, du_stall, du_addr, du_dat_i, du_dat_o,
du_read, du_write, du_except,
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
 
// External Debug Interface
122,6 → 127,8
input ex_freeze; // EX stage freeze
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch op
input [dw-1:0] ex_insn; // EX insn
input [31:0] spr_dat_npc; // Next PC (for trace)
input [31:0] rf_dataw; // ALU result (for trace)
output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR
output du_stall; // Debug Unit Stall
output [aw-1:0] du_addr; // Debug Unit Address
156,7 → 163,20
//
`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
assign dbg_lss_o = 4'b0000;
 
reg [1:0] dbg_is_o;
//
// Show insn activity (temp, must be removed)
//
always @(posedge clk or posedge rst)
if (rst)
dbg_is_o <= #1 2'b00;
else if (!ex_freeze &
~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
dbg_is_o <= #1 ~dbg_is_o;
`ifdef UNUSED
assign dbg_is_o = 2'b00;
`endif
`else
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
assign dbg_is_o = {1'b0, icpu_cycstb_i};
220,18 → 240,27
reg [31:0] spr_dat_o;
`endif
reg [13:0] except_stop; // Exceptions that stop because of DSR
`ifdef OR1200_DU_TB_IMPLEMENTED
wire tb_enw;
reg [7:0] tb_wadr;
reg [31:0] tb_timstmp;
`endif
wire [31:0] tbia_dat_o;
wire [31:0] tbim_dat_o;
wire [31:0] tbar_dat_o;
wire [31:0] tbts_dat_o;
 
//
// DU registers address decoder
//
`ifdef OR1200_DU_DMR1
assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DMR1));
assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DMR1));
`endif
`ifdef OR1200_DU_DSR
assign dsr_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DSR));
assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DSR));
`endif
`ifdef OR1200_DU_DRR
assign drr_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DRR));
assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DRR));
`endif
 
//
353,8 → 382,9
// Read DU registers
//
`ifdef OR1200_DU_READREGS
always @(spr_addr or dsr or drr or dmr1 or dmr2)
case (spr_addr[`OR1200_SPR_OFS_BITS])
always @(spr_addr or dsr or drr or dmr1 or dmr2 or
tbia_dat_o or tbim_dat_o or tbar_dat_o or tb_wadr)
casex (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
`ifdef OR1200_DU_DMR1
`OR1200_DU_OFS_DMR1:
spr_dat_o = {8'b0, dmr1, 22'b0};
371,6 → 401,18
`OR1200_DU_OFS_DRR:
spr_dat_o = {18'b0, drr};
`endif
`ifdef OR1200_DU_TB_IMPLEMENTED
`OR1200_DU_OFS_TBADR:
spr_dat_o = {24'h000000, tb_wadr};
`OR1200_DU_OFS_TBIA:
spr_dat_o = tbia_dat_o;
`OR1200_DU_OFS_TBIM:
spr_dat_o = tbim_dat_o;
`OR1200_DU_OFS_TBAR:
spr_dat_o = tbar_dat_o;
`OR1200_DU_OFS_TBTS:
spr_dat_o = tbts_dat_o;
`endif
default:
spr_dat_o = 32'h0000_0000;
endcase
381,8 → 423,195
//
assign du_dsr = dsr;
 
`ifdef OR1200_DU_TB_IMPLEMENTED
//
// Simple trace buffer
// (right now hardcoded for Xilinx Virtex FPGAs)
//
// Stores last 256 instruction addresses, instruction
// machine words and ALU results
//
 
//
// Trace buffer write enable
//
assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);
 
//
// Trace buffer write address pointer
//
always @(posedge clk or posedge rst)
if (rst)
tb_wadr <= #1 8'h00;
else if (tb_enw)
tb_wadr <= #1 tb_wadr + 8'd1;
 
//
// Free running counter (time stamp)
//
always @(posedge clk or posedge rst)
if (rst)
tb_timstmp <= #1 32'h00000000;
else if (!dbg_bp_r)
tb_timstmp <= #1 tb_timstmp + 32'd1;
 
//
// Trace buffer RAMs
//
RAMB4_S16_S16 tbia_ramb4_s16_0(
.CLKA(clk),
.RSTA(rst),
.ADDRA(tb_wadr),
.DIA(spr_dat_npc[15:0]),
.ENA(1'b1),
.WEA(tb_enw),
.DOA(),
 
.CLKB(clk),
.RSTB(rst),
.ADDRB(spr_addr[7:0]),
.DIB(16'h0000),
.ENB(1'b1),
.WEB(1'b0),
.DOB(tbia_dat_o[15:0])
);
 
RAMB4_S16_S16 tbia_ramb4_s16_1(
.CLKA(clk),
.RSTA(rst),
.ADDRA(tb_wadr),
.DIA(spr_dat_npc[31:16]),
.ENA(1'b1),
.WEA(tb_enw),
.DOA(),
 
.CLKB(clk),
.RSTB(rst),
.ADDRB(spr_addr[7:0]),
.DIB(16'h0000),
.ENB(1'b1),
.WEB(1'b0),
.DOB(tbia_dat_o[31:16])
);
 
RAMB4_S16_S16 tbim_ramb4_s16_0(
.CLKA(clk),
.RSTA(rst),
.ADDRA(tb_wadr),
.DIA(ex_insn[15:0]),
.ENA(1'b1),
.WEA(tb_enw),
.DOA(),
 
.CLKB(clk),
.RSTB(rst),
.ADDRB(spr_addr[7:0]),
.DIB(16'h0000),
.ENB(1'b1),
.WEB(1'b0),
.DOB(tbim_dat_o[15:0])
);
 
RAMB4_S16_S16 tbim_ramb4_s16_1(
.CLKA(clk),
.RSTA(rst),
.ADDRA(tb_wadr),
.DIA(ex_insn[31:16]),
.ENA(1'b1),
.WEA(tb_enw),
.DOA(),
 
.CLKB(clk),
.RSTB(rst),
.ADDRB(spr_addr[7:0]),
.DIB(16'h0000),
.ENB(1'b1),
.WEB(1'b0),
.DOB(tbim_dat_o[31:16])
);
 
RAMB4_S16_S16 tbar_ramb4_s16_0(
.CLKA(clk),
.RSTA(rst),
.ADDRA(tb_wadr),
.DIA(rf_dataw[15:0]),
.ENA(1'b1),
.WEA(tb_enw),
.DOA(),
 
.CLKB(clk),
.RSTB(rst),
.ADDRB(spr_addr[7:0]),
.DIB(16'h0000),
.ENB(1'b1),
.WEB(1'b0),
.DOB(tbar_dat_o[15:0])
);
 
RAMB4_S16_S16 tbar_ramb4_s16_1(
.CLKA(clk),
.RSTA(rst),
.ADDRA(tb_wadr),
.DIA(rf_dataw[31:16]),
.ENA(1'b1),
.WEA(tb_enw),
.DOA(),
 
.CLKB(clk),
.RSTB(rst),
.ADDRB(spr_addr[7:0]),
.DIB(16'h0000),
.ENB(1'b1),
.WEB(1'b0),
.DOB(tbar_dat_o[31:16])
);
 
RAMB4_S16_S16 tbts_ramb4_s16_0(
.CLKA(clk),
.RSTA(rst),
.ADDRA(tb_wadr),
.DIA(tb_timstmp[15:0]),
.ENA(1'b1),
.WEA(tb_enw),
.DOA(),
 
.CLKB(clk),
.RSTB(rst),
.ADDRB(spr_addr[7:0]),
.DIB(16'h0000),
.ENB(1'b1),
.WEB(1'b0),
.DOB(tbts_dat_o[15:0])
);
 
RAMB4_S16_S16 tbts_ramb4_s16_1(
.CLKA(clk),
.RSTA(rst),
.ADDRA(tb_wadr),
.DIA(tb_timstmp[31:16]),
.ENA(1'b1),
.WEA(tb_enw),
.DOA(),
 
.CLKB(clk),
.RSTB(rst),
.ADDRB(spr_addr[7:0]),
.DIB(16'h0000),
.ENB(1'b1),
.WEB(1'b0),
.DOB(tbts_dat_o[31:16])
);
 
`else
assign tbia_dat_o = 32'h0000_0000;
assign tbim_dat_o = 32'h0000_0000;
assign tbar_dat_o = 32'h0000_0000;
assign tbts_dat_o = 32'h0000_0000;
 
`endif // OR1200_DU_TB_IMPLEMENTED
 
`else // OR1200_DU_IMPLEMENTED
 
//
// When DU is not implemented, drive all outputs as would when DU is disabled
//
/trunk/or1200/rtl/verilog/or1200_defines.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.15 2002/06/08 16:20:21 lampret
// Added defines for enabling generic FF based memory macro for register file.
//
// Revision 1.14 2002/03/29 16:24:06 lampret
// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives
//
231,6 → 234,7
//
`define OR1200_XILINX_RAMB4
//`define OR1200_XILINX_RAM32X1D
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
 
//
// Do not implement Data cache
288,6 → 292,13
//
 
//
// Disable bursts if they are not supported by the
// memory subsystem (only affect cache line fill)
//
//`define OR1200_NO_BURSTS
//
 
//
// Enable additional synthesis directives if using
// _Synopsys_ synthesis tool
//
858,14 → 869,23
// Define it if you want DU implemented
`define OR1200_DU_IMPLEMENTED
 
// Define if you want trace buffer
// (for now only available for Xilinx Virtex FPGAs)
`define OR1200_DU_TB_IMPLEMENTED
 
// Address offsets of DU registers inside DU group
`define OR1200_DU_OFS_DMR1 5'd16
`define OR1200_DU_OFS_DMR2 5'd17
`define OR1200_DU_OFS_DSR 5'd20
`define OR1200_DU_OFS_DRR 5'd21
`define OR1200_DU_OFS_DMR1 11'd16
`define OR1200_DU_OFS_DMR2 11'd17
`define OR1200_DU_OFS_DSR 11'd20
`define OR1200_DU_OFS_DRR 11'd21
`define OR1200_DU_OFS_TBADR 11'h00ff
`define OR1200_DU_OFS_TBIA 11'h01xx
`define OR1200_DU_OFS_TBIM 11'h02xx
`define OR1200_DU_OFS_TBAR 11'h03xx
`define OR1200_DU_OFS_TBTS 11'h10xx
 
// Position of offset bits inside SPR address
`define OR1200_DUOFS_BITS 4:0
`define OR1200_DUOFS_BITS 10:0
 
// Define if you want these DU registers to be implemented
`define OR1200_DU_DMR1
/trunk/or1200/rtl/verilog/or1200_freeze.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.3 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
98,7 → 101,8
multicycle, flushpipe, extend_flush, lsu_stall, if_stall,
lsu_unstall, du_stall, mac_stall,
force_dslot_fetch, abort_ex,
genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze
genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze,
icpu_ack_i, icpu_err_i
);
 
//
121,6 → 125,8
output id_freeze;
output ex_freeze;
output wb_freeze;
input icpu_ack_i;
input icpu_err_i;
 
//
// Internal wires and regs
127,6 → 133,7
//
wire multicycle_freeze;
reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle_cnt;
reg flushpipe_r;
 
//
// Pipeline freeze
141,7 → 148,7
// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.
// This way NOP is asserted from stage ID into EX stage.
//
assign genpc_freeze = du_stall | flushpipe;
assign genpc_freeze = du_stall | flushpipe_r;
assign if_freeze = id_freeze | extend_flush;
//assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~flushpipe | du_stall;
assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) | du_stall;
150,6 → 157,18
assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) | du_stall | mac_stall | abort_ex;
 
//
// registered flushpipe
//
always @(posedge clk or posedge rst)
if (rst)
flushpipe_r <= #1 1'b0;
else if (icpu_ack_i | icpu_err_i)
// else if (!if_stall)
flushpipe_r <= #1 flushpipe;
else if (!flushpipe)
flushpipe_r <= #1 1'b0;
//
// Multicycle freeze
//
assign multicycle_freeze = |multicycle_cnt;
/trunk/or1200/rtl/verilog/or1200_cpu.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2002/03/29 16:29:37 lampret
// Fixed some ports in instnatiations that were removed from the modules
//
// Revision 1.8 2002/03/29 15:16:54 lampret
// Some of the warnings fixed.
//
136,6 → 139,7
 
// Debug unit
ex_insn, ex_freeze, branch_op,
spr_dat_npc, rf_dataw,
du_stall, du_addr, du_dat_du, du_read, du_write, du_dsr, du_except, du_dat_cpu,
// Data interface
191,6 → 195,7
output [31:0] ex_insn;
output ex_freeze;
output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
 
input du_stall;
input [dw-1:0] du_addr;
input [dw-1:0] du_dat_du;
199,6 → 204,7
input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
output [12:0] du_except;
output [dw-1:0] du_dat_cpu;
output [dw-1:0] rf_dataw;
 
//
// Data (DC) interface
233,6 → 239,7
input [dw-1:0] spr_dat_du;
output [dw-1:0] spr_addr;
output [dw-1:0] spr_dat_cpu;
output [dw-1:0] spr_dat_npc;
output [31:0] spr_cs;
output spr_we;
 
662,7 → 669,9
.if_freeze(if_freeze),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
.wb_freeze(wb_freeze)
.wb_freeze(wb_freeze),
.icpu_ack_i(icpu_ack_i),
.icpu_err_i(icpu_err_i)
);
 
//
685,6 → 694,11
.sig_immufault(except_immufault),
.sig_tick(sig_tick),
.branch_taken(branch_taken),
.icpu_ack_i(icpu_ack_i),
.icpu_err_i(icpu_err_i),
.dcpu_ack_i(dcpu_ack_i),
.dcpu_err_i(dcpu_err_i),
.genpc_freeze(genpc_freeze),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
.wb_freeze(wb_freeze),
/trunk/or1200/rtl/verilog/or1200_except.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.8 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
130,11 → 133,11
// Internal i/f
sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,
branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze, if_stall,
if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
except_started, except_stop, ex_void,
spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
esr, sr, lsu_addr, abort_ex
esr, sr, lsu_addr, abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i
);
 
//
156,6 → 159,7
input sig_immufault;
input sig_tick;
input branch_taken;
input genpc_freeze;
input id_freeze;
input ex_freeze;
input wb_freeze;
183,6 → 187,10
output [31:0] spr_dat_ppc;
output [31:0] spr_dat_npc;
output abort_ex;
input icpu_ack_i;
input icpu_err_i;
input dcpu_ack_i;
input dcpu_err_i;
 
//
// Internal regs and wires
502,7 → 510,8
esr <= #1 {1'b1, datain[`OR1200_SR_WIDTH-2:0]};
end
`OR1200_EXCEPTFSM_FLU1:
// if (!if_stall & !id_freeze)
if (icpu_ack_i | icpu_err_i | genpc_freeze)
// if (!if_stall | genpc_freeze)
state <= #1 `OR1200_EXCEPTFSM_FLU2;
`OR1200_EXCEPTFSM_FLU2:
if (except_type == `OR1200_EXCEPT_TRAP) begin
/trunk/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
64,7 → 67,341
`include "or1200_defines.v"
 
`ifdef OR1200_XILINX_RAM32X1D
`ifdef OR1200_USE_RAM16X1D_FOR_RAM32X1D
module or1200_xcv_ram32x8d
(
DPO,
SPO,
A,
D,
DPRA,
WCLK,
WE
);
output [7:0] DPO;
output [7:0] SPO;
input [4:0] A;
input [4:0] DPRA;
input [7:0] D;
input WCLK;
input WE;
 
wire [7:0] DPO_0;
wire [7:0] SPO_0;
 
wire [7:0] DPO_1;
wire [7:0] SPO_1;
 
wire WE_0 ;
wire WE_1 ;
 
assign DPO = DPRA[4] ? DPO_1 : DPO_0 ;
assign SPO = A[4] ? SPO_1 : SPO_0 ;
 
assign WE_0 = !A[4] && WE ;
assign WE_1 = A[4] && WE ;
 
RAM16X1D ram32x1d_0_0(
.DPO(DPO_0[0]),
.SPO(SPO_0[0]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[0]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_0)
);
 
//
// Instantiation of block 1
//
RAM16X1D ram32x1d_0_1(
.DPO(DPO_0[1]),
.SPO(SPO_0[1]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[1]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_0)
);
 
//
// Instantiation of block 2
//
RAM16X1D ram32x1d_0_2(
.DPO(DPO_0[2]),
.SPO(SPO_0[2]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[2]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_0)
);
 
//
// Instantiation of block 3
//
RAM16X1D ram32x1d_0_3(
.DPO(DPO_0[3]),
.SPO(SPO_0[3]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[3]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_0)
);
 
//
// Instantiation of block 4
//
RAM16X1D ram32x1d_0_4(
.DPO(DPO_0[4]),
.SPO(SPO_0[4]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[4]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_0)
);
 
//
// Instantiation of block 5
//
RAM16X1D ram32x1d_0_5(
.DPO(DPO_0[5]),
.SPO(SPO_0[5]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[5]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_0)
);
 
//
// Instantiation of block 6
//
RAM16X1D ram32x1d_0_6(
.DPO(DPO_0[6]),
.SPO(SPO_0[6]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[6]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_0)
);
 
//
// Instantiation of block 7
//
RAM16X1D ram32x1d_0_7(
.DPO(DPO_0[7]),
.SPO(SPO_0[7]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[7]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_0)
);
 
RAM16X1D ram32x1d_1_0(
.DPO(DPO_1[0]),
.SPO(SPO_1[0]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[0]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_1)
);
 
//
// Instantiation of block 1
//
RAM16X1D ram32x1d_1_1(
.DPO(DPO_1[1]),
.SPO(SPO_1[1]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[1]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_1)
);
 
//
// Instantiation of block 2
//
RAM16X1D ram32x1d_1_2(
.DPO(DPO_1[2]),
.SPO(SPO_1[2]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[2]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_1)
);
 
//
// Instantiation of block 3
//
RAM16X1D ram32x1d_1_3(
.DPO(DPO_1[3]),
.SPO(SPO_1[3]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[3]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_1)
);
 
//
// Instantiation of block 4
//
RAM16X1D ram32x1d_1_4(
.DPO(DPO_1[4]),
.SPO(SPO_1[4]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[4]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_1)
);
 
//
// Instantiation of block 5
//
RAM16X1D ram32x1d_1_5(
.DPO(DPO_1[5]),
.SPO(SPO_1[5]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[5]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_1)
);
 
//
// Instantiation of block 6
//
RAM16X1D ram32x1d_1_6(
.DPO(DPO_1[6]),
.SPO(SPO_1[6]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[6]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_1)
);
 
//
// Instantiation of block 7
//
RAM16X1D ram32x1d_1_7(
.DPO(DPO_1[7]),
.SPO(SPO_1[7]),
.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.D(D[7]),
.DPRA0(DPRA[0]),
.DPRA1(DPRA[1]),
.DPRA2(DPRA[2]),
.DPRA3(DPRA[3]),
.WCLK(WCLK),
.WE(WE_1)
);
endmodule
 
`else
 
module or1200_xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);
 
//
247,5 → 584,5
);
 
endmodule
 
`endif
`endif
/trunk/or1200/rtl/verilog/or1200_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.5 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
335,7 → 338,10
wire ex_freeze;
wire [31:0] ex_insn;
wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
wire [31:0] spr_dat_npc;
wire [31:0] rf_dataw;
 
 
//
// Instantiation of Instruction WISHBONE BIU
//
515,7 → 521,9
.du_dsr(du_dsr),
.du_except(du_except),
.du_dat_cpu(du_dat_cpu),
.rf_dataw(rf_dataw),
 
 
// Connection IMMU and CPU internally
.immu_en(immu_en),
 
550,6 → 558,7
.spr_dat_dmmu(spr_dat_dmmu),
.spr_dat_immu(spr_dat_immu),
.spr_dat_du(spr_dat_du),
.spr_dat_npc(spr_dat_npc),
.spr_cs(spr_cs),
.spr_we(spr_we)
);
642,6 → 651,10
.ex_insn(ex_insn),
.du_dsr(du_dsr),
 
// For Trace buffer
.spr_dat_npc(spr_dat_npc),
.rf_dataw(rf_dataw),
 
// DU's access to SPR unit
.du_stall(du_stall),
.du_addr(du_addr),
/trunk/or1200/rtl/verilog/or1200_wb_biu.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.12 2001/11/22 13:42:51 lampret
// Added wb_cyc_o assignment after it was removed by accident.
//
274,10 → 277,18
if (wb_rst_i)
wb_cyc_o <= #1 1'b0;
else
`ifdef OR1200_NO_BURSTS
wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i;
`else
wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i | biu_cab_i;
`endif
`else
`ifdef OR1200_NO_BURSTS
assign wb_cyc_o = biu_cyc_i;
`else
assign wb_cyc_o = biu_cyc_i | biu_cab_i;
`endif
`endif
 
//
// WB stb_o

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