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funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/doc/ref_doc.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/pkt_codec_mk2.1.0.xml =================================================================== --- funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/pkt_codec_mk2.1.0.xml (revision 90) +++ funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/pkt_codec_mk2.1.0.xml (nonexistent) @@ -1,10 +0,0 @@ - - - - TUT - ip.hwp.communication - pkt_codec_mk2 - 1.0 - true - true - Index: funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/addr_gen.vhd =================================================================== --- funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/addr_gen.vhd (revision 90) +++ funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/addr_gen.vhd (nonexistent) @@ -1,179 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Address generator for pkt_codec --- Project : -------------------------------------------------------------------------------- --- File : addr_gen.vhd --- Author : Lasse Lehtonen --- Company : --- Created : 2011-10-12 --- Last update: 2011-10-25 --- Platform : --- Standard : VHDL'87 -------------------------------------------------------------------------------- --- Description: --- Handles address flit repeating when data comes slowly from IP and --- prevents sending only address flits without at least on data flit. --- -------------------------------------------------------------------------------- --- Copyright (c) 2011 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2011-10-12 1.0 lehton87 Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -entity addr_gen is - - generic ( - cmd_width_g : positive; - data_width_g : positive; - addr_flit_en_g : natural); - - port ( - clk : in std_logic; - rst_n : in std_logic; - -- from IP side - ip_cmd_in : in std_logic_vector(cmd_width_g-1 downto 0); - ip_data_in : in std_logic_vector(data_width_g-1 downto 0); - ip_stall_out : out std_logic; - orig_addr_in : in std_logic_vector(data_width_g-1 downto 0); - -- to NET - net_cmd_out : out std_logic_vector(cmd_width_g-1 downto 0); - net_data_out : out std_logic_vector(data_width_g-1 downto 0); - net_stall_in : in std_logic); - -end addr_gen; - -architecture rtl of addr_gen is - - signal cmd_r : std_logic_vector(cmd_width_g-1 downto 0); - signal data_r : std_logic_vector(data_width_g-1 downto 0); - signal addr_r : std_logic_vector(data_width_g-1 downto 0); - signal stall_r : std_logic; - signal first_data_r : std_logic; - - type state_type is (idle, addr, orig, data); - signal state_r : state_type; - -begin -- rtl - - ip_stall_out <= net_stall_in or stall_r; - - fsm_p : process (clk, rst_n) - begin -- process fsm_p - if rst_n = '0' then -- asynchronous reset (active low) - state_r <= idle; - cmd_r <= (others => '0'); - data_r <= (others => '0'); - addr_r <= (others => '0'); - stall_r <= '0'; - first_data_r <= '0'; - net_cmd_out <= (others => '0'); - net_data_out <= (others => '0'); - elsif clk'event and clk = '1' then -- rising clock edge - - -- default - if net_stall_in = '0' then - stall_r <= '0'; - end if; - - case state_r is - ----------------------------------------------------------------------- - -- IDLE - ----------------------------------------------------------------------- - when idle => - if net_stall_in = '0' then - if ip_cmd_in = "00" then - net_cmd_out <= "00"; - first_data_r <= '0'; - elsif ip_cmd_in = "01" then - net_cmd_out <= "00"; - first_data_r <= '1'; - addr_r <= ip_data_in; - state_r <= addr; - else - first_data_r <= '1'; - data_r <= ip_data_in; - net_cmd_out <= "01"; - net_data_out <= addr_r; - state_r <= data; - end if; - end if; - - --------------------------------------------------------------------- - -- ADDR - --------------------------------------------------------------------- - when addr => - if net_stall_in = '0' then - if ip_cmd_in = "00" then - state_r <= idle; - net_cmd_out <= "00"; - first_data_r <= '0'; - elsif ip_cmd_in = "01" then - addr_r <= ip_data_in; - state_r <= addr; - net_cmd_out <= "00"; - first_data_r <= '1'; - else - net_cmd_out <= "01"; - net_data_out <= addr_r; - data_r <= ip_data_in; - state_r <= data; - end if; - end if; - - --------------------------------------------------------------------- - -- DATA - --------------------------------------------------------------------- - when data => - if net_stall_in = '0' then - if ip_cmd_in = "00" then - if first_data_r = '1' and addr_flit_en_g = 1 then - stall_r <= '1'; - net_cmd_out <= "10"; - net_data_out <= orig_addr_in; - first_data_r <= '0'; - else - net_data_out <= data_r; - net_cmd_out <= "10"; - state_r <= idle; - end if; - elsif ip_cmd_in = "01" then - if first_data_r = '1' and addr_flit_en_g = 1 then - stall_r <= '1'; - net_cmd_out <= "10"; - net_data_out <= orig_addr_in; - first_data_r <= '0'; - else - net_data_out <= data_r; - net_cmd_out <= "10"; - addr_r <= ip_data_in; - state_r <= addr; - first_data_r <= '1'; -- ase 25-10-2011 - end if; - else - if first_data_r = '1' and addr_flit_en_g = 1 then - stall_r <= '1'; - net_cmd_out <= "10"; - net_data_out <= orig_addr_in; - first_data_r <= '0'; - else - net_data_out <= data_r; - net_cmd_out <= "10"; - data_r <= ip_data_in; - end if; - end if; - end if; - - when others => null; - end case; - - - end if; - end process fsm_p; - -end rtl; Index: funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/log2_pkg.vhd =================================================================== --- funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/log2_pkg.vhd (revision 90) +++ funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/log2_pkg.vhd (nonexistent) @@ -1,62 +0,0 @@ -------------------------------------------------------------------------------- --- Title : log2_ceil function --- Project : -------------------------------------------------------------------------------- --- File : log2_pkg.vhdl --- Author : Lasse Lehtonen --- Company : --- Created : 2010-06-16 --- Last update: 2011-10-07 --- Platform : --- Standard : VHDL'93 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- --- Copyright (c) 2010 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2010-06-16 1.0 ase Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -------------------------------------------------------------------------------- --- PACKAGE DECLARATION -------------------------------------------------------------------------------- - -package log2_pkg is - - ----------------------------------------------------------------------------- - -- HELPER FUNCTIONS - ----------------------------------------------------------------------------- - - -- purpose: Return ceiling log 2 of n - function log2_ceil ( - constant n : positive) - return positive; - -end package log2_pkg; - - -------------------------------------------------------------------------------- --- PACKAGE BODY -------------------------------------------------------------------------------- - -package body log2_pkg is - - -- purpose: Return ceiling log 2 of n - function log2_ceil ( - constant n : positive) - return positive is - variable retval : positive := 1; - begin -- function log2_ceil - while 2**retval < n loop - retval := retval + 1; - end loop; - return retval; - end function log2_ceil; - -end package body log2_pkg; Index: funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/addr_rip.vhd =================================================================== --- funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/addr_rip.vhd (revision 90) +++ funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/addr_rip.vhd (nonexistent) @@ -1,118 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Address flit ripper / replacer --- Project : -------------------------------------------------------------------------------- --- File : addr_rip.vhd --- Author : Lasse Lehtonen --- Company : --- Created : 2011-10-12 --- Last update: 2011-10-25 --- Platform : --- Standard : VHDL'87 -------------------------------------------------------------------------------- --- Description: --- --- Rips the address flit when wanted or replaces the network address --- with original address (or doesn't do a thing). --- -------------------------------------------------------------------------------- --- Copyright (c) 2011 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2011-10-12 1.0 lehton87 Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - -entity addr_rip is - - generic ( - cmd_width_g : positive; - data_width_g : positive; - addr_flit_en_g : natural; - rip_addr_g : natural); - - port ( - clk : in std_logic; - rst_n : in std_logic; - net_cmd_in : in std_logic_vector(cmd_width_g-1 downto 0); - net_data_in : in std_logic_vector(data_width_g-1 downto 0); - net_stall_out : out std_logic; - ip_cmd_out : out std_logic_vector(cmd_width_g-1 downto 0); - ip_data_out : out std_logic_vector(data_width_g-1 downto 0); - ip_stall_in : in std_logic); - -end addr_rip; - - -architecture rtl of addr_rip is - - signal was_addr_r : std_logic; - -begin -- rtl - - addr_check_p : process (clk, rst_n) - begin -- process addr_check_p - if rst_n = '0' then -- asynchronous reset (active low) - was_addr_r <= '0'; - elsif clk'event and clk = '1' then -- rising clock edge - if net_cmd_in = "01" then - was_addr_r <= '1'; - else - was_addr_r <= '0'; - end if; - end if; - end process addr_check_p; - - ip_data_out <= net_data_in; - net_stall_out <= ip_stall_in; - - rip : if rip_addr_g = 1 generate - replace : if addr_flit_en_g = 1 generate - m1 : process (net_cmd_in, was_addr_r) - begin -- process m - if net_cmd_in = "01" then - ip_cmd_out <= "00"; - elsif was_addr_r = '1' then - ip_cmd_out <= "01"; - else - ip_cmd_out <= net_cmd_in; - end if; - end process m1; - end generate replace; - - dont_replace : if addr_flit_en_g = 0 generate - m2: process (net_cmd_in) - begin -- process m2 - if net_cmd_in = "01" then - ip_cmd_out <= "00"; - else - ip_cmd_out <= net_cmd_in; - end if; - end process m2; - end generate dont_replace; - end generate rip; - - dont_rip : if rip_addr_g = 0 generate - replace1 : if addr_flit_en_g = 1 generate - m3 : process (net_cmd_in, was_addr_r) - begin -- process m - if net_cmd_in = "01" then - ip_cmd_out <= "00"; - elsif was_addr_r = '1' then - ip_cmd_out <= "01"; - else - ip_cmd_out <= net_cmd_in; - end if; - end process m3; - end generate replace1; - - dont_replace1 : if addr_flit_en_g = 0 generate - ip_cmd_out <= net_cmd_in; - end generate dont_replace1; - end generate dont_rip; - -end rtl; Index: funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/pkt_codec_mk2.vhd =================================================================== --- funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/pkt_codec_mk2.vhd (revision 90) +++ funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/pkt_codec_mk2.vhd (nonexistent) @@ -1,215 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Packet Codec MK2 --- Project : -------------------------------------------------------------------------------- --- File : pkt_codec_mk2.vhd --- Author : Lasse Lehtonen --- Company : --- Created : 2011-01-12 --- Last update: 2011-10-24 --- Platform : --- Standard : VHDL'93 -------------------------------------------------------------------------------- --- Description: --- --- Generics --- --- address_mode_g 0 : IP gives raw network address --- address_mode_g 1 : IP gives integer ID numbers as target address --- address_mode_g 2 : IP gives memory mapped addresses --- --- clock_mode_g 0 : Use one clock for both ip and the net --- (clk_ip must be same as clk_net) --- clock_mode_g 1 : Use two asynchronous clocks --- --- noc_type_g 0 : ase_noc --- noc_type_g 1 : ase_mesh1 --- -------------------------------------------------------------------------------- --- Copyright (c) 2011 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2011-01-12 1.0 ase Created -------------------------------------------------------------------------------- - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.ase_noc_pkg.all; -use work.ase_mesh1_pkg.all; - -entity pkt_codec_mk2 is - - generic ( - my_id_g : natural; - data_width_g : positive; - cmd_width_g : positive; - agents_g : positive; - cols_g : positive; - rows_g : positive; - agent_ports_g : positive; - addr_flit_en_g : natural; - address_mode_g : natural; - clock_mode_g : natural; - rip_addr_g : natural; - noc_type_g : natural); - - port ( - clk_ip : in std_logic; - clk_net : in std_logic; - rst_n : in std_logic; - - -- IP read interface - ip_cmd_out : out std_logic_vector(cmd_width_g-1 downto 0); - ip_data_out : out std_logic_vector(data_width_g-1 downto 0); - ip_stall_in : in std_logic; - - -- IP write interface - ip_cmd_in : in std_logic_vector(cmd_width_g-1 downto 0); - ip_data_in : in std_logic_vector(data_width_g-1 downto 0); - ip_stall_out : out std_logic; - - -- NoC write interface - net_cmd_out : out std_logic_vector(cmd_width_g-1 downto 0); - net_data_out : out std_logic_vector(data_width_g-1 downto 0); - net_stall_in : in std_logic; - - -- NoC read interface - net_cmd_in : in std_logic_vector(cmd_width_g-1 downto 0); - net_data_in : in std_logic_vector(data_width_g-1 downto 0); - net_stall_out : out std_logic - ); - -end entity pkt_codec_mk2; - - - -architecture rtl of pkt_codec_mk2 is - - ----------------------------------------------------------------------------- - -- SIGNALS - ----------------------------------------------------------------------------- - - -- from ip to net path - -- cdc -> at - signal net_cmd_from_cdc : std_logic_vector(cmd_width_g-1 downto 0); - signal net_data_from_cdc : std_logic_vector(data_width_g-1 downto 0); - signal net_stall_to_cdc : std_logic; - -- at -> ag - signal net_cmd_from_at : std_logic_vector(cmd_width_g-1 downto 0); - signal net_data_from_at : std_logic_vector(data_width_g-1 downto 0); - signal net_stall_to_at : std_logic; - signal orig_addr_from_at : std_logic_vector(data_width_g-1 downto 0); - - -- from net to ip path - -- ar -> cdc - signal ip_cmd_from_ar : std_logic_vector(cmd_width_g-1 downto 0); - signal ip_data_from_ar : std_logic_vector(data_width_g-1 downto 0); - signal ip_stall_to_ar : std_logic; - - -------------------------------------------------------------------------------- -begin -- architecture rtl -------------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- CLOCK DOMAIN CROSSING - ----------------------------------------------------------------------------- - - cdc_1 : entity work.cdc - generic map ( - cmd_width_g => cmd_width_g, - data_width_g => data_width_g, - clock_mode_g => clock_mode_g) - port map ( - clk_ip => clk_ip, - clk_net => clk_net, - rst_n => rst_n, - ip_cmd_out => ip_cmd_out, - ip_data_out => ip_data_out, - ip_stall_in => ip_stall_in, - ip_cmd_in => ip_cmd_in, - ip_data_in => ip_data_in, - ip_stall_out => ip_stall_out, - net_cmd_out => net_cmd_from_cdc, - net_data_out => net_data_from_cdc, - net_stall_in => net_stall_to_cdc, - net_cmd_in => ip_cmd_from_ar, - net_data_in => ip_data_from_ar, - net_stall_out => ip_stall_to_ar); - - ----------------------------------------------------------------------------- - -- ADDRESS TRANSLATION (only from IP to NET) - ----------------------------------------------------------------------------- - - addr_translation_1 : entity work.addr_translation - generic map ( - my_id_g => my_id_g, - cmd_width_g => cmd_width_g, - data_width_g => data_width_g, - address_mode_g => address_mode_g, - cols_g => cols_g, - rows_g => rows_g, - agents_g => agents_g, - agent_ports_g => agent_ports_g, - addr_flit_en_g => addr_flit_en_g, - noc_type_g => noc_type_g) - port map ( - clk => clk_net, - rst_n => rst_n, - ip_cmd_in => net_cmd_from_cdc, - ip_data_in => net_data_from_cdc, - ip_stall_out => net_stall_to_cdc, - net_cmd_out => net_cmd_from_at, - net_data_out => net_data_from_at, - net_stall_in => net_stall_to_at, - orig_addr_out => orig_addr_from_at); - - - ----------------------------------------------------------------------------- - -- ADDRESS GENERATOR (only from IP to NET) - ----------------------------------------------------------------------------- - - addr_gen_1 : entity work.addr_gen - generic map ( - cmd_width_g => cmd_width_g, - data_width_g => data_width_g, - addr_flit_en_g => addr_flit_en_g) - port map ( - clk => clk_net, - rst_n => rst_n, - ip_cmd_in => net_cmd_from_at, - ip_data_in => net_data_from_at, - ip_stall_out => net_stall_to_at, - orig_addr_in => orig_addr_from_at, - net_cmd_out => net_cmd_out, - net_data_out => net_data_out, - net_stall_in => net_stall_in - ); - - - ----------------------------------------------------------------------------- - -- ADDRESS RIPPER / REPLACER (only from NET to IP) - ----------------------------------------------------------------------------- - - addr_rip_1 : entity work.addr_rip - generic map ( - cmd_width_g => cmd_width_g, - data_width_g => data_width_g, - addr_flit_en_g => addr_flit_en_g, - rip_addr_g => rip_addr_g) - port map ( - clk => clk_net, - rst_n => rst_n, - net_cmd_in => net_cmd_in, - net_data_in => net_data_in, - net_stall_out => net_stall_out, - ip_cmd_out => ip_cmd_from_ar, - ip_data_out => ip_data_from_ar, - ip_stall_in => ip_stall_to_ar); - -end architecture rtl; Index: funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/ase_mesh1_pkg.vhd =================================================================== --- funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/ase_mesh1_pkg.vhd (revision 90) +++ funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/ase_mesh1_pkg.vhd (nonexistent) @@ -1,166 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Functions for ase_mesh1 and wrappers using it --- Project : -------------------------------------------------------------------------------- --- File : ase_mesh1_pkg.vhdl --- Author : Lasse Lehtonen --- Company : --- Created : 2010-06-16 --- Last update: 2011-11-09 --- Platform : --- Standard : VHDL'93 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- --- Copyright (c) 2010 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2010-06-16 1.0 ase Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.log2_pkg.all; - -------------------------------------------------------------------------------- --- PACKAGE DECLARATION -------------------------------------------------------------------------------- - -package ase_mesh1_pkg is - - ----------------------------------------------------------------------------- - -- HELPER FUCTIONS - ----------------------------------------------------------------------------- - - -- Returns target address (ase_mesh1 network address) - pure function ase_mesh1_address ( - src_id : in integer; -- Source agent id number - dst_id : in integer; -- Destination agent id number - rows : in positive; - cols : in positive; - bus_width : in positive) - return std_logic_vector; - -end package ase_mesh1_pkg; - -------------------------------------------------------------------------------- --- PACKAGE BODY -------------------------------------------------------------------------------- - -package body ase_mesh1_pkg is - - pure function ase_mesh1_address ( - constant src_id : in integer; -- Source agent id number - constant dst_id : in integer; -- Destination agent id number - constant rows : in positive; - constant cols : in positive; - constant bus_width : in positive) - return std_logic_vector is - variable retval : std_logic_vector(bus_width-1 downto 0); - variable lr_bit : std_logic; - variable here_bit : std_logic; - variable first_dir : std_logic_vector(1 downto 0); - variable src_row : integer; - variable src_col : integer; - variable dst_row : integer; - variable dst_col : integer; - constant mesh1_row_width_c : positive := log2_ceil(rows - 1); - constant mesh1_col_width_c : positive := log2_ceil(cols - 1); - constant mesh1_port_width_c : positive := - bus_width - mesh1_row_width_c - mesh1_col_width_c - 4; - variable dst_port : integer := 0; - begin - - retval := (others => '0'); - lr_bit := '0'; - here_bit := '0'; - first_dir := "00"; - src_row := (src_id / cols); - src_col := src_id - (src_row * cols); - dst_row := (dst_id / cols); - dst_col := dst_id - (dst_row * cols); - --- if src_id = 7 and dst_id = 4 then --- report "srow " & integer'image(src_row) & ", drow " --- & integer'image(dst_row) & ", scol " --- & integer'image(src_col) & ", dcol " --- & integer'image(dst_col) & ", cols " --- & integer'image(cols) & ", rows " --- & integer'image(rows) --- severity note; --- end if; - - retval(bus_width-1 downto bus_width-mesh1_port_width_c) := - std_logic_vector(to_unsigned(dst_port, mesh1_port_width_c)); - - if src_row = dst_row then - if src_col = dst_col then - - elsif src_col < dst_col then - first_dir := "01"; - retval(mesh1_row_width_c+mesh1_col_width_c-1 downto mesh1_row_width_c) - := std_logic_vector - (to_unsigned - ((2**mesh1_col_width_c)-(dst_col-src_col), mesh1_col_width_c)); - else - first_dir := "11"; - retval(mesh1_row_width_c+mesh1_col_width_c-1 downto mesh1_row_width_c) - := std_logic_vector - (to_unsigned - ((2**mesh1_col_width_c)-(src_col-dst_col), mesh1_col_width_c)); - end if; - elsif src_row < dst_row then - first_dir := "10"; - retval(mesh1_row_width_c-1 downto 0) := - std_logic_vector - (to_unsigned - ((2**mesh1_row_width_c)-(dst_row-src_row), mesh1_row_width_c)); - if src_col = dst_col then - here_bit := '1'; - elsif src_col < dst_col then - retval(mesh1_row_width_c+mesh1_col_width_c-1 downto mesh1_row_width_c) - := std_logic_vector - (to_unsigned - ((2**mesh1_col_width_c)-(dst_col-src_col), mesh1_col_width_c)); - else - lr_bit := '1'; - retval(mesh1_row_width_c+mesh1_col_width_c-1 downto mesh1_row_width_c) - := std_logic_vector - (to_unsigned - ((2**mesh1_col_width_c)-(src_col-dst_col), mesh1_col_width_c)); - end if; - else - first_dir := "00"; - retval(mesh1_row_width_c-1 downto 0) := - std_logic_vector - (to_unsigned - ((2**mesh1_row_width_c)-(src_row-dst_row), mesh1_row_width_c)); - if src_col = dst_col then - here_bit := '1'; - elsif src_col < dst_col then - retval(mesh1_row_width_c+mesh1_col_width_c-1 downto mesh1_row_width_c) - := std_logic_vector - (to_unsigned - ((2**mesh1_col_width_c)-(dst_col-src_col), mesh1_col_width_c)); - else - lr_bit := '1'; - retval(mesh1_row_width_c+mesh1_col_width_c-1 downto mesh1_row_width_c) - := std_logic_vector - (to_unsigned - ((2**mesh1_col_width_c)-(src_col-dst_col), mesh1_col_width_c)); - end if; - end if; - - retval(mesh1_row_width_c+mesh1_col_width_c+0) := lr_bit; - retval(mesh1_row_width_c+mesh1_col_width_c+1) := here_bit; - retval(mesh1_row_width_c+mesh1_col_width_c+2) := first_dir(0); - retval(mesh1_row_width_c+mesh1_col_width_c+3) := first_dir(1); - - return retval; - end function ase_mesh1_address; - - -end package body ase_mesh1_pkg; Index: funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/ase_noc_pkg.vhd =================================================================== --- funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/ase_noc_pkg.vhd (revision 90) +++ funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/ase_noc_pkg.vhd (nonexistent) @@ -1,414 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Mesh configuration package --- Project : -------------------------------------------------------------------------------- --- File : ase_noc_pkg.vhd --- Author : Lasse Lehtonen --- Company : --- Created : 2011-01-18 --- Last update: 2011-11-08 --- Platform : --- Standard : VHDL'93 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- --- Copyright (c) 2011 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2011-01-18 1.0 lehton87 Created -------------------------------------------------------------------------------- - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.log2_pkg.all; - -package ase_noc_pkg is - - -- Commands - constant mesh_cmd_idle_c : std_logic_vector(1 downto 0) := "00"; - constant mesh_cmd_addr_c : std_logic_vector(1 downto 0) := "01"; - constant mesh_cmd_data_c : std_logic_vector(1 downto 0) := "10"; - constant mesh_cmd_empty_c : std_logic_vector(1 downto 0) := "11"; - - -- Helper functions - function ase_noc_address ( - constant own_id : in natural; - constant target_id : in natural; - constant mesh_cols_c : in positive; - constant mesh_rows_c : in positive; - constant mesh_agent_ports_c : in positive; - constant mesh_data_width_c : in positive) - return std_logic_vector; - - function ase_noc_address_s ( - constant own_id : in natural; - signal target_id : in integer; - constant mesh_cols_c : in positive; - constant mesh_rows_c : in positive; - constant mesh_agent_ports_c : in positive; - constant mesh_data_width_c : in positive) - return std_logic_vector; - -end package ase_noc_pkg; - - - - -package body ase_noc_pkg is - - - function ase_noc_address ( - constant own_id : in natural; - constant target_id : in natural; - constant mesh_cols_c : in positive; - constant mesh_rows_c : in positive; - constant mesh_agent_ports_c : in positive; - constant mesh_data_width_c : in positive) - return std_logic_vector is - variable ret : std_logic_vector(mesh_data_width_c-1 downto 0); - variable src_row : natural range 0 to mesh_rows_c-1; - variable src_col : natural range 0 to mesh_cols_c-1; - variable dst_row : natural range 0 to mesh_rows_c-1; - variable dst_col : natural range 0 to mesh_cols_c-1; - variable col_dif : integer range -mesh_cols_c/2-1 to mesh_cols_c/2+1; - variable row_dif : integer range -mesh_rows_c/2-1 to mesh_rows_c/2+1; - variable dst_port : natural range 4 to 4+mesh_agent_ports_c-1; - constant mesh_port_width_c : natural := log2_ceil(4+mesh_agent_ports_c); - constant mesh_ids_c : natural := - mesh_rows_c*mesh_cols_c*mesh_agent_ports_c; - constant mesh_col_add_c : natural := log2_ceil(mesh_cols_c-1); - constant mesh_row_add_c : natural := log2_ceil(mesh_rows_c-1); - begin -- function mesh_address - - ret := (others => '0'); - src_row := (own_id / (mesh_cols_c * mesh_agent_ports_c)); - src_col := own_id - (src_row * (mesh_cols_c * mesh_agent_ports_c)); - dst_row := (target_id / (mesh_cols_c * mesh_agent_ports_c)); - dst_col := target_id - (dst_row * (mesh_cols_c * mesh_agent_ports_c)); - col_dif := dst_col - src_col; - row_dif := dst_row - src_row; - dst_port := target_id - (dst_row*mesh_cols_c+dst_col)*mesh_agent_ports_c+4; - - if src_row = dst_row then - - if src_col = dst_col then - - ret(mesh_port_width_c-1 downto 0) := - std_logic_vector(to_unsigned(dst_port, mesh_port_width_c)); - - elsif src_col < dst_col then - - ret(mesh_port_width_c-1 downto 0) := - std_logic_vector(to_unsigned(1, mesh_port_width_c)); - ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) := - std_logic_vector(to_unsigned(2**mesh_col_add_c-col_dif, - mesh_col_add_c)); - ret(mesh_port_width_c+mesh_col_add_c+mesh_port_width_c-1 downto - mesh_col_add_c+mesh_port_width_c) := - std_logic_vector(to_unsigned(dst_port, mesh_port_width_c)); - - else - - ret(mesh_port_width_c-1 downto 0) := - std_logic_vector(to_unsigned(3, mesh_port_width_c)); - ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) := - std_logic_vector(to_unsigned(2**mesh_col_add_c+col_dif, - mesh_col_add_c)); - ret(mesh_port_width_c+mesh_col_add_c+mesh_port_width_c-1 downto - mesh_col_add_c+mesh_port_width_c) := - std_logic_vector(to_unsigned(dst_port, mesh_port_width_c)); - - end if; - - elsif src_row < dst_row then - - if src_col = dst_col then - - ret(mesh_port_width_c-1 downto 0) := - std_logic_vector(to_unsigned(2, mesh_port_width_c)); - ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) := - std_logic_vector(to_unsigned(2**mesh_row_add_c-row_dif, - mesh_row_add_c)); - ret(mesh_port_width_c+mesh_row_add_c+mesh_port_width_c-1 downto - mesh_row_add_c+mesh_port_width_c) := - std_logic_vector(to_unsigned(dst_port, mesh_port_width_c)); - - elsif src_col < dst_col then - - ret(mesh_port_width_c-1 downto 0) := - std_logic_vector(to_unsigned(2, mesh_port_width_c)); - ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) := - std_logic_vector(to_unsigned(2**mesh_row_add_c-row_dif, - mesh_row_add_c)); - ret(mesh_row_add_c+mesh_port_width_c*2-1 downto - mesh_row_add_c+mesh_port_width_c) := - std_logic_vector(to_unsigned(1, mesh_port_width_c)); - ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto - mesh_port_width_c*2+mesh_row_add_c) := - std_logic_vector(to_unsigned(2**mesh_col_add_c-col_dif, - mesh_col_add_c)); - ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto - mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) := - std_logic_vector(to_unsigned(dst_port, mesh_port_width_c)); - - else - - ret(mesh_port_width_c-1 downto 0) := - std_logic_vector(to_unsigned(2, mesh_port_width_c)); - ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) := - std_logic_vector(to_unsigned(2**mesh_row_add_c-row_dif, - mesh_row_add_c)); - ret(mesh_row_add_c+mesh_port_width_c*2-1 downto - mesh_row_add_c+mesh_port_width_c) := - std_logic_vector(to_unsigned(3, mesh_port_width_c)); - ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto - mesh_port_width_c*2+mesh_row_add_c) := - std_logic_vector(to_unsigned(2**mesh_col_add_c+col_dif, - mesh_col_add_c)); - ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto - mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) := - std_logic_vector(to_unsigned(dst_port, mesh_port_width_c)); - - end if; - - else - - if src_col = dst_col then - - ret(mesh_port_width_c-1 downto 0) := - std_logic_vector(to_unsigned(0, mesh_port_width_c)); - ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) := - std_logic_vector(to_unsigned(2**mesh_row_add_c+row_dif, - mesh_row_add_c)); - ret(mesh_port_width_c+mesh_row_add_c+mesh_port_width_c-1 downto - mesh_row_add_c+mesh_port_width_c) := - std_logic_vector(to_unsigned(dst_port, mesh_port_width_c)); - - elsif src_col < dst_col then - - ret(mesh_port_width_c-1 downto 0) := - std_logic_vector(to_unsigned(0, mesh_port_width_c)); - ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) := - std_logic_vector(to_unsigned(2**mesh_row_add_c+row_dif, - mesh_row_add_c)); - ret(mesh_row_add_c+mesh_port_width_c*2-1 downto - mesh_row_add_c+mesh_port_width_c) := - std_logic_vector(to_unsigned(1, mesh_port_width_c)); - ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto - mesh_port_width_c*2+mesh_row_add_c) := - std_logic_vector(to_unsigned(2**mesh_col_add_c-col_dif, - mesh_col_add_c)); - ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto - mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) := - std_logic_vector(to_unsigned(dst_port, mesh_port_width_c)); - - else - - ret(mesh_port_width_c-1 downto 0) := - std_logic_vector(to_unsigned(0, mesh_port_width_c)); - ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) := - std_logic_vector(to_unsigned(2**mesh_row_add_c+row_dif, - mesh_row_add_c)); - ret(mesh_row_add_c+mesh_port_width_c*2-1 downto - mesh_row_add_c+mesh_port_width_c) := - std_logic_vector(to_unsigned(3, mesh_port_width_c)); - ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto - mesh_port_width_c*2+mesh_row_add_c) := - std_logic_vector(to_unsigned(2**mesh_col_add_c+col_dif, - mesh_col_add_c)); - ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto - mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) := - std_logic_vector(to_unsigned(dst_port, mesh_port_width_c)); - - end if; - - end if; - - report "From " & integer'image(own_id) & " to " & integer'image(target_id) - & " gives " & integer'image(to_integer(unsigned(ret))) severity note; - report "col_add " & integer'image(mesh_col_add_c) - & ", row_add " & integer'image(mesh_row_add_c) - & ", port_w " & integer'image(mesh_port_width_c) severity note; - - return ret; - - end function ase_noc_address; - - - function ase_noc_address_s ( - constant own_id : in natural; - signal target_id : in integer; - constant mesh_cols_c : in positive; - constant mesh_rows_c : in positive; - constant mesh_agent_ports_c : in positive; - constant mesh_data_width_c : in positive) - return std_logic_vector is - variable ret : std_logic_vector(mesh_data_width_c-1 downto 0); - variable src_row : natural range 0 to mesh_rows_c-1; - variable src_col : natural range 0 to mesh_cols_c-1; - variable dst_row : natural range 0 to mesh_rows_c-1; - variable dst_col : natural range 0 to mesh_cols_c-1; - variable col_dif : integer range -mesh_cols_c/2-1 to mesh_cols_c/2+1; - variable row_dif : integer range -mesh_rows_c/2-1 to mesh_rows_c/2+1; - variable dst_port : natural range 4 to 4+mesh_agent_ports_c-1; - constant mesh_port_width_c : natural := log2_ceil(4+mesh_agent_ports_c); - constant mesh_ids_c : natural := - mesh_rows_c*mesh_cols_c*mesh_agent_ports_c; - constant mesh_col_add_c : natural := log2_ceil(mesh_cols_c-1); - constant mesh_row_add_c : natural := log2_ceil(mesh_rows_c-1); - begin -- function mesh_address - - ret := (others => '0'); - src_row := (own_id / (mesh_cols_c * mesh_agent_ports_c)); - src_col := own_id - (src_row * (mesh_cols_c * mesh_agent_ports_c)); - dst_row := (target_id / (mesh_cols_c * mesh_agent_ports_c)); - dst_col := target_id - (dst_row * (mesh_cols_c * mesh_agent_ports_c)); - col_dif := dst_col - src_col; - row_dif := dst_row - src_row; - dst_port := target_id - (dst_row*mesh_cols_c+dst_col)*mesh_agent_ports_c+4; - - if src_row = dst_row then - - if src_col = dst_col then - - ret(mesh_port_width_c-1 downto 0) := - std_logic_vector(to_unsigned(dst_port, mesh_port_width_c)); - - elsif src_col < dst_col then - - ret(mesh_port_width_c-1 downto 0) := - std_logic_vector(to_unsigned(1, mesh_port_width_c)); - ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) := - std_logic_vector(to_unsigned(2**mesh_col_add_c-col_dif, - mesh_col_add_c)); - ret(mesh_port_width_c+mesh_col_add_c+mesh_port_width_c-1 downto - mesh_col_add_c+mesh_port_width_c) := - std_logic_vector(to_unsigned(dst_port, mesh_port_width_c)); - - else - - ret(mesh_port_width_c-1 downto 0) := - std_logic_vector(to_unsigned(3, mesh_port_width_c)); - ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) := - std_logic_vector(to_unsigned(2**mesh_col_add_c+col_dif, - mesh_col_add_c)); - ret(mesh_port_width_c+mesh_col_add_c+mesh_port_width_c-1 downto - mesh_col_add_c+mesh_port_width_c) := - std_logic_vector(to_unsigned(dst_port, mesh_port_width_c)); - - end if; - - elsif src_row < dst_row then - - if src_col = dst_col then - - ret(mesh_port_width_c-1 downto 0) := - std_logic_vector(to_unsigned(2, mesh_port_width_c)); - ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) := - std_logic_vector(to_unsigned(2**mesh_row_add_c-row_dif, - mesh_row_add_c)); - ret(mesh_port_width_c+mesh_row_add_c+mesh_port_width_c-1 downto - mesh_row_add_c+mesh_port_width_c) := - std_logic_vector(to_unsigned(dst_port, mesh_port_width_c)); - - elsif src_col < dst_col then - - ret(mesh_port_width_c-1 downto 0) := - std_logic_vector(to_unsigned(2, mesh_port_width_c)); - ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) := - std_logic_vector(to_unsigned(2**mesh_row_add_c-row_dif, - mesh_row_add_c)); - ret(mesh_row_add_c+mesh_port_width_c*2-1 downto - mesh_row_add_c+mesh_port_width_c) := - std_logic_vector(to_unsigned(1, mesh_port_width_c)); - ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto - mesh_port_width_c*2+mesh_row_add_c) := - std_logic_vector(to_unsigned(2**mesh_col_add_c-col_dif, - mesh_col_add_c)); - ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto - mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) := - std_logic_vector(to_unsigned(dst_port, mesh_port_width_c)); - - else - - ret(mesh_port_width_c-1 downto 0) := - std_logic_vector(to_unsigned(2, mesh_port_width_c)); - ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) := - std_logic_vector(to_unsigned(2**mesh_row_add_c-row_dif, - mesh_row_add_c)); - ret(mesh_row_add_c+mesh_port_width_c*2-1 downto - mesh_row_add_c+mesh_port_width_c) := - std_logic_vector(to_unsigned(3, mesh_port_width_c)); - ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto - mesh_port_width_c*2+mesh_row_add_c) := - std_logic_vector(to_unsigned(2**mesh_col_add_c+col_dif, - mesh_col_add_c)); - ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto - mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) := - std_logic_vector(to_unsigned(dst_port, mesh_port_width_c)); - - end if; - - else - - if src_col = dst_col then - - ret(mesh_port_width_c-1 downto 0) := - std_logic_vector(to_unsigned(0, mesh_port_width_c)); - ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) := - std_logic_vector(to_unsigned(2**mesh_row_add_c+row_dif, - mesh_row_add_c)); - ret(mesh_port_width_c+mesh_row_add_c+mesh_port_width_c-1 downto - mesh_row_add_c+mesh_port_width_c) := - std_logic_vector(to_unsigned(dst_port, mesh_port_width_c)); - - elsif src_col < dst_col then - - ret(mesh_port_width_c-1 downto 0) := - std_logic_vector(to_unsigned(0, mesh_port_width_c)); - ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) := - std_logic_vector(to_unsigned(2**mesh_row_add_c+row_dif, - mesh_row_add_c)); - ret(mesh_row_add_c+mesh_port_width_c*2-1 downto - mesh_row_add_c+mesh_port_width_c) := - std_logic_vector(to_unsigned(1, mesh_port_width_c)); - ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto - mesh_port_width_c*2+mesh_row_add_c) := - std_logic_vector(to_unsigned(2**mesh_col_add_c-col_dif, - mesh_col_add_c)); - ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto - mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) := - std_logic_vector(to_unsigned(dst_port, mesh_port_width_c)); - - else - - ret(mesh_port_width_c-1 downto 0) := - std_logic_vector(to_unsigned(0, mesh_port_width_c)); - ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) := - std_logic_vector(to_unsigned(2**mesh_row_add_c+row_dif, - mesh_row_add_c)); - ret(mesh_row_add_c+mesh_port_width_c*2-1 downto - mesh_row_add_c+mesh_port_width_c) := - std_logic_vector(to_unsigned(3, mesh_port_width_c)); - ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto - mesh_port_width_c*2+mesh_row_add_c) := - std_logic_vector(to_unsigned(2**mesh_col_add_c+col_dif, - mesh_col_add_c)); - ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto - mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) := - std_logic_vector(to_unsigned(dst_port, mesh_port_width_c)); - - end if; - - end if; - - return ret; - - end function ase_noc_address_s; - - - -end package body ase_noc_pkg; Index: funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/addr_translation.vhd =================================================================== --- funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/addr_translation.vhd (revision 90) +++ funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/addr_translation.vhd (nonexistent) @@ -1,125 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Address translation unit --- Project : -------------------------------------------------------------------------------- --- File : addr_translation.vhd --- Author : Lasse Lehtonen --- Company : --- Created : 2011-10-12 --- Last update: 2011-10-24 --- Platform : --- Standard : VHDL'87 -------------------------------------------------------------------------------- --- Description: --- --- Translates various addressing styles to network adresses and also --- handles inserting the original address behind the network address flit. --- --- Generics: --- --- address_mode_g 0 : IP gives raw network address --- address_mode_g 1 : IP gives integer ID numbers as target address --- address_mode_g 2 : IP gives memory mapped addresses --- --- addr_flit_en_g 0 : Nothing done --- addr_flit_en_g 1 : Places the original address to the second flit --- -------------------------------------------------------------------------------- --- Copyright (c) 2011 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2011-10-12 1.0 lehton87 Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity addr_translation is - - generic ( - my_id_g : natural; - cmd_width_g : positive; - data_width_g : positive; - address_mode_g : natural; - cols_g : positive; - rows_g : positive; - agents_g : positive; - agent_ports_g : positive; - addr_flit_en_g : natural; - noc_type_g : natural); - - port ( - clk : in std_logic; - rst_n : in std_logic; - -- from IP side - ip_cmd_in : in std_logic_vector(cmd_width_g-1 downto 0); - ip_data_in : in std_logic_vector(data_width_g-1 downto 0); - ip_stall_out : out std_logic; - -- to NET - net_cmd_out : out std_logic_vector(cmd_width_g-1 downto 0); - net_data_out : out std_logic_vector(data_width_g-1 downto 0); - net_stall_in : in std_logic; - orig_addr_out : out std_logic_vector(data_width_g-1 downto 0)); - -end addr_translation; - - -architecture rtl of addr_translation is - - signal addr_to_lut : std_logic_vector(data_width_g-1 downto 0); - signal addr_from_lut : std_logic_vector(data_width_g-1 downto 0); - signal orig_addr_r : std_logic_vector(data_width_g-1 downto 0); - -begin -- rtl - - safe_p: process (ip_cmd_in, ip_data_in) - begin -- process safe_p - if ip_cmd_in = "01" then - addr_to_lut <= ip_data_in; - else - addr_to_lut <= (others => '0'); - end if; - end process safe_p; - - addr_lut_1 : entity work.addr_lut - generic map ( - my_id_g => my_id_g, - data_width_g => data_width_g, - address_mode_g => address_mode_g, - cols_g => cols_g, - rows_g => rows_g, - agent_ports_g => agent_ports_g, - agents_g => agents_g, - noc_type_g => noc_type_g) - port map ( - addr_in => addr_to_lut, - addr_out => addr_from_lut); - - net_cmd_out <= ip_cmd_in; - ip_stall_out <= net_stall_in; - orig_addr_out <= orig_addr_r; - - oa_p : process (clk, rst_n) - begin -- process oa_p - if rst_n = '0' then -- asynchronous reset (active low) - orig_addr_r <= (others => '0'); - elsif clk'event and clk = '1' then -- rising clock edge - if ip_cmd_in = "01" then - orig_addr_r <= ip_data_in; - end if; - end if; - end process oa_p; - - mux_p : process (ip_cmd_in, addr_from_lut, ip_data_in) - begin -- process mux_p - if ip_cmd_in = "01" then - net_data_out <= addr_from_lut; - else - net_data_out <= ip_data_in; - end if; - end process mux_p; - - - -end rtl; Index: funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/ram_1clk.vhd =================================================================== --- funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/ram_1clk.vhd (revision 90) +++ funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/ram_1clk.vhd (nonexistent) @@ -1,83 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Single clock one port RAM --- Project : -------------------------------------------------------------------------------- --- File : ram_1clk.vhd --- Author : Lasse Lehtonen --- Company : --- Created : 2011-01-13 --- Last update: 2011-10-19 --- Platform : --- Standard : VHDL'93 -------------------------------------------------------------------------------- --- Description: --- --- Basic one port RAM with one clock, new data on read-during-write --- -------------------------------------------------------------------------------- --- Copyright (c) 2011 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2011-01-13 1.0 ase Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - -entity ram_1clk is - - generic ( - data_width_g : positive; - addr_width_g : positive; - depth_g : positive; - out_reg_en_g : natural); - - port ( - clk : in std_logic; - wr_addr_in : in std_logic_vector(addr_width_g-1 downto 0); - rd_addr_in : in std_logic_vector(addr_width_g-1 downto 0); - we_in : in std_logic; - data_in : in std_logic_vector(data_width_g-1 downto 0); - data_out : out std_logic_vector(data_width_g-1 downto 0)); - -end entity ram_1clk; - - -architecture rtl of ram_1clk is - - type ram_type is array (0 to depth_g-1) - of std_logic_vector(data_width_g-1 downto 0); - - signal ram_r : ram_type; - signal read_addr_r : integer range 0 to depth_g-1; - -begin -- architecture rtl - - ram_p : process (clk) is - begin -- process ram_p - if clk'event and clk = '1' then -- rising clock edge - - if we_in = '1' then - ram_r(to_integer(unsigned(wr_addr_in))) <= data_in; - end if; - - if out_reg_en_g = 1 then - read_addr_r <= to_integer(unsigned(rd_addr_in)); - end if; - - end if; - end process ram_p; - - out_reg_en_1: if out_reg_en_g = 1 generate - data_out <= ram_r(read_addr_r); - end generate out_reg_en_1; - - out_reg_en_0: if out_reg_en_g = 0 generate - data_out <= ram_r(to_integer(unsigned(rd_addr_in))); - end generate out_reg_en_0; - - -end architecture rtl; Index: funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/cdc.vhd =================================================================== --- funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/cdc.vhd (revision 90) +++ funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/cdc.vhd (nonexistent) @@ -1,222 +0,0 @@ -------------------------------------------------------------------------------- --- Title : CDC (Clock Domain Crossing) --- Project : -------------------------------------------------------------------------------- --- File : cdc.vhd --- Author : Lasse Lehtonen --- Company : --- Created : 2011-10-12 --- Last update: 2011-10-24 --- Platform : --- Standard : VHDL'87 -------------------------------------------------------------------------------- --- Description: --- --- Generics: --- --- clock_mode_g 0 : single clock --- clock_mode_g 1 : two asynchronous clocks --- -------------------------------------------------------------------------------- --- Copyright (c) 2011 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2011-10-12 1.0 lehton87 Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity cdc is - - generic ( - cmd_width_g : positive; - data_width_g : positive; - clock_mode_g : natural); - - port ( - clk_ip : in std_logic; - clk_net : in std_logic; - rst_n : in std_logic; - - ip_cmd_out : out std_logic_vector(cmd_width_g-1 downto 0); - ip_data_out : out std_logic_vector(data_width_g-1 downto 0); - ip_stall_in : in std_logic; - - ip_cmd_in : in std_logic_vector(cmd_width_g-1 downto 0); - ip_data_in : in std_logic_vector(data_width_g-1 downto 0); - ip_stall_out : out std_logic; - - net_cmd_out : out std_logic_vector(cmd_width_g-1 downto 0); - net_data_out : out std_logic_vector(data_width_g-1 downto 0); - net_stall_in : in std_logic; - - net_cmd_in : in std_logic_vector(cmd_width_g-1 downto 0); - net_data_in : in std_logic_vector(data_width_g-1 downto 0); - net_stall_out : out std_logic); - -end cdc; - - -architecture rtl of cdc is - - signal ip_in_cd : std_logic_vector(cmd_width_g+data_width_g-1 downto 0); - signal net_in_cd : std_logic_vector(cmd_width_g+data_width_g-1 downto 0); - signal ip_out_cd : std_logic_vector(cmd_width_g+data_width_g-1 downto 0); - signal net_out_cd : std_logic_vector(cmd_width_g+data_width_g-1 downto 0); - signal ip_out_cd_r : std_logic_vector(cmd_width_g+data_width_g-1 downto 0); - signal net_out_cd_r : std_logic_vector(cmd_width_g+data_width_g-1 downto 0); - signal ip_we : std_logic; - signal net_we : std_logic; - signal ip_re : std_logic; - signal net_re : std_logic; - signal ip_empty : std_logic; - signal net_empty : std_logic; - - -begin -- rtl - - ----------------------------------------------------------------------------- - -- ONE CLOCK - -- - -- Just a direct combinatorial connection - ----------------------------------------------------------------------------- - clock_mode_0 : if clock_mode_g = 0 generate - - ip_cmd_out <= net_cmd_in; - ip_data_out <= net_data_in; - net_stall_out <= ip_stall_in; - - net_cmd_out <= ip_cmd_in; - net_data_out <= ip_data_in; - ip_stall_out <= net_stall_in; - - end generate clock_mode_0; - - ----------------------------------------------------------------------------- - -- TWO ASYNCHRONOUS CLOCKS - ----------------------------------------------------------------------------- - clock_mode_1 : if clock_mode_g = 1 generate - - --------------------------------------------------------------------------- - -- FROM IP TO NET - --------------------------------------------------------------------------- - ip_in_cd <= ip_cmd_in & ip_data_in; - net_re <= not net_stall_in; - - ip_we_p : process (ip_cmd_in) - begin -- process ip_we_p - if ip_cmd_in /= "00" then - ip_we <= '1'; - else - ip_we <= '0'; - end if; - end process ip_we_p; - - fifo_ip2net : entity work.fifo_2clk - generic map ( - data_width_g => cmd_width_g+data_width_g, - depth_g => 4) - port map ( - rst_n => rst_n, - - clk_wr => clk_ip, - we_in => ip_we, - data_in => ip_in_cd, - full_out => ip_stall_out, - - clk_rd => clk_net, - re_in => net_re, - data_out => net_out_cd, - empty_out => net_empty); - - sto1_p: process (clk_net, rst_n) - begin -- process sto1_p - if rst_n = '0' then -- asynchronous reset (active low) - net_out_cd_r <= (others => '0'); - elsif clk_net'event and clk_net = '1' then -- rising clock edge - if net_stall_in = '0' and net_empty = '0' then - net_out_cd_r <= net_out_cd; - end if; - end if; - end process sto1_p; - - net_outs_p: process (net_stall_in, net_empty, net_out_cd, net_out_cd_r) - begin -- process net_outs_p - if net_stall_in = '1' then - net_cmd_out <= net_out_cd_r(cmd_width_g+data_width_g-1 downto - data_width_g); - net_data_out <= net_out_cd_r(data_width_g-1 downto 0); - elsif net_empty = '1' then - net_cmd_out <= (others => '0'); - net_data_out <= (others => '0'); - else - net_cmd_out <= net_out_cd(cmd_width_g+data_width_g-1 downto - data_width_g); - net_data_out <= net_out_cd(data_width_g-1 downto 0); - end if; - end process net_outs_p; - - --------------------------------------------------------------------------- - -- FROM NET TO IP - --------------------------------------------------------------------------- - net_in_cd <= net_cmd_in & net_data_in; - ip_re <= not ip_stall_in; - - net_we_p : process (net_cmd_in) - begin -- process ip_we_p - if net_cmd_in /= "00" then - net_we <= '1'; - else - net_we <= '0'; - end if; - end process net_we_p; - - fifo_net2ip : entity work.fifo_2clk - generic map ( - data_width_g => cmd_width_g+data_width_g, - depth_g => 4) - port map ( - rst_n => rst_n, - - clk_wr => clk_net, - we_in => net_we, - data_in => net_in_cd, - full_out => net_stall_out, - - clk_rd => clk_ip, - re_in => ip_re, - data_out => ip_out_cd, - empty_out => ip_empty); - - sto2_p: process (clk_ip, rst_n) - begin -- process sto1_p - if rst_n = '0' then -- asynchronous reset (active low) - ip_out_cd_r <= (others => '0'); - elsif clk_ip'event and clk_ip = '1' then -- rising clock edge - if ip_stall_in = '0' and ip_empty = '0' then - ip_out_cd_r <= ip_out_cd; - end if; - end if; - end process sto2_p; - - ip_outs_p: process (ip_stall_in, ip_empty, ip_out_cd, ip_out_cd_r) - begin -- process net_outs_p - if ip_stall_in = '1' then - ip_cmd_out <= ip_out_cd_r(cmd_width_g+data_width_g-1 downto - data_width_g); - ip_data_out <= ip_out_cd_r(data_width_g-1 downto 0); - elsif ip_empty = '1' then - ip_cmd_out <= (others => '0'); - ip_data_out <= (others => '0'); - else - ip_cmd_out <= ip_out_cd(cmd_width_g+data_width_g-1 downto - data_width_g); - ip_data_out <= ip_out_cd(data_width_g-1 downto 0); - end if; - end process ip_outs_p; - - end generate clock_mode_1; - -end rtl; Index: funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/ase_dring1_pkg.vhd =================================================================== --- funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/ase_dring1_pkg.vhd (revision 90) +++ funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/ase_dring1_pkg.vhd (nonexistent) @@ -1,166 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Package for ase_ring1 and wrappers using it --- Project : -------------------------------------------------------------------------------- --- File : ase_ring1_pkg.vhdl --- Author : Lasse Lehtonen --- Company : --- Created : 2010-07-04 --- Last update: 2011-11-03 --- Platform : --- Standard : VHDL'93 -------------------------------------------------------------------------------- --- Description: -------------------------------------------------------------------------------- --- Copyright (c) 2010 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2010-07-04 1.0 ase Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.log2_pkg.all; - -------------------------------------------------------------------------------- --- PACKAGE DECLARATION -------------------------------------------------------------------------------- -package ase_dring1_pkg is - - ----------------------------------------------------------------------------- - -- HELPER FUNCTIONS - ----------------------------------------------------------------------------- - - -- Returns data_width_c wide address calculated from source and - -- destination id numbers (ie. their position on the ring) - function dring1_address ( - src_id : in integer; - dst_id : in integer; - agents_c : in positive; - data_width_c : in positive) - return std_logic_vector; - - function dring1_address_s ( - constant src_id : in integer; - signal dst_id : in integer; - constant agents_c : in positive; - constant data_width_c : in positive) - return std_logic_vector; - -end package ase_dring1_pkg; - -------------------------------------------------------------------------------- --- PACKAGE BODY -------------------------------------------------------------------------------- -package body ase_dring1_pkg is - - ----------------------------------------------------------------------------- - -- FUNCTIONS - ----------------------------------------------------------------------------- - function dring1_address ( - src_id : in integer; - dst_id : in integer; - agents_c : in positive; - data_width_c : in positive) - return std_logic_vector is - variable retval_v : std_logic_vector(data_width_c-1 downto 0); - constant addr_width_c : positive := log2_ceil(agents_c/2); - variable src_v : integer; --natural range 0 to agents_c-1; - variable dst_v : integer; --natural range 0 to agents_c-1; - variable tmp_v : signed(addr_width_c+2 downto 0); - begin - retval_v := (others => '0'); - src_v := src_id; - dst_v := dst_id; - if src_v < dst_v then - if dst_v - src_v <= agents_c / 2 then - report "#1 src: " & integer'image(src_id) & " dst: " - & integer'image(dst_id) severity note; - retval_v(addr_width_c) := '0'; - retval_v(addr_width_c-1 downto 0) := - std_logic_vector(to_signed - (2**addr_width_c - (dst_v - src_v), addr_width_c+3) - (addr_width_c-1 downto 0)); - else - report "#2 src: " & integer'image(src_id) & " dst: " - & integer'image(dst_id) severity note; - retval_v(addr_width_c) := '1'; - retval_v(addr_width_c-1 downto 0) := - std_logic_vector(to_signed( - 2**addr_width_c - (agents_c - dst_v + src_v), addr_width_c+3) - (addr_width_c-1 downto 0)); - end if; - else - if src_v - dst_v <= agents_c / 2 then - report "#3 src: " & integer'image(src_id) & " dst: " - & integer'image(dst_id) severity note; - retval_v(addr_width_c) := '1'; - retval_v(addr_width_c-1 downto 0) := - std_logic_vector(to_signed - (2**addr_width_c - (src_v - dst_v), addr_width_c+3) - (addr_width_c-1 downto 0)); - else - report "#4 src: " & integer'image(src_id) & " dst: " - & integer'image(dst_id) severity note; - retval_v(addr_width_c) := '0'; - tmp_v := to_signed( - 2**addr_width_c - (agents_c - src_v + dst_v), addr_width_c+3); - report "#4 tmpv: " & integer'image(to_integer(tmp_v)); - retval_v(addr_width_c-1 downto 0) := std_logic_vector(tmp_v(addr_width_c-1 downto 0)); - report "#4 resv: " & - integer'image(2**addr_width_c - (agents_c - src_v + dst_v)) - severity note; - end if; - end if; - report "RESULT: " & integer'image(to_integer(unsigned(retval_v))) - severity note; - return retval_v; - end function dring1_address; - - - function dring1_address_s ( - constant src_id : in integer; - signal dst_id : in integer; - constant agents_c : in positive; - constant data_width_c : in positive) - return std_logic_vector is - variable retval_v : std_logic_vector(data_width_c-1 downto 0); - constant addr_width_c : positive := log2_ceil(agents_c/2); - variable src_v : integer; --natural range 0 to agents_c-1; - variable dst_v : integer; --natural range 0 to agents_c-1; - begin - retval_v := (others => '0'); - src_v := src_id; - dst_v := dst_id; - if src_v < dst_v then - if dst_v - src_v <= agents_c / 2 then - retval_v(addr_width_c) := '0'; - retval_v(addr_width_c-1 downto 0) := - std_logic_vector(to_unsigned - (2**addr_width_c - dst_v - src_v, addr_width_c)); - else - retval_v(addr_width_c) := '1'; - retval_v(addr_width_c-1 downto 0) := - std_logic_vector(to_unsigned( - 2**addr_width_c - agents_c - dst_v + src_v, addr_width_c)); - end if; - else - if src_v - dst_v <= agents_c / 2 then - retval_v(addr_width_c) := '1'; - retval_v(addr_width_c-1 downto 0) := - std_logic_vector(to_unsigned - (2**addr_width_c - src_v - dst_v, addr_width_c)); - else - retval_v(addr_width_c) := '0'; - retval_v(addr_width_c-1 downto 0) := - std_logic_vector(to_unsigned( - 2**addr_width_c - agents_c - src_v + dst_v, addr_width_c)); - end if; - end if; - return retval_v; - end function dring1_address_s; - -end package body ase_dring1_pkg; Index: funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/fifo_2clk.vhd =================================================================== --- funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/fifo_2clk.vhd (revision 90) +++ funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/fifo_2clk.vhd (nonexistent) @@ -1,326 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Basic FIFO with two clocks --- Project : -------------------------------------------------------------------------------- --- File : fifo_2clk.vhd --- Author : Lasse Lehtonen --- Company : --- Created : 2011-01-13 --- Last update: 2011-10-19 --- Platform : --- Standard : VHDL'93 -------------------------------------------------------------------------------- --- Description: --- --- Fully asynchronous fifo. --- --- Idea from: --- Cummings et al., Simulation and Synthesis Techniques for Asynchronous --- FIFO Design with Asynchronous Pointer Comparisons, SNUG San Jose 2002 --- -------------------------------------------------------------------------------- --- Copyright (c) 2011 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2011-01-13 1.0 ase Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - -entity fifo_2clk is - - generic ( - data_width_g : positive; - depth_g : positive); - - port ( - rst_n : in std_logic; - -- Write - clk_wr : in std_logic; - we_in : in std_logic; - data_in : in std_logic_vector(data_width_g-1 downto 0); - full_out : out std_logic; - -- Read - clk_rd : in std_logic; - re_in : in std_logic; - data_out : out std_logic_vector(data_width_g-1 downto 0); - empty_out : out std_logic); - -end entity fifo_2clk; - - -architecture rtl of fifo_2clk is - - ----------------------------------------------------------------------------- - -- FUNCTIONS - ----------------------------------------------------------------------------- - -- purpose: Return ceiling log 2 of n - function log2_ceil ( - constant n : positive) - return positive is - variable retval : positive := 1; - begin -- function log2_ceil - while 2**retval < n loop - retval := retval + 1; - end loop; - return retval; - end function log2_ceil; - - -- binary to graycode conversion - function bin2gray ( - signal num : integer range 0 to depth_g-1) - return std_logic_vector is - variable retval : std_logic_vector(log2_ceil(depth_g)-1 downto 0); - variable d1 : std_logic_vector(log2_ceil(depth_g)-1 downto 0); - begin - d1 := std_logic_vector((to_unsigned(num, log2_ceil(depth_g)))); - retval := d1 xor ('0' & d1(log2_ceil(depth_g)-1 downto 1)); - return retval; - end function bin2gray; - - ----------------------------------------------------------------------------- - -- CONSTANTS - ----------------------------------------------------------------------------- - constant addr_width_c : positive := log2_ceil(depth_g); - - ----------------------------------------------------------------------------- - -- REGISTERS - ----------------------------------------------------------------------------- - signal wr_addr_r : integer range 0 to depth_g-1; - signal rd_addr_r : integer range 0 to depth_g-1; - signal full_1_r : std_logic; - signal full_2_r : std_logic; - signal empty_1_r : std_logic; - signal empty_2_r : std_logic; - - ----------------------------------------------------------------------------- - -- COMBINATORIAL SIGNALS - ----------------------------------------------------------------------------- - signal next_wr_addr : integer range 0 to depth_g-1; - signal next_rd_addr : integer range 0 to depth_g-1; - signal wr_addr : std_logic_vector(addr_width_c-1 downto 0); - signal rd_addr : std_logic_vector(addr_width_c-1 downto 0); - signal we : std_logic; - signal dirset_n : std_logic; - signal dirclr_n : std_logic; - signal direction : std_logic; - signal h : std_logic; - signal empty_n : std_logic; - signal full_n : std_logic; - -begin -- architecture rtl - - - full_out <= full_2_r; - empty_out <= empty_2_r; - - ----------------------------------------------------------------------------- - -- WRITE - ----------------------------------------------------------------------------- - - write_p : process (clk_wr, rst_n) - begin -- process write_p - if rst_n = '0' then -- asynchronous reset (active low) - - wr_addr_r <= 0; - - elsif clk_wr'event and clk_wr = '1' then -- rising clock edge - - if we_in = '1' and full_2_r = '0' then - wr_addr_r <= next_wr_addr; - end if; - - end if; - end process write_p; - - we <= we_in and not full_2_r; - - ----------------------------------------------------------------------------- - -- READ - ----------------------------------------------------------------------------- - - read_p : process (clk_rd, rst_n) - begin -- process read_p - if rst_n = '0' then -- asynchronous reset (active low) - - rd_addr_r <= 0; - - elsif clk_rd'event and clk_rd = '1' then -- rising clock edge - - if re_in = '1' and empty_2_r = '0' then - rd_addr_r <= next_rd_addr; - end if; - - end if; - end process read_p; - - ----------------------------------------------------------------------------- - -- RAM - ----------------------------------------------------------------------------- - - wr_addr <= std_logic_vector(to_unsigned(wr_addr_r, addr_width_c)); - rd_addr <= std_logic_vector(to_unsigned(rd_addr_r, addr_width_c)); - - ram_2clk_1 : entity work.ram_1clk - generic map ( - data_width_g => data_width_g, - addr_width_g => addr_width_c, - depth_g => depth_g, - out_reg_en_g => 0) - port map ( - clk => clk_wr, - wr_addr_in => wr_addr, - rd_addr_in => rd_addr, - we_in => we, - data_in => data_in, - data_out => data_out); - - ----------------------------------------------------------------------------- - -- NEXT ADDRESSES - ----------------------------------------------------------------------------- - - next_wr_addr_p : process (wr_addr_r) is - begin - - if wr_addr_r = depth_g-1 then - next_wr_addr <= 0; - else - next_wr_addr <= wr_addr_r + 1; - end if; - - end process next_wr_addr_p; - - next_rd_addr_p : process (rd_addr_r) is - begin - - if rd_addr_r = depth_g-1 then - next_rd_addr <= 0; - else - next_rd_addr <= rd_addr_r + 1; - end if; - - end process next_rd_addr_p; - - ----------------------------------------------------------------------------- - -- ASYNC COMPARISON (FULL AND EMPTY GENERATION) - ----------------------------------------------------------------------------- - - dirgen_p : process (wr_addr_r, rd_addr_r, rst_n) - variable wr_h1 : std_logic; - variable wr_h2 : std_logic; - variable rd_h1 : std_logic; - variable rd_h2 : std_logic; - begin -- process asyncomp_p - - wr_h1 := bin2gray(wr_addr_r)(addr_width_c-1); - wr_h2 := bin2gray(wr_addr_r)(addr_width_c-2); - rd_h1 := bin2gray(rd_addr_r)(addr_width_c-1); - rd_h2 := bin2gray(rd_addr_r)(addr_width_c-2); - - dirset_n <= not ((wr_h1 xor rd_h2) and not (wr_h2 xor rd_h1)); - dirclr_n <= not ((not (wr_h1 xor rd_h2) and (wr_h2 xor rd_h1)) - or not rst_n); - - end process dirgen_p; - - h <= '1'; - --- dir_rs_flop_p : process (dirset_n, dirclr_n, h) --- begin -- process dir_rs_flop_p - --- if (h'event and h = '1') or --- (dirset_n'event and dirset_n = '0') or --- (dirclr_n'event and dirclr_n = '0') then - --- if dirclr_n = '0' then --- direction <= '0'; --- elsif dirset_n = '0' then --- direction <= '1'; --- else --- direction <= h; --- end if; - --- end if; - --- end process dir_rs_flop_p; - - rs_flop_p : process (dirclr_n, dirset_n, direction) - begin -- process rs_flop_p - if dirclr_n = '0' then - direction <= '0'; - elsif dirset_n = '0' then - direction <= '1'; - else - direction <= direction; - end if; - end process rs_flop_p; - - full_empty_s : process (direction, wr_addr_r, rd_addr_r) - variable match_v : std_logic; - begin -- process empty_s - if rd_addr_r = wr_addr_r then - match_v := '1'; - else - match_v := '0'; - end if; - if match_v = '1' and direction = '1' then - full_n <= '0'; - else - full_n <= '1'; - end if; - if match_v = '1' and direction = '0' then - empty_n <= '0'; - else - empty_n <= '1'; - end if; - end process full_empty_s; - - empty_sync_1p : process (clk_rd, rst_n, empty_n) - begin -- process empty_sync_p - if rst_n = '0' then -- asynchronous reset (active low) - empty_1_r <= '1'; - elsif empty_n = '0' then - empty_1_r <= not empty_n; - elsif clk_rd'event and clk_rd = '1' then -- rising clock edge - empty_1_r <= not empty_n; - end if; - end process empty_sync_1p; - - empty_sync_2p : process (clk_rd, rst_n, empty_n, empty_1_r) - begin -- process empty_sync_p - if rst_n = '0' then -- asynchronous reset (active low) - empty_2_r <= '1'; - elsif empty_n = '0' then - empty_2_r <= empty_1_r; - elsif clk_rd'event and clk_rd = '1' then -- rising clock edge - empty_2_r <= empty_1_r; - end if; - end process empty_sync_2p; - - full_sync_1p : process (clk_wr, rst_n, full_n) - begin -- process empty_sync_p - if rst_n = '0' then -- asynchronous reset (active low) - full_1_r <= '0'; - elsif full_n = '0' then - full_1_r <= not full_n; - elsif clk_wr'event and clk_wr = '1' then -- rising clock edge - full_1_r <= not full_n; - end if; - end process full_sync_1p; - - full_sync_2p : process (clk_wr, rst_n, full_n, full_1_r) - begin -- process empty_sync_p - if rst_n = '0' then -- asynchronous reset (active low) - full_2_r <= '0'; - elsif full_n = '0' then - full_2_r <= full_1_r; - elsif clk_wr'event and clk_wr = '1' then -- rising clock edge - full_2_r <= full_1_r; - end if; - end process full_sync_2p; - -end architecture rtl; Index: funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/addr_lut.vhd =================================================================== --- funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/addr_lut.vhd (revision 90) +++ funbase_ip_library/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/addr_lut.vhd (nonexistent) @@ -1,198 +0,0 @@ -------------------------------------------------------------------------------- --- Title : Address look-up table --- Project : -------------------------------------------------------------------------------- --- File : addr_lut.vhd --- Author : Lasse Lehtonen --- Company : --- Created : 2011-01-12 --- Last update: 2011-11-09 --- Platform : --- Standard : VHDL'93 -------------------------------------------------------------------------------- --- Description: Converts memory mapped I/O address to NoC address -------------------------------------------------------------------------------- --- Copyright (c) 2011 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2011-01-12 1.0 ase Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.ase_noc_pkg.all; -use work.ase_mesh1_pkg.all; -use work.ase_dring1_pkg.all; - -entity addr_lut is - - generic ( - my_id_g : natural; - data_width_g : positive; - address_mode_g : natural; - cols_g : positive; - rows_g : positive; - agent_ports_g : positive; - agents_g : positive; - noc_type_g : natural); - - port ( - addr_in : in std_logic_vector(data_width_g-1 downto 0); - addr_out : out std_logic_vector(data_width_g-1 downto 0)); - -end entity addr_lut; - - - -architecture rtl of addr_lut is - - -- How many different address ranges there are - constant n_addr_ranges_c : positive := 32; - constant mesh_ids_c : positive := cols_g*rows_g*agent_ports_g; - - signal noc_target : integer; - - - type addr_range_type is array (0 to 2) of unsigned(data_width_g-1 downto 0); - type addr_lut_type is array (0 to n_addr_ranges_c-1) of addr_range_type; - - function addr_gen ( - constant target : natural) - return unsigned is - variable retval : unsigned(data_width_g-1 downto 0); - begin - if noc_type_g = 0 then - retval := unsigned(ase_noc_address(my_id_g, target, cols_g, rows_g, - agent_ports_g, data_width_g)); - return retval; - end if; - if noc_type_g = 1 then - retval := unsigned(ase_mesh1_address(my_id_g, target, rows_g, cols_g, - data_width_g)); - return retval; - end if; - if noc_type_g = 2 then - retval := unsigned(dring1_address(my_id_g, target, agents_g, - data_width_g)); - return retval; - end if; - end addr_gen; - - function addr_gen_s ( - signal target : integer) - return std_logic_vector is - variable retval : std_logic_vector(data_width_g-1 downto 0); - begin - if noc_type_g = 0 then - retval := ase_noc_address_s(my_id_g, target, cols_g, rows_g, - agent_ports_g, data_width_g); - return retval; - end if; - if noc_type_g = 1 then - retval := ase_mesh1_address(my_id_g, target, rows_g, cols_g, - data_width_g); - return retval; - end if; - if noc_type_g = 2 then - retval := dring1_address(my_id_g, target, agents_g, data_width_g); - return retval; - end if; - end addr_gen_s; - - -- First = address range's minimum address - -- Second = address range's maximum address - -- Third = corresponding network address - - constant addr_lut_c : addr_lut_type := - ( - (x"00000000", x"00FFFFFF", addr_gen(0)), - (x"01000000", x"01FFFFFF", addr_gen(1)), - (x"02000000", x"02FFFFFF", addr_gen(2)), - (x"03000000", x"03FFFFFF", addr_gen(3)), - (x"04000000", x"04FFFFFF", addr_gen(4)), - (x"05000000", x"05FFFFFF", addr_gen(5)), - (x"06000000", x"06FFFFFF", addr_gen(6)), - (x"07000000", x"07FFFFFF", addr_gen(7)), - (x"08000000", x"08FFFFFF", addr_gen(8)), - (x"09000000", x"09FFFFFF", addr_gen(9)), - (x"0A000000", x"0AFFFFFF", addr_gen(10)), - (x"0B000000", x"0BFFFFFF", addr_gen(11)), - (x"0C000000", x"0CFFFFFF", addr_gen(12)), - (x"0D000000", x"0DFFFFFF", addr_gen(13)), - (x"0E000000", x"0EFFFFFF", addr_gen(14)), - (x"0F000000", x"0FFFFFFF", addr_gen(15)), - (x"10000000", x"10FFFFFF", addr_gen(16)), - (x"11000000", x"11FFFFFF", addr_gen(17)), - (x"12000000", x"12FFFFFF", addr_gen(18)), - (x"13000000", x"13FFFFFF", addr_gen(19)), - (x"14000000", x"14FFFFFF", addr_gen(20)), - (x"15000000", x"15FFFFFF", addr_gen(21)), - (x"16000000", x"16FFFFFF", addr_gen(22)), - (x"17000000", x"17FFFFFF", addr_gen(23)), - (x"18000000", x"18FFFFFF", addr_gen(24)), - (x"19000000", x"19FFFFFF", addr_gen(25)), - (x"1A000000", x"1AFFFFFF", addr_gen(26)), - (x"1B000000", x"1BFFFFFF", addr_gen(27)), - (x"1C000000", x"1CFFFFFF", addr_gen(28)), - (x"1D000000", x"1DFFFFFF", addr_gen(29)), - (x"1E000000", x"1EFFFFFF", addr_gen(30)), - (x"1F000000", x"1FFFFFFF", addr_gen(31)) - ); - --- constant addr_lut_c : addr_lut_type := --- ( --- (x"0000", x"0FFF", addr_gen(0)), --- (x"1000", x"1FFF", addr_gen(1)), --- (x"2000", x"2FFF", addr_gen(2)), --- (x"3000", x"3FFF", addr_gen(3)) --- ); - -begin -- architecture rtl - - ----------------------------------------------------------------------------- - -- MEMORY MAPPED ADDRESSES - ----------------------------------------------------------------------------- - use_mem_addr_gen : if address_mode_g = 2 generate - - translate_p : process (addr_in) is - begin -- process translate_p - - addr_out <= (others => '1'); - - for i in 0 to n_addr_ranges_c-1 loop - - if unsigned(addr_in) >= addr_lut_c(i)(0) - and unsigned(addr_in) <= addr_lut_c(i)(1) then - - addr_out <= std_logic_vector(addr_lut_c(i)(2)); - end if; - - end loop; -- i - - end process translate_p; - - end generate use_mem_addr_gen; - - ----------------------------------------------------------------------------- - -- INTEGER ADDRESSES - ----------------------------------------------------------------------------- - use_int_addr_gen : if address_mode_g = 1 generate - - noc_target <= to_integer(unsigned(addr_in(data_width_g-2 downto 0))); - addr_out <= addr_gen_s(noc_target); - - end generate use_int_addr_gen; - - ----------------------------------------------------------------------------- - -- NO ADDRESS TRANSLATION - ----------------------------------------------------------------------------- - no_translation_g : if address_mode_g = 0 generate - - addr_out <= addr_in; - - end generate no_translation_g; - -end architecture rtl;

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