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Rev 90 → Rev 91

/raytrac/trunk/fpbranch/ema2.vhd
40,10 → 40,29
end ema2;
 
architecture ema2_arch of ema2 is
signal sa,sb,ssa,ssb,sssa,sssb,s4a : std_logic_vector(31 downto 0);
signal s4umb : std_logic_vector(23 downto 0);
signal s4sma,s4smb : std_logic_vector(24 downto 0);
signal s4sgb,za,zb,ssz : std_logic;
component lpm_mult
generic (
lpm_hint : string;
lpm_representation : string;
lpm_type : string;
lpm_widtha : natural;
lpm_widthb : natural;
lpm_widthp : natural
);
port (
dataa : in std_logic_vector ( lpm_widtha-1 downto 0 );
datab : in std_logic_vector ( lpm_widthb-1 downto 0 );
result : out std_logic_vector( lpm_widthp-1 downto 0 )
);
end component;
signal bss : std_logic_vector(22 downto 0); -- Inversor de la mantissa
signal sa,sb,ssa,ssb,sssa,sssb,s4a : std_logic_vector(31 downto 0); -- Float 32 bit
signal s4umb : std_logic_vector(23 downto 0); -- Unsigned mantissa
signal s4sma,s4smb : std_logic_vector(24 downto 0); -- Signed mantissas
signal sspH,sspL : std_logic_vector(35 downto 0); -- Shifter Product
signal s4sgb,zeroa,zerob,ssz : std_logic;
begin
 
process (clk)
61,7 → 80,7
ssb(30 downto 23) <= sa(30 downto 23)-sb(30 downto 23);
ssb(22 downto 0) <= sb(22 downto 0);
--! zero signaling
ssz <= zb;
ssz <= zerob;
--!clasifica a
ssa <= sa;
71,17 → 90,25
ssb(30 downto 23) <= sb(30 downto 23)-sa(30 downto 23);
ssb(22 downto 0) <= sa(22 downto 0);
--! zero signaling
ssz <= za;
ssz <= zeroa;
--!clasifica b
ssa <= sb;
end if;
--! Tercera etapa corrimiento y normalizaci&oacute;n de mantissas
--! Segunda etapa corrimiento y denormalizaci&oacute;n de mantissas
s4a <= ssa;
s4sgb <= ssb(31);
s4umb <= shr(ssz&ssb(22 downto 0),ssb(30 downto 23));
--! Cuarta etapa signar la mantissa y entregar el exponente.
for i in 17 downto 0 loop
s4umb(i) <= sspH(17-i) or sspL(23-i);
end loop;
for i in 23 downto 18 loop
s4umb(i) <= sspL(23-i);
end loop;
 
--! Tercera etapa signar la mantissa y entregar el exponente.
sma <= s4sma + s4a(31);
smb <= s4smb + s4sgb;
exp <= s4a(30 downto 23);
88,7 → 115,13
end if;
end process;
--! Combinatorial Gremlin
highshiftermult:lpm_mult
generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",18,18,36)
port map (shl(conv_std_logic_vector(1,18),ssb(30 downto 23)),bss(22 downto 5),sspH);
lowshiftermult:lpm_mult
generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",18,18,36)
port map (shl(conv_std_logic_vector(1,18),ssb(30 downto 23)),conv_std_logic_vector(0,12)&bss(4 downto 0)&ssz,sspL);
 
--!Signar b y c
signbc:
for i in 23 downto 0 generate
107,20 → 140,24
--! zero
process (sb,sa)
begin
zb <='0';
za <='0';
zerob <='0';
zeroa <='0';
for i in 30 downto 23 loop
if sa(i)='1' then
za <= '1';
zeroa <= '1';
end if;
if sb(i)='1' then
zb <='1';
zerob <='1';
end if;
end loop;
end process;
--! ssb2bssInversor de posicion
ssb2bss:
for i in 22 downto 0 generate
bss(i) <= ssb(22-i);
end generate ssb2bss;
end ema2_arch;
 
/raytrac/trunk/fpbranch/ema3.vhd
29,6 → 29,7
use ieee.std_logic_arith.all;
 
 
 
entity ema3 is
port (
clk : in std_logic;
42,10 → 43,28
end ema3;
 
architecture ema3_arch of ema3 is
signal sa,sb,sc,ssa,ssb,ssc,sssa,sssb,sssc,s4a : std_logic_vector(31 downto 0);
component lpm_mult
generic (
lpm_hint : string;
lpm_representation : string;
lpm_type : string;
lpm_widtha : natural;
lpm_widthb : natural;
lpm_widthp : natural
);
port (
dataa : in std_logic_vector ( lpm_widtha-1 downto 0 );
datab : in std_logic_vector ( lpm_widthb-1 downto 0 );
result : out std_logic_vector( lpm_widthp-1 downto 0 )
);
end component;
signal bss,css : std_logic_vector(22 downto 0);
signal sa,sb,sc,ssa,ssb,ssc,s4a : std_logic_vector(31 downto 0);
signal s4umb,s4umc : std_logic_vector(23 downto 0);
signal s4sma,s4smb,s4smc : std_logic_vector(24 downto 0);
signal s4sgb,s4sgc : std_logic;
signal s4sma,s4smb,s4smc : std_logic_vector(24 downto 0);
signal sspHb,sspLb,sspHc,sspLc : std_logic_vector(35 downto 0);
signal s4sgb,s4sgc,zeroa,zerob,zeroc,sszb,sszc : std_logic;
begin
 
process (clk)
58,52 → 77,62
sc <= c32;
 
--!Primera etapa a vs. b
if sa(30 downto 23) >= sb (30 downto 23) then
--!signo,exponente,mantissa
if sa(30 downto 23) >= sb (30 downto 23) and sa(30 downto 23) >=sc(30 downto 23) then
--!signo,exponente,mantissa de b yc
ssb(31) <= sb(31);
ssb(30 downto 23) <= sb(30 downto 23);
ssb(30 downto 23) <= sa(30 downto 23) - sb(30 downto 23);
ssb(22 downto 0) <= sb(22 downto 0);
sszb <= zerob;
ssc(31) <= sc(31);
ssc(30 downto 23) <= sa(30 downto 23) - sc(30 downto 23);
ssc(22 downto 0) <= sc(22 downto 0);
sszc <= zeroc;
--!clasifica a
ssa <= sa;
else
elsif sb(30 downto 23) >= sc (30 downto 23) then
--!signo,exponente,mantissa
ssb(31) <= sa(31);
ssb(30 downto 23) <= sa(30 downto 23);
ssb(30 downto 23) <= sb(30 downto 23)-sa(30 downto 23);
ssb(22 downto 0) <= sa(22 downto 0);
sszb <= zeroa;
ssc(31) <= sc(31);
ssc(30 downto 23) <= sb(30 downto 23) - sc(30 downto 23);
ssc(22 downto 0) <= sc(22 downto 0);
sszc <= zeroc;
--!clasifica b
ssa <= sb;
end if;
ssc <= sc;
--!Segunda Etapa, ganador de a/b vs c, resta de exponentes para saber cuanto se debe correr.
if ssa(30 downto 23) >= ssc (30 downto 23) then
else
--!signo,exponente,mantissa
sssc(31) <= ssc(31);
sssc(30 downto 23) <= ssa(30 downto 23)-ssc(30 downto 23);
sssb(30 downto 23) <= ssa(30 downto 23)-ssb(30 downto 23);
sssc(22 downto 0) <= ssc(22 downto 0);
--!clasifica ganador de ab
sssa <= ssa;
else
--!signo,exponente,mantissa
sssc(31) <= ssa(31);
sssc(30 downto 23) <= ssc(30 downto 23)-ssa(30 downto 23);
sssb(30 downto 23) <= ssc(30 downto 23)-ssb(30 downto 23);
sssc(22 downto 0) <= ssa(22 downto 0);
ssb(31) <= sb(31);
ssb(30 downto 23) <= sc(30 downto 23)-sb(30 downto 23);
ssb(22 downto 0) <= sb(22 downto 0);
sszb <= zerob;
ssc(31) <= sa(31);
ssc(30 downto 23) <= sc(30 downto 23) - sa(30 downto 23);
ssc(22 downto 0) <= sa(22 downto 0);
sszc <= zeroa;
--!clasifica c
sssa <= ssc;
ssa <= sc;
end if;
sssb(31) <= ssb(31);
sssb(22 downto 0) <= ssb(22 downto 0);
--! Tercera etapa corrimiento y normalizaci&oacute;n de mantissas
s4a <= sssa;
s4sgb <= sssb(31);
s4sgc <= sssc(31);
s4umb <= shr('1'&sssb(22 downto 0),sssb(30 downto 23));
s4umc <= shr('1'&sssc(22 downto 0),sssc(30 downto 23));
--! Cuarta etapa signar la mantissa y entregar el exponente.
--! Segunda etapa corrimiento y normalizaci&oacute;n de mantissas
s4a <= ssa;
s4sgb <= ssb(31);
s4sgc <= ssc(31);
for i in 17 downto 0 loop
s4umb(i) <= sspHb(17-i) or sspLb(23-i);
s4umc(i) <= sspHc(17-i) or sspLc(23-i);
end loop;
for i in 23 downto 18 loop
s4umb(i) <= sspLb(23-i);
s4umc(i) <= sspLc(23-i);
end loop;
--! Tercera etapa signar la mantissa y entregar el exponente.
sma <= s4sma + s4a(31);
smb <= s4smb + s4sgb;
smc <= s4smc + s4sgc;
110,7 → 139,20
exp <= s4a(30 downto 23);
end if;
end process;
--! Combinatorial Gremlin
highshiftermultb:lpm_mult
generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",18,18,36)
port map (shl(conv_std_logic_vector(1,18),ssb(30 downto 23)),bss(22 downto 5),sspHb);
lowshiftermultb:lpm_mult
generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",18,18,36)
port map (shl(conv_std_logic_vector(1,18),ssb(30 downto 23)),conv_std_logic_vector(0,12)&bss(4 downto 0)&sszb,sspLb);
highshiftermultc:lpm_mult
generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",18,18,36)
port map (shl(conv_std_logic_vector(1,18),ssc(30 downto 23)),css(22 downto 5),sspHc);
lowshiftermultc:lpm_mult
generic map ("DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9","UNSIGNED","LPM_MULT",18,18,36)
port map (shl(conv_std_logic_vector(1,18),ssc(30 downto 23)),conv_std_logic_vector(0,12)&css(4 downto 0)&sszc,sspLc);
--!Signar b y c
signbc:
127,8 → 169,35
s4sma(i) <= s4a(31) xor s4a(i);
end generate;
s4sma(23) <= not(s4a(31));
s4sma(24) <= s4a(31);
s4sma(24) <= s4a(31);
--! zero
process (sc,sb,sa)
begin
zeroc <= '0';
zerob <= '0';
zeroa <= '0';
for i in 30 downto 23 loop
if sa(i)='1' then
zeroa <= '1';
end if;
if sb(i)='1' then
zerob <='1';
end if;
if sc(i)='1' then
zeroc <='1';
end if;
end loop;
end process;
--! ssb2bssInversor de posicion
ssb2bss:
for i in 22 downto 0 generate
bss(i) <= ssb(22-i);
css(i) <= ssc(22-i);
end generate ssb2bss;
end ema3_arch;
 

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