OpenCores
URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 914 to Rev 915
    ↔ Reverse comparison
  •

Rev 914 → Rev 915

/trunk/or1ksim/cuc/bb.c
83,7 → 83,11
assert (n->init_bb_reloc = (int *)malloc (sizeof (int) * f->num_init_bb));
for (b = 0; b < f->num_init_bb; b++) n->init_bb_reloc[b] = f->init_bb_reloc[b];
n->num_init_bb = f->num_init_bb;
for (i = 0; i < MAX_REGS; i++) n->saved_regs[i] = f->saved_regs[i];
for (i = 0; i < MAX_REGS; i++) {
n->saved_regs[i] = f->saved_regs[i];
n->lur[i] = f->lur[i];
n->used_regs[i] = f->used_regs[i];
}
n->start_addr = f->start_addr;
n->end_addr = f->end_addr;
n->orig_time = f->orig_time;
/trunk/or1ksim/cuc/verilog.c
23,7 → 23,11
#include <assert.h>
#include "cuc.h"
#include "insn.h"
#include "profiler.h"
 
/* Shortcut */
#define GEN(x...) fprintf (fo, x)
 
/* returns log2(x) */
int log2 (unsigned long x)
{
64,11 → 68,11
int first = 0;
while (t) {
if (f->INSN(t->ref).type & IT_MEMORY) {
fprintf (fo, "%s%c_end[%i]", first ? " && " : "",
GEN ("%s%c_end[%i]", first ? " && " : "",
II_IS_LOAD (f->INSN(t->ref).index) ? 'l' : 's', find_lsc_index (f, t->ref));
} else if (f->INSN(t->ref).index == II_CALL) {
int x;
fprintf (fo, "%sf_end[%i]", first ? " && " : "", find_lsc_index (f, t->ref));
GEN ("%sf_end[%i]", first ? " && " : "", find_lsc_index (f, t->ref));
} else {
printf ("print_deps: err %x\n", t->ref);
assert (0);
77,8 → 81,8
t = t->next;
}
} else {
if (registered) fprintf (fo, "bb_start_r[%i]", b);
else fprintf (fo, "bb_start[%i]", b);
if (registered) GEN ("bb_start_r[%i]", b);
else GEN ("bb_start[%i]", b);
}
}
 
122,7 → 126,7
else sprintf (tmp, "%s%c", tmp, *s);
s++;
}
fprintf (fo, "%-40s /* %s */\n", tmp, ii->disasm);
GEN ("%-40s /* %s */\n", tmp, ii->disasm);
if (ii->type & IT_MEMORY) {
int j, nls = find_lsc_index (f, REF (b, i));
if (II_IS_LOAD (ii->index)) {
130,36 → 134,36
for (nm = 0; nm < f->nmsched; nm++) if (f->msched[nm] == REF (b, i)) break;
assert (nm < f->nmsched);
 
fprintf (fo, " if (rst) t%x_%x <= #1 32'h0;\n", b, i);
fprintf (fo, " else if (l_end[%i]) t%x_%x <= #1 ", nls, b, i);
GEN (" if (rst) t%x_%x <= #Tp 32'h0;\n", b, i);
GEN (" else if (l_end[%i]) t%x_%x <= #Tp ", nls, b, i);
switch (f->mtype[nm] & (MT_WIDTH | MT_SIGNED)) {
case 1: fprintf (fo, "lwb_dat_i & 32'hff;\n");
case 1: GEN ("lwb_dat_i & 32'hff;\n");
break;
case 2: fprintf (fo, "lwb_dat_i & 32'hffff;\n");
case 2: GEN ("lwb_dat_i & 32'hffff;\n");
break;
case 4 | MT_SIGNED:
case 4: fprintf (fo, "lwb_dat_i;\n");
case 4: GEN ("lwb_dat_i;\n");
break;
case 1 | MT_SIGNED:
fprintf (fo, "{24{lwb_dat_i[7]}, lwb_dat_i[7:0]};\n");
GEN ("{24{lwb_dat_i[7]}, lwb_dat_i[7:0]};\n");
break;
case 2 | MT_SIGNED:
fprintf (fo, "{16{lwb_dat_i[15]}, lwb_dat_i[15:0]};\n");
GEN ("{16{lwb_dat_i[15]}, lwb_dat_i[15:0]};\n");
break;
default: assert (0);
}
}
} else if (ii->index == II_LRBB) {
fprintf (fo, " if (rst) t%x_%x <= #1 1'b0;\n", b, i);
GEN (" if (rst) t%x_%x <= #Tp 1'b0;\n", b, i);
assert (f->bb[b].prev[0] >= 0);
fprintf (fo, " else if (bb_start[%i]) t%x_%x <= #1 bb_stb[%i];\n", b, b, i, f->bb[b].prev[0]);
GEN (" else if (bb_start[%i]) t%x_%x <= #Tp bb_stb[%i];\n", b, b, i, f->bb[b].prev[0]);
} else if (ii->index == II_REG) {
fprintf (fo, " if (rst) t%x_%x <= #1 32'h0;\n", b, i);
GEN (" if (rst) t%x_%x <= #Tp 32'h0;\n", b, i);
assert (ii->opt[1] == OPT_REF);
fprintf (fo, " else if (");
GEN (" else if (");
if (f->bb[b].mdep) print_deps (fo, f, b, f->bb[b].mdep, 0);
else fprintf (fo, "bb_stb[%i]", b);
fprintf (fo, ") t%x_%x <= #1 t%x_%x;\n", b, i,
else GEN ("bb_stb[%i]", b);
GEN (") t%x_%x <= #Tp t%x_%x;\n", b, i,
REF_BB (ii->op[1]), REF_I (ii->op[1]));
}
}
187,7 → 191,7
{
while (dep) {
assert (f->INSN(dep->ref).type & IT_MEMORY || f->INSN(dep->ref).index == II_CALL);
fprintf (fo, " %c_stb[%i] <= #1 1'b0;\n", f->INSN(dep->ref).index == II_CALL ? 'f'
GEN (" %c_stb[%i] <= #Tp 1'b0;\n", f->INSN(dep->ref).index == II_CALL ? 'f'
: II_IS_LOAD (f->INSN(dep->ref).index) ? 'l' : 's', find_lsc_index (f, dep->ref));
dep = dep->next;
}
230,90 → 234,92
assert (end_bb && end_bb->type & BB_END);
 
/* output header */
fprintf (fo, "/* %s -- generated by OpenRISC Custom Unit Compiler\n", tmp);
fprintf (fo, " (C) 2002 OpenCores.\n");
fprintf (fo, " function \"%s\"\n", filename);
fprintf (fo, " at %08x - %08x\n", f->start_addr, f->end_addr);
fprintf (fo, " num BBs %i */\n\n", f->num_bb);
fprintf (fo, "module %s (clk, rst,\n", filename);
fprintf (fo, " lwb_adr_o, lwb_dat_i, lwb_cycstb_o,\n");
fprintf (fo, " lwb_sel_o, lwb_linbrst_o, lwb_ack_i,\n");
fprintf (fo, " swb_adr_o, swb_dat_o, swb_cycstb_o,\n");
fprintf (fo, " swb_sel_o, swb_linbrst_o, swb_ack_i,\n");
GEN ("/* %s -- generated by OpenRISC Custom Unit Compiler\n", tmp);
GEN (" (C) 2002 OpenCores http://www.opencores.org/\n");
GEN (" function \"%s\"\n", filename);
GEN (" at %08x - %08x\n", f->start_addr, f->end_addr);
GEN (" num BBs %i */\n\n", f->num_bb);
GEN ("module %s (clk, rst,\n", filename);
GEN (" lwb_adr_o, lwb_dat_i, lwb_cycstb_o,\n");
GEN (" lwb_sel_o, lwb_linbrst_o, lwb_ack_i,\n");
GEN (" swb_adr_o, swb_dat_o, swb_cycstb_o,\n");
GEN (" swb_sel_o, swb_linbrst_o, swb_ack_i,\n");
 
fprintf (fo, "/* inputs */ ");
GEN ("/* inputs */ ");
for (i = 0; i < MAX_REGS; i++)
if (f->used_regs[i]) {
fprintf (fo, "r%i_i, ", i);
GEN ("r%i_i, ", i);
ci++;
}
if (!ci) fprintf (fo, "/* NONE */");
if (!ci) GEN ("/* NONE */");
 
fprintf (fo, "\n/* outputs */ ");
GEN ("\n/* outputs */ ");
for (i = 0; i < MAX_REGS; i++)
if (f->lur[i] >= 0 && !f->saved_regs[i]) {
fprintf (fo, "r%i_o, ", i);
GEN ("r%i_o, ", i);
co++;
}
 
if (!co) fprintf (fo, "/* NONE */");
if (!co) GEN ("/* NONE */");
if (f->nfdeps) {
fprintf (fo, "\n/* f. calls */, fstart_o, %sfend_i, fr11_i, ",
GEN ("\n/* f. calls */, fstart_o, %sfend_i, fr11_i, ",
log2 (f->nfdeps) > 0 ? "fid_o, " : "");
for (i = 0; i < 6; i++) fprintf (fo, "fr%i_o, ", i + 3);
for (i = 0; i < 6; i++) GEN ("fr%i_o, ", i + 3);
}
fprintf (fo, "\n start_i, end_o, busy_o);\n\n");
GEN ("\n start_i, end_o, busy_o);\n\n");
 
fprintf (fo, "input clk, rst;\n");
fprintf (fo, "input start_i;\t/* Module starts when set to 1 */ \n");
fprintf (fo, "output end_o;\t/* Set when module finishes, cleared upon start_i == 1 */\n");
fprintf (fo, "output busy_o;\t/* Set when module should not be interrupted */\n");
fprintf (fo, "\n/* Bus signals */\n");
fprintf (fo, "output lwb_cycstb_o, swb_cycstb_o;\n");
fprintf (fo, "input lwb_ack_i, swb_ack_i;\n");
fprintf (fo, "output [3:0] lwb_sel_o, swb_sel_o;\n");
fprintf (fo, "output [31:0] lwb_adr_o, swb_adr_o;\n");
fprintf (fo, "output lwb_linbrst_o, swb_linbrst_o;\n");
fprintf (fo, "input [31:0] lwb_dat_i;\n");
fprintf (fo, "output [31:0] swb_dat_o;\n\n");
GEN ("parameter Tp = 1;\n\n");
GEN ("input clk, rst;\n");
GEN ("input start_i;\t/* Module starts when set to 1 */ \n");
GEN ("output end_o;\t/* Set when module finishes, cleared upon start_i == 1 */\n");
GEN ("output busy_o;\t/* Set when module should not be interrupted */\n");
GEN ("\n/* Bus signals */\n");
GEN ("output lwb_cycstb_o, swb_cycstb_o;\n");
GEN ("input lwb_ack_i, swb_ack_i;\n");
GEN ("output [3:0] lwb_sel_o, swb_sel_o;\n");
GEN ("output [31:0] lwb_adr_o, swb_adr_o;\n");
GEN ("output lwb_linbrst_o, swb_linbrst_o;\n");
GEN ("input [31:0] lwb_dat_i;\n");
GEN ("output [31:0] swb_dat_o;\n\n");
 
fprintf (fo, "reg lwb_cycstb_o, swb_cycstb_o;\n");
fprintf (fo, "reg [31:0] lwb_adr_o, swb_adr_o;\n");
fprintf (fo, "reg [3:0] lwb_sel_o, swb_sel_o;\n");
fprintf (fo, "reg [31:0] swb_dat_o;\n");
fprintf (fo, "reg lwb_linbrst_o, swb_linbrst_o;\n");
GEN ("reg lwb_cycstb_o, swb_cycstb_o;\n");
GEN ("reg [31:0] lwb_adr_o, swb_adr_o;\n");
GEN ("reg [3:0] lwb_sel_o, swb_sel_o;\n");
GEN ("reg [31:0] swb_dat_o;\n");
GEN ("reg lwb_linbrst_o, swb_linbrst_o;\n");
if (ci || co) fprintf (fo, "\n/* module ports */\n");
if (ci || co) GEN ("\n/* module ports */\n");
if (ci) {
int first = 1;
fprintf (fo, "input [31:0]");
GEN ("input [31:0]");
for (i = 0; i < MAX_REGS; i++)
if (f->used_regs[i]) {
fprintf (fo, "%sr%i_i", first ? " " : ", ", i);
GEN ("%sr%i_i", first ? " " : ", ", i);
first = 0;
}
fprintf (fo, ";\n");
GEN (";\n");
}
 
if (co) {
int first = 1;
fprintf (fo, "output [31:0]");
GEN ("output [31:0]");
for (i = 0; i < MAX_REGS; i++)
if (f->lur[i] >= 0 && !f->saved_regs[i]) {
fprintf (fo, "%sr%i_o", first ? " " : ", ", i);
GEN ("%sr%i_o", first ? " " : ", ", i);
first = 0;
}
fprintf (fo, ";\n");
GEN (";\n");
}
 
if (f->nfdeps) {
fprintf (fo, "\n/* Function calls */\n");
fprintf (fo, "output [31:0] fr3_o");
for (i = 1; i < 6; i++) fprintf (fo, ", fr%i_o", i + 3);
fprintf (fo, ";\n");
if (log2(f->nfdeps) > 0) fprintf (fo, "output [%i:0] fid_o;\n", log2(f->nfdeps));
fprintf (fo, "output fstart_o;\n");
fprintf (fo, "input fend_i;\n");
GEN ("\n/* Function calls */\n");
GEN ("output [31:0] fr3_o");
for (i = 1; i < 6; i++) GEN (", fr%i_o", i + 3);
GEN (";\n");
if (log2(f->nfdeps) > 0) GEN ("output [%i:0] fid_o;\n", log2(f->nfdeps));
GEN ("output fstart_o;\n");
GEN ("input fend_i;\n");
}
/* Count loads & stores */
326,14 → 332,14
if (nloads) {
int first = 1;
int num = 0;
fprintf (fo, "\n/* internal registers for loads */\n");
GEN ("\n/* internal registers for loads */\n");
for (i = 0; i < f->nmsched; i++)
if (f->mtype[i] & MT_LOAD) {
fprintf (fo, "%st%x_%x", first ? "reg [31:0] " : ", ",
GEN ("%st%x_%x", first ? "reg [31:0] " : ", ",
REF_BB(f->msched[i]), REF_I(f->msched[i]));
 
if (num >= 8) {
fprintf (fo, ";\n");
GEN (";\n");
first = 1;
num = 0;
} else {
341,19 → 347,19
num++;
}
}
if (!first) fprintf (fo, ";\n");
if (!first) GEN (";\n");
}
 
/* Internal register for function return value */
if (f->nfdeps) {
fprintf (fo, "\n/* Internal register for function return value */\n");
fprintf (fo, "reg [31:0] fr11_r;\n");
GEN ("\n/* Internal register for function return value */\n");
GEN ("reg [31:0] fr11_r;\n");
}
fprintf (fo, "\n/* 'zero or one' hot state machines */\n");
if (nloads) fprintf (fo, "reg [%i:0] l_stb; /* loads */\n", nloads - 1);
if (nstores) fprintf (fo, "reg [%i:0] s_stb; /* stores */\n", nstores - 1);
fprintf (fo, "reg [%i:0] bb_stb; /* basic blocks */\n", f->num_bb - 1);
GEN ("\n/* 'zero or one' hot state machines */\n");
if (nloads) GEN ("reg [%i:0] l_stb; /* loads */\n", nloads - 1);
if (nstores) GEN ("reg [%i:0] s_stb; /* stores */\n", nstores - 1);
GEN ("reg [%i:0] bb_stb; /* basic blocks */\n", f->num_bb - 1);
 
{
int first = 2;
363,10 → 369,10
if (f->bb[b].insn[i].type & IT_COND
&& f->bb[b].insn[i].index != II_REG
&& f->bb[b].insn[i].index != II_LRBB) {
if (first == 2) fprintf (fo, "\n/* basic block condition wires */\n");
fprintf (fo, "%st%x_%x", first ? "wire " : ", ", b, i);
if (first == 2) GEN ("\n/* basic block condition wires */\n");
GEN ("%st%x_%x", first ? "wire " : ", ", b, i);
if (num >= 8) {
fprintf (fo, ";\n");
GEN (";\n");
first = 1;
num = 0;
} else {
374,9 → 380,9
num++;
}
}
if (!first) fprintf (fo, ";\n");
if (!first) GEN (";\n");
 
fprintf (fo, "\n/* forward declaration of normal wires */\n");
GEN ("\n/* forward declaration of normal wires */\n");
num = 0;
first = 1;
for (b = 0; b < f->num_bb; b++)
386,9 → 392,9
&& f->bb[b].insn[i].index != II_LRBB) {
/* Exclude loads */
if (f->bb[b].insn[i].type & IT_MEMORY && II_IS_LOAD (f->bb[b].insn[i].index)) continue;
fprintf (fo, "%st%x_%x", first ? "wire [31:0] " : ", ", b, i);
GEN ("%st%x_%x", first ? "wire [31:0] " : ", ", b, i);
if (num >= 8) {
fprintf (fo, ";\n");
GEN (";\n");
first = 1;
num = 0;
} else {
396,9 → 402,9
num++;
}
}
if (!first) fprintf (fo, ";\n");
if (!first) GEN (";\n");
fprintf (fo, "\n/* forward declaration registers */\n");
GEN ("\n/* forward declaration registers */\n");
num = 0;
first = 1;
for (b = 0; b < f->num_bb; b++)
405,9 → 411,9
for (i = 0; i < f->bb[b].ninsn; i++)
if (f->bb[b].insn[i].index == II_REG
&& f->bb[b].insn[i].index != II_LRBB) {
fprintf (fo, "%st%x_%x", first ? "reg [31:0] " : ", ", b, i);
GEN ("%st%x_%x", first ? "reg [31:0] " : ", ", b, i);
if (num >= 8) {
fprintf (fo, ";\n");
GEN (";\n");
first = 1;
num = 0;
} else {
415,7 → 421,7
num++;
}
}
if (!first) fprintf (fo, ";\n");
if (!first) GEN (";\n");
 
num = 0;
first = 1;
423,9 → 429,9
for (i = 0; i < f->bb[b].ninsn; i++)
if (f->bb[b].insn[i].index != II_REG
&& f->bb[b].insn[i].index == II_LRBB) {
fprintf (fo, "%st%x_%x", first ? "reg " : ", ", b, i);
GEN ("%st%x_%x", first ? "reg " : ", ", b, i);
if (num >= 8) {
fprintf (fo, ";\n");
GEN (";\n");
first = 1;
num = 0;
} else {
433,24 → 439,24
num++;
}
}
if (!first) fprintf (fo, ";\n");
if (!first) GEN (";\n");
}
 
if (nloads || nstores) fprintf (fo, "\n/* dependencies */\n");
if (nloads) fprintf (fo, "wire [%i:0] l_end = l_stb & {%i{lwb_ack_i}};\n",
if (nloads || nstores) GEN ("\n/* dependencies */\n");
if (nloads) GEN ("wire [%i:0] l_end = l_stb & {%i{lwb_ack_i}};\n",
nloads - 1, nloads);
if (nstores) fprintf (fo, "wire [%i:0] s_end = s_stb & {%i{swb_ack_i}};\n",
if (nstores) GEN ("wire [%i:0] s_end = s_stb & {%i{swb_ack_i}};\n",
nstores - 1, nstores);
if (ncalls) fprintf (fo, "wire [%i:0] f_end = f_stb & {%i{fend_i}};\n",
if (ncalls) GEN ("wire [%i:0] f_end = f_stb & {%i{fend_i}};\n",
ncalls - 1, ncalls);
 
fprintf (fo, "\n/* last dependency */\n");
fprintf (fo, "wire end_o = bb_stb[%i]", end_bb_no);
GEN ("\n/* last dependency */\n");
GEN ("wire end_o = bb_stb[%i]", end_bb_no);
if (end_bb->mdep) {
fprintf (fo, " && ");
GEN (" && ");
print_deps (fo, f, end_bb_no, end_bb->mdep, 0);
}
fprintf (fo, "wire busy_o = |bb_stb\n");
GEN ("wire busy_o = |bb_stb\n");
 
/* Is there a loop right at end? */
if (end_bb->next[0] >= 0) {
457,104 → 463,104
int bidx = branch_index (end_bb);
char t[30];
print_op_v (f, t, REF (end_bb_no, bidx), 1);
fprintf (fo, " && !%s", t);
GEN (" && !%s", t);
}
fprintf (fo, ";\n");
GEN (";\n");
fprintf (fo, "\n/* Basic block triggers */\n");
fprintf (fo, "wire [%2i:0] bb_start = {\n", f->num_bb - 1);
GEN ("\n/* Basic block triggers */\n");
GEN ("wire [%2i:0] bb_start = {\n", f->num_bb - 1);
for (b = f->num_bb - 1; b >= 0; b--) {
fprintf (fo, " /* bb_start[%2i] */ ", b);
if (f->bb[b].prev[0] < 0) fprintf (fo, "start_i");
GEN (" /* bb_start[%2i] */ ", b);
if (f->bb[b].prev[0] < 0) GEN ("start_i");
else {
cuc_bb *prev = &f->bb[f->bb[b].prev[0]];
int t;
if (prev->mdep) {
print_deps (fo, f, f->bb[b].prev[0], prev->mdep, 0);
fprintf (fo, " && ");
GEN (" && ");
}
fprintf (fo, "bb_stb[%i]", f->bb[b].prev[0]);
GEN ("bb_stb[%i]", f->bb[b].prev[0]);
if (prev->next[0] >= 0 && prev->next[1] >= 0) {
int bidx = branch_index (&f->bb[f->bb[b].prev[0]]);
assert (bidx >= 0);
fprintf (fo, " && ");
GEN (" && ");
t = prev->next[0] == b;
fprintf (fo, "%st%x_%x", t ? "" : "!", f->bb[b].prev[0], bidx);
GEN ("%st%x_%x", t ? "" : "!", f->bb[b].prev[0], bidx);
}
if (f->bb[b].prev[1] >= 0) {
prev = &f->bb[f->bb[b].prev[1]];
fprintf (fo, "\n || ");
GEN ("\n || ");
if (prev->mdep) {
print_deps (fo, f, f->bb[b].prev[1], prev->mdep, 0);
fprintf (fo, " && ");
GEN (" && ");
}
fprintf (fo, "bb_stb[%i]", f->bb[b].prev[1]);
GEN ("bb_stb[%i]", f->bb[b].prev[1]);
if (prev->next[0] >= 0 && prev->next[1] >= 0) {
int bidx = branch_index (&f->bb[f->bb[b].prev[1]]);
assert (bidx >= 0);
fprintf (fo, " && ");
GEN (" && ");
t = prev->next[0] == b;
fprintf (fo, "%st%x_%x", t ? "" : "!", f->bb[b].prev[1], bidx);
GEN ("%st%x_%x", t ? "" : "!", f->bb[b].prev[1], bidx);
}
}
}
if (b == 0) fprintf (fo, "};\n");
else fprintf (fo, ",\n");
if (b == 0) GEN ("};\n");
else GEN (",\n");
}
 
fprintf (fo, "\n/* Register the bb_start */\n");
fprintf (fo, "reg [%2i:0] bb_start_r;\n\n", f->num_bb - 1);
fprintf (fo, "always @(posedge rst or posedge clk)\n");
fprintf (fo, "begin\n");
fprintf (fo, " if (rst) bb_start_r <= #1 %i'b0;\n", f->num_bb);
fprintf (fo, " else if (end_o) bb_start_r <= #1 %i'b0;\n", f->num_bb);
fprintf (fo, " else bb_start_r <= #1 bb_start;\n");
fprintf (fo, "end\n");
GEN ("\n/* Register the bb_start */\n");
GEN ("reg [%2i:0] bb_start_r;\n\n", f->num_bb - 1);
GEN ("always @(posedge rst or posedge clk)\n");
GEN ("begin\n");
GEN (" if (rst) bb_start_r <= #Tp %i'b0;\n", f->num_bb);
GEN (" else if (end_o) bb_start_r <= #Tp %i'b0;\n", f->num_bb);
GEN (" else bb_start_r <= #Tp bb_start;\n");
GEN ("end\n");
 
fprintf (fo, "\n/* Logic */\n");
GEN ("\n/* Logic */\n");
/* output body */
for (b = 0; b < f->num_bb; b++) {
fprintf (fo, "\t\t/* BB%i */\n", b);
GEN ("\t\t/* BB%i */\n", b);
for (i = 0; i < f->bb[b].ninsn; i++)
print_insn_v (fo, f, b, i);
fprintf (fo, "\n");
GEN ("\n");
}
 
if (co) {
fprintf (fo, "\n/* Outputs */\n");
GEN ("\n/* Outputs */\n");
for (i = 0; i < MAX_REGS; i++)
if (f->lur[i] >= 0 && !f->saved_regs[i])
fprintf (fo, "assign r%i_o = t%x_%x;\n", i, REF_BB(f->lur[i]),
GEN ("assign r%i_o = t%x_%x;\n", i, REF_BB(f->lur[i]),
REF_I(f->lur[i]));
}
 
if (nstores) {
int cur_store = 0;
fprintf (fo, "\n/* Memory stores */\n");
fprintf (fo, "always @(posedge clk or posedge rst)\nbegin\n");
fprintf (fo, " if (rst) swb_dat_o <= #1 32'h0;\n");
GEN ("\n/* Memory stores */\n");
GEN ("always @(posedge clk or posedge rst)\nbegin\n");
GEN (" if (rst) swb_dat_o <= #Tp 32'h0;\n");
for (i = 0; i < f->nmsched; i++)
if (f->mtype[i] & MT_STORE) {
char t[30];
fprintf (fo, " else if (s_stb[%i]) swb_dat_o <= #1 %s;\n", cur_store++,
GEN (" else if (s_stb[%i]) swb_dat_o <= #Tp %s;\n", cur_store++,
print_op_v (f, t, f->msched[i], 0));
//printf ("msched[%i] = %x (mtype %x) %x\n", i, f->msched[i], f->mtype[i], f->INSN(f->msched[i]).op[0]);
}
fprintf (fo, "end\n");
GEN ("end\n");
}
 
if (nloads) {
int cur_load = 0;
fprintf (fo, "\n/* Load state machine */\n");
fprintf (fo, "always @(posedge clk or posedge rst)\n");
fprintf (fo, "begin\n");
fprintf (fo, " if (rst) begin\n");
fprintf (fo, " l_stb <= #1 %i'h0;\n", nloads);
fprintf (fo, " lwb_cycstb_o <= #1 1'b0;\n");
fprintf (fo, " lwb_sel_o[3:0] <= #1 4'b0000;\n");
fprintf (fo, " lwb_linbrst_o <= #1 1'b0;\n");
fprintf (fo, " lwb_adr_o <= #1 32'h0;\n");
fprintf (fo, " end else begin\n");
GEN ("\n/* Load state machine */\n");
GEN ("always @(posedge clk or posedge rst)\n");
GEN ("begin\n");
GEN (" if (rst) begin\n");
GEN (" l_stb <= #Tp %i'h0;\n", nloads);
GEN (" lwb_cycstb_o <= #Tp 1'b0;\n");
GEN (" lwb_sel_o[3:0] <= #Tp 4'b0000;\n");
GEN (" lwb_linbrst_o <= #Tp 1'b0;\n");
GEN (" lwb_adr_o <= #Tp 32'h0;\n");
GEN (" end else begin\n");
cucdebug (1, "loads \n");
for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_LOAD) {
char t[30];
561,50 → 567,50
dep_list *dep = f->INSN(f->msched[i]).dep;
cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
fprintf (fo, " if (");
GEN (" if (");
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
fprintf (fo, ") begin\n");
GEN (") begin\n");
print_turn_off_dep (fo, f, dep);
fprintf (fo, " l_stb[%i] <= #1 1'b1;\n", cur_load++);
fprintf (fo, " lwb_cycstb_o <= #1 1'b1;\n");
fprintf (fo, " lwb_sel_o[3:0] <= #1 4'b");
GEN (" l_stb[%i] <= #Tp 1'b1;\n", cur_load++);
GEN (" lwb_cycstb_o <= #Tp 1'b1;\n");
GEN (" lwb_sel_o[3:0] <= #Tp 4'b");
switch (f->mtype[i] & MT_WIDTH) {
case 1: fprintf (fo, "0001 << (%s & 32'h3);\n",
case 1: GEN ("0001 << (%s & 32'h3);\n",
print_op_v (f, t, f->msched[i], 1)); break;
case 2: fprintf (fo, "0011 << ((%s & 32'h1) << 1);\n",
case 2: GEN ("0011 << ((%s & 32'h1) << 1);\n",
print_op_v (f, t, f->msched[i], 1)); break;
case 4: fprintf (fo, "1111;\n"); break;
case 4: GEN ("1111;\n"); break;
default: assert (0);
}
fprintf (fo, " lwb_linbrst_o <= #1 1'b%i;\n",
GEN (" lwb_linbrst_o <= #Tp 1'b%i;\n",
(f->mtype[i] & MT_BURST) && !(f->mtype[i] & MT_BURSTE) ? 1 : 0);
fprintf (fo, " lwb_adr_o <= #1 t%x_%x & ~32'h3;\n",
GEN (" lwb_adr_o <= #Tp t%x_%x & ~32'h3;\n",
REF_BB(f->INSN(f->msched[i]).op[1]), REF_I(f->INSN(f->msched[i]).op[1]));
fprintf (fo, " end\n");
GEN (" end\n");
}
fprintf (fo, " if (l_end[%i]) begin\n", nloads - 1);
fprintf (fo, " l_stb <= #1 %i'h0;\n", nloads);
fprintf (fo, " lwb_cycstb_o <= #1 1'b0;\n");
fprintf (fo, " lwb_sel_o[3:0] <= #1 4'b0000;\n");
fprintf (fo, " lwb_linbrst_o <= #1 1'b0;\n");
fprintf (fo, " lwb_adr_o <= #1 32'h0;\n");
fprintf (fo, " end\n");
fprintf (fo, " end\n");
fprintf (fo, "end\n");
GEN (" if (l_end[%i]) begin\n", nloads - 1);
GEN (" l_stb <= #Tp %i'h0;\n", nloads);
GEN (" lwb_cycstb_o <= #Tp 1'b0;\n");
GEN (" lwb_sel_o[3:0] <= #Tp 4'b0000;\n");
GEN (" lwb_linbrst_o <= #Tp 1'b0;\n");
GEN (" lwb_adr_o <= #Tp 32'h0;\n");
GEN (" end\n");
GEN (" end\n");
GEN ("end\n");
}
 
if (nstores) {
int cur_store = 0;
fprintf (fo, "\n/* Store state machine */\n");
fprintf (fo, "always @(posedge clk or posedge rst)\n");
fprintf (fo, "begin\n");
fprintf (fo, " if (rst) begin\n");
fprintf (fo, " s_stb <= #1 %i'h0;\n", nstores);
fprintf (fo, " swb_cycstb_o <= #1 1'b0;\n");
fprintf (fo, " swb_sel_o[3:0] <= #1 4'b0000;\n");
fprintf (fo, " swb_linbrst_o <= #1 1'b0;\n");
fprintf (fo, " swb_adr_o <= #1 32'h0;\n");
fprintf (fo, " end else begin\n");
GEN ("\n/* Store state machine */\n");
GEN ("always @(posedge clk or posedge rst)\n");
GEN ("begin\n");
GEN (" if (rst) begin\n");
GEN (" s_stb <= #Tp %i'h0;\n", nstores);
GEN (" swb_cycstb_o <= #Tp 1'b0;\n");
GEN (" swb_sel_o[3:0] <= #Tp 4'b0000;\n");
GEN (" swb_linbrst_o <= #Tp 1'b0;\n");
GEN (" swb_adr_o <= #Tp 32'h0;\n");
GEN (" end else begin\n");
cucdebug (1, "stores \n");
for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_STORE) {
char t[30];
611,50 → 617,50
dep_list *dep = f->INSN(f->msched[i]).dep;
cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
fprintf (fo, " if (");
GEN (" if (");
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
fprintf (fo, ") begin\n");
GEN (") begin\n");
print_turn_off_dep (fo, f, dep);
fprintf (fo, " s_stb[%i] <= #1 1'b1;\n", cur_store++);
fprintf (fo, " swb_cycstb_o <= #1 1'b1;\n");
fprintf (fo, " swb_sel_o[3:0] <= #1 4'b");
GEN (" s_stb[%i] <= #Tp 1'b1;\n", cur_store++);
GEN (" swb_cycstb_o <= #Tp 1'b1;\n");
GEN (" swb_sel_o[3:0] <= #Tp 4'b");
switch (f->mtype[i] & MT_WIDTH) {
case 1: fprintf (fo, "0001 << (%s & 32'h3);\n",
case 1: GEN ("0001 << (%s & 32'h3);\n",
print_op_v (f, t, f->msched[i], 1)); break;
case 2: fprintf (fo, "0011 << ((%s & 32'h1) << 1);\n",
case 2: GEN ("0011 << ((%s & 32'h1) << 1);\n",
print_op_v (f, t, f->msched[i], 1)); break;
case 4: fprintf (fo, "1111;\n"); break;
case 4: GEN ("1111;\n"); break;
default: assert (0);
}
fprintf (fo, " swb_linbrst_o <= #1 1'b%i;\n",
GEN (" swb_linbrst_o <= #Tp 1'b%i;\n",
(f->mtype[i] & MT_BURST) && !(f->mtype[i] & MT_BURSTE) ? 1 : 0);
fprintf (fo, " swb_adr_o <= #1 t%x_%x & ~32'h3;\n",
GEN (" swb_adr_o <= #Tp t%x_%x & ~32'h3;\n",
REF_BB(f->INSN(f->msched[i]).op[1]), REF_I(f->INSN(f->msched[i]).op[1]));
fprintf (fo, " end\n");
GEN (" end\n");
}
fprintf (fo, " if (s_end[%i]) begin\n", nstores - 1);
fprintf (fo, " s_stb <= #1 %i'h0;\n", nstores);
fprintf (fo, " swb_cycstb_o <= #1 1'b0;\n");
fprintf (fo, " swb_sel_o[3:0] <= #1 4'b0000;\n");
fprintf (fo, " swb_linbrst_o <= #1 1'b0;\n");
fprintf (fo, " swb_adr_o <= #1 32'h0;\n");
fprintf (fo, " end\n");
fprintf (fo, " end\n");
fprintf (fo, "end\n");
GEN (" if (s_end[%i]) begin\n", nstores - 1);
GEN (" s_stb <= #Tp %i'h0;\n", nstores);
GEN (" swb_cycstb_o <= #Tp 1'b0;\n");
GEN (" swb_sel_o[3:0] <= #Tp 4'b0000;\n");
GEN (" swb_linbrst_o <= #Tp 1'b0;\n");
GEN (" swb_adr_o <= #Tp 32'h0;\n");
GEN (" end\n");
GEN (" end\n");
GEN ("end\n");
}
 
if (ncalls) {
int cur_call = 0;
fprintf (fo, "\n/* Function calls state machine */\n");
fprintf (fo, "always @(posedge clk or posedge rst)\n");
fprintf (fo, "begin\n");
fprintf (fo, " if (rst) begin\n");
fprintf (fo, " f_stb <= #1 %i'h0;\n", nstores);
for (i = 0; i < 6; i++) fprintf (fo, " fr%i_o <= #1 32'h0;\n", i + 3);
if (log2(ncalls)) fprintf (fo, " fid_o <= #1 %i'h0;\n", log2 (f->nfdeps));
fprintf (fo, " fstart_o <= #1 1'b0;\n");
//fprintf (fo, " f11_r <= #1 32'h0;\n");
fprintf (fo, " end else begin\n");
GEN ("\n/* Function calls state machine */\n");
GEN ("always @(posedge clk or posedge rst)\n");
GEN ("begin\n");
GEN (" if (rst) begin\n");
GEN (" f_stb <= #Tp %i'h0;\n", nstores);
for (i = 0; i < 6; i++) GEN (" fr%i_o <= #Tp 32'h0;\n", i + 3);
if (log2(ncalls)) GEN (" fid_o <= #Tp %i'h0;\n", log2 (f->nfdeps));
GEN (" fstart_o <= #Tp 1'b0;\n");
//GEN (" f11_r <= #Tp 32'h0;\n");
GEN (" end else begin\n");
cucdebug (1, "calls \n");
for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_CALL) {
char t[30];
661,45 → 667,368
dep_list *dep = f->INSN(f->msched[i]).dep;
cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
fprintf (fo, " if (");
GEN (" if (");
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
fprintf (fo, ") begin\n");
GEN (") begin\n");
print_turn_off_dep (fo, f, dep);
fprintf (fo, " f_stb[%i] <= #1 1'b1;\n", cur_call++);
fprintf (fo, " fstart_o <= #1 1'b1;\n");
GEN (" f_stb[%i] <= #Tp 1'b1;\n", cur_call++);
GEN (" fstart_o <= #Tp 1'b1;\n");
if (log2 (f->nfdeps))
fprintf (fo, " fid_o <= #1 %i'h%x;\n", log2 (f->nfdeps), func_index (f, f->msched[i]));
GEN (" fid_o <= #Tp %i'h%x;\n", log2 (f->nfdeps), func_index (f, f->msched[i]));
 
for (j = 0; j < 6; j++)
fprintf (fo, " fr%i_o <= #1 t%x_%x;\n", j + 3,
GEN (" fr%i_o <= #Tp t%x_%x;\n", j + 3,
REF_BB (f->msched[i]), REF_I (f->msched[i]) - 6 + i);
fprintf (fo, " end\n");
GEN (" end\n");
}
fprintf (fo, " if (f_end[%i]) begin\n", ncalls - 1);
fprintf (fo, " f_stb <= #1 %i'h0;\n", ncalls);
fprintf (fo, " f_start_o <= #1 1'b0;\n");
fprintf (fo, " end\n");
fprintf (fo, " end\n");
fprintf (fo, "end\n");
GEN (" if (f_end[%i]) begin\n", ncalls - 1);
GEN (" f_stb <= #Tp %i'h0;\n", ncalls);
GEN (" f_start_o <= #Tp 1'b0;\n");
GEN (" end\n");
GEN (" end\n");
GEN ("end\n");
}
 
fprintf (fo, "\n/* Basic blocks state machine */\n");
fprintf (fo, "always @(posedge clk or posedge rst)\n");
fprintf (fo, "begin\n");
fprintf (fo, " if (rst) bb_stb <= #1 %i'h%x;\n", f->num_bb, 0);
fprintf (fo, " else if (end_o) bb_stb <= #1 %i'h%x;\n", f->num_bb, 0);
GEN ("\n/* Basic blocks state machine */\n");
GEN ("always @(posedge clk or posedge rst)\n");
GEN ("begin\n");
GEN (" if (rst) bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
GEN (" else if (end_o) bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
for (i = 0; i < f->num_bb; i++) {
fprintf (fo, " else if (bb_start[%i]) begin\n", i);
fprintf (fo, " bb_stb <= #1 %i'h%x;\n", f->num_bb, 1 << i);
GEN (" else if (bb_start[%i]) begin\n", i);
GEN (" bb_stb <= #Tp %i'h%x;\n", f->num_bb, 1 << i);
}
fprintf (fo, " end else if (end_o) begin\n");
fprintf (fo, " bb_stb <= #1 %i'h%x;\n", f->num_bb, 0);
fprintf (fo, " end\n");
fprintf (fo, "end\n");
GEN (" end else if (end_o) begin\n");
GEN (" bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
GEN (" end\n");
GEN ("end\n");
 
/* output footer */
fprintf (fo, "\nendmodule\n");
GEN ("\nendmodule\n");
 
fclose (fo);
}
 
void generate_main (int nfuncs, cuc_func **f, char *filename)
{
FILE *fo;
int i, j, nrf, first;
char tmp[256];
int ncallees[MAX_FUNCS];
int maxncallees = 0;
sprintf (tmp, "%s.v", filename);
 
for (i = 0, nrf = 0; i < nfuncs; i++) {
if (f[i]) f[i]->tmp = nrf++;
ncallees[i] = 0;
}
if (!nrf) return;
 
for (i = 0; i < nfuncs; i++) if (f[i])
for (j = 0; j < f[i]->nfdeps; j++)
ncallees[f[i]->fdeps[j]->tmp]++;
for (i = 0; i < nrf; i++)
if (maxncallees < ncallees[i]) maxncallees = ncallees[i];
log ("Generating verilog file \"%s\"\n", tmp);
printf ("Generating verilog file \"%s\"\n", tmp);
if ((fo = fopen (tmp, "wt+")) == NULL) {
fprintf (stderr, "Cannot open '%s'\n", tmp);
exit (1);
}
 
/* output header */
GEN ("/* %s -- generated by OpenRISC Custom Unit Compiler\n", tmp);
GEN (" (C) 2002 OpenCores http://www.opencores.org/ */\n\n");
GEN ("/* Includes %i functions:", nrf);
for (i = 0; i < nfuncs; i++) if (f[i])
GEN ("\n%s", prof_func[i].name);
GEN (" */\n\n");
 
GEN ("`include \"timescale.v\"\n\n");
GEN ("module %s (clk, rst,\n", filename);
GEN (" /* Load and store master Wishbone ports */\n");
GEN (" lwb_adr_o, lwb_dat_i, lwb_cycstb_o,\n");
GEN (" lwb_sel_o, lwb_linbrst_o, lwb_ack_i,\n");
GEN (" swb_adr_o, swb_dat_o, swb_cycstb_o,\n");
GEN (" swb_sel_o, swb_linbrst_o, swb_ack_i,\n\n");
GEN (" /* cuc interface */\n");
GEN (" cuc_stb_i, cuc_adr_i, cuc_dat_i, cuc_dat_o, cuc_we_i, cuc_ack_o);\n\n");
 
GEN ("parameter Tp = 1;\n");
GEN ("\n/* module ports */\n");
GEN ("input clk, rst, cuc_stb_i, cuc_we_i;\n");
GEN ("input lwb_ack_i, swb_ack_i, lwb_linbrst_o, swb_linbrst_o;\n");
GEN ("output lwb_cycstb_o, lwb_linbrst_o;\n");
GEN ("output swb_cycstb_o swb_linbrst_o;\n");
GEN ("output cuc_ack_o;\n");
GEN ("output [3:0] lwb_sel_o, swb_sel_o;\n");
GEN ("output [31:0] lwb_adr_o, swb_adr_o, swb_dat_o, cuc_dat_o;\n");
GEN ("input [15:0] cuc_adr_i;\n");
GEN ("input [31:0] lwb_dat_i, cuc_dat_i;\n\n");
 
/* Function specific data */
for (i = 0; i < nfuncs; i++) if (f[i]) {
int ci = 0, co = 0;
int fn = f[i]->tmp;
GEN ("\n/* Registers for function %s */\n", prof_func[i].name);
GEN ("wire i%i_we = cuc_stb_i && cuc_we_i && cuc_adr_i[15:6] == %i;\n", fn, fn);
GEN ("wire i%i_re = cuc_stb_i && !cuc_we_i && cuc_adr_i[15:6] == %i;\n", fn, fn);
GEN ("wire i%i_start, i%i_finish;\n\n", fn, fn);
 
GEN ("assign i%i_start = i%i_go_bsy & cuc_ack_o;\n", fn, fn);
GEN ("wire main_start%i = start_i && cuc_adr_i[15:6] == %i && cuc_adr_i[5:0] == %i && i%i_we;\n",
i, i, j, i);
GEN ("wire main_end%i = end_i && cuc_adr_i[15:6] == %i && cuc_adr_i[5:0] == %i && i%i_we;\n",
i, i, j, i);
GEN ("\nalways @(posedge clk or posedge rst)\n");
GEN (" begin\n");
GEN (" if (rst) cuc_ack_o <= #Tp 1'b0;\n");
GEN (" else if ((i%i_we | i%i_re) & !i%i_go_bsy)\n", fn, fn, fn);
GEN (" cuc_ack_o <= #Tp ~cuc_ack_o;\n");
GEN (" end\n");
 
GEN ("\nalways @(posedge clk or posedge rst)\n");
GEN ("begin\n");
GEN (" if (rst) i%i_go_bsy <= #Tp 1'b0;\n", fn);
GEN (" else if (i%i_we && (cuc_adr_i[15:6] == %i)) i%i_go_bsy <= #Tp 1'b1;\n", fn, fn, fn);
GEN (" else if (i%i_finish) i%i_go_bsy <= #Tp 1'b0;\n", fn, fn);
GEN ("end\n");
 
for (j = 0, first = 1; j < MAX_REGS; j++) if (f[i]->used_regs[j]) {
GEN ("%s i%i_r%ii", first ? "\n/* inputs */\nreg [31:0]" : ",", fn, j);
first = 0;
ci++;
}
if (ci) GEN (";\n");
 
for (j = 0, first = 1; j < MAX_REGS; j++)
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j]) {
GEN ("%s i%i_r%io", first ? "\n/* outputs */\nreg [31:0]" : ",", fn, j);
first = 0;
co++;
}
if (co) GEN (";\n");
//GEN ("wire [31:0] i%i_r11;\n\n");
 
if (ci) {
GEN ("\n/* write register access */\n");
GEN ("always @(posedge clk or posedge rst)\n");
GEN ("begin\n");
GEN (" if (rst) begin\n");
for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
GEN (" i%i_r%-2i <= #Tp 32'h0;\n", fn, j);
GEN (" end else if (!i%i_go_bsy && i%i_we)\n", fn, fn);
GEN (" case (cuc_adr_i[5:0])\n");
for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
GEN (" %-2i: r%i <= #Tp cuc_dat_i;\n", j, j);
GEN (" endcase\n");
GEN ("end\n");
}
 
GEN ("\n\n");
}
 
/* Generate machine for reading all function registers. First registers can delay
transfer till function completion */
{
int co;
GEN ("/* read register access - data */\n");
GEN ("always @(posedge clk or posedge rst)\n");
GEN (" if (rst) cuc_dat_o <= #Tp 32'h0;\n");
GEN (" else if (cuc_stb_i && cuc_we_i) begin\n");
GEN (" ");
 
for (i = 0; i < nfuncs; i++) if (f[i]) {
co = 0;
for (j = 0; j < MAX_REGS; j++)
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j]) co++;
GEN ("if (cuc_addr_i[15:6] == %i) begin\n", f[i]->tmp);
if (co) {
first = 1;
GEN (" case (cuc_adr_i[5:0])\n");
for (j = 0; j < MAX_REGS; j++)
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
GEN (" %-2i: cuc_dat_o <= #Tp i%i_r%i;\n", j, f[i]->tmp, j);
GEN (" endcase\n");
} else {
/* no registers => just write an acknowledge */
GEN (" cuc_dat_o <= #Tp 32'hx;\n");
}
GEN (" end else ");
}
GEN ("cuc_dat_o <= #Tp 32'hx;\n");
GEN (" else cuc_dat_o <= #Tp 32'hx;\n");
GEN ("end\n");
GEN ("\n/* read register access - acknowledge */\n");
GEN ("always @(cuc_stb_i or cuc_we_i or cuc_adr_i");
for (i = 0; i < nrf; i++) GEN (" or main_end%i", i);
GEN (")\n");
GEN (" if (cuc_stb_i && cuc_we_i) begin\n");
GEN (" ");
 
for (i = 0; i < nfuncs; i++) if (f[i]) {
GEN (" if (cuc_addr_i[15:6] == %i) cuc_ack_o <= #Tp main_end%i;\n",
f[i]->tmp, f[i]->tmp);
GEN (" else ");
}
GEN ("cuc_ack_o <= #Tp 1'b0;\n");
GEN (" else cuc_ack_o <= #Tp 1'b0;\n");
GEN ("end\n");
}
 
for (j = 0; j < 2; j++) {
char t = j ? 's' : 'l';
GEN ("\n/* %s Wishbone bridge */\n", j ? "store" : "load");
GEN ("reg [%2i:0] %cm_sel;\n", log2 (nrf), t);
GEN ("reg [%2i:0] %cm_bid;\n", log2 (nrf), t);
 
GEN ("\n/* highest bid */\n");
GEN ("always @(");
for (i = 0; i < nrf; i++) GEN ("%si%i_%cwb_cycstb", i > 0 ? " or " : "", i, t);
GEN (")\n");
for (i = 0; i < nrf; i++) GEN (" %sif (i%i_%cwb_cycstb) %cm_bid <= %i'h%x;\n",
i ? "else " : "", i, t, t, log2 (nrf) + 1, i);
 
GEN ("\n/* selected transfer */\n");
GEN ("always @(posedge clk or posedge rst)\n");
GEN (" if (rst) %cm_sel <= #Tp %cm_sel <= #Tp %i'h0;\n", t, t, log2 (nrf) + 1);
GEN (" else if (%cwb_ack_i) %cm_sel <= #Tp %i'h0;\n", t, t, log2 (nrf) + 1);
GEN (" else if (!%ccyc_ip) %cm_sel <= #Tp %cm_bid;\n", t, t, t);
 
GEN ("\n/* Cycle */\n");
GEN ("assign %cwb_cyc_o = (lwb_cycstb | swb_cycstb);\n", t);
GEN ("assign %cwb_stb_o = %cwb_stb_o;\n", t, t);
GEN ("\nalways @(posedge clk or posedge rst)\n");
GEN (" if (rst) %ccyc_ip <= #Tp 1'b0;\n", t);
GEN (" else if (%cwb_ack_i) %ccyc_ip <= #Tp 1'b0;\n", t, t);
GEN (" else %ccyc_ip <= #Tp %cwb_cyc_o;\n", t, t);
}
 
GEN ("\n/* Acknowledge */\n");
for (i = 0; i < nrf; i++)
GEN ("assign i%i_swb_ack = ((sm_bid == %i & !scyc_ip) | sm_sel == %i) & swb_ack_i;\n", i, i, i);
 
GEN ("\n/* Data */\n");
for (i = 0; i < nrf; i++) GEN ("wire [31:0] i%i_swb_dat;\n", i);
GEN ("\nassign swb_dat_o = ");
for (i = 0; i < nrf - 1; i++)
GEN ("\n sm_bid == %i ? i%i_swb_dat : ", i, i);
GEN ("i%i_swb_dat;\n\n", nrf - 1);
 
for (i = 0; i < nrf; i++) GEN ("wire [31:0] i%i_lwb_dat = lwb_dat_i;\n", i);
GEN ("\n/* selects */\n");
for (i = 0; i < nrf; i++) GEN ("wire [3:0] i%i_swb_sel, i%i_lwb_sel;\n", i, i);
GEN ("\nassign swb_sel_o = ");
for (i = 0; i < nrf - 1; i++)
GEN ("\n sm_bid == %i ? i%i_swb_sel : ", i, i);
GEN ("i%i_swb_sel;\n", nrf - 1);
GEN ("\nassign lwb_sel_o = ");
for (i = 0; i < nrf - 1; i++)
GEN ("\n lm_bid == %i ? i%i_lwb_sel : ", i, i);
GEN ("i%i_lwb_sel;\n", nrf - 1);
GEN ("\n/* write enable */\n");
for (i = 0; i < nrf; i++) GEN ("wire i%i_swb_we, i%i_lwb_we;\n", i, i);
GEN ("\nassign swb_we_o = ");
for (i = 0; i < nrf - 1; i++) GEN ("\n sm_bid == %i ? i%i_swb_we : ", i, i);
GEN ("i%i_swb_we;\n", nrf - 1);
 
GEN ("\nassign lwb_we_o = ");
for (i = 0; i < nrf - 1; i++) GEN ("\n lm_bid == %i ? i%i_lwb_we : ", i, i);
GEN ("i%i_lwb_we;\n", nrf - 1);
 
GEN ("\n/* burst enable */\n");
for (i = 0; i < nrf; i++) GEN ("wire i%i_swb_linbrst, i%i_lwb_linbrst;\n", i, i);
GEN ("\nassign swb_linbrst_o = ");
for (i = 0; i < nrf - 1; i++) GEN ("\n sm_bid == %i ? i%i_swb_linbrst : ", i, i);
GEN ("i%i_swb_linbrst;\n", nrf - 1);
GEN ("\n\nassign lwb_linbrst_o = ");
for (i = 0; i < nrf - 1; i++) GEN ("\n lm_bid == %i ? i%i_lwb_linbrst : ", i, i);
GEN ("i%i_lwb_linbrst;\n", nrf - 1);
/* start/end signals */
GEN ("\n\n/* start/end signals */\n");
 
for (i = 0, first = 1; i < nrf; i++) {
GEN ("%si%i_current == %i && i%i_end", first ? "assign end_o = " : "\n || ", i, i, i);
first = 0;
}
GEN (";\n\n");
 
for (i = 0, j = 0; i < nfuncs; i++) if (f[i]) {
if (log2 (ncallees[i])) {
GEN ("reg [%i:0] i%i_start_bid;\n", log2 (ncallees[i]), j);
GEN ("always @(start%i", f[i]->tmp);
for (j = 0, first = 1; j < f[i]->nfdeps; j++)
if (f[i]->fdeps[j]) GEN (", ");
GEN (")\n");
GEN ("begin !!!\n"); //TODO
GEN (" \n");
GEN ("end\n");
}
GEN ("wire i%i_start = start_i;\n", j);
j++;
}
GEN ("\n");
 
for (i = 0, first = 1; i < nrf; i++) {
if (log2 (maxncallees + 1))
GEN ("wire [%i:0] i%i_current = i%i_busy ? i%i_current_r : i%i_start_bid;\n",
log2 (maxncallees + 1), i, i, i, i, i);
else GEN ("wire i%i_current = 0;\n", i);
}
GEN ("\n");
for (i = 0, first = 1; i < nrf; i++) {
int rf;
/* Find real function */
for (rf = 0; rf < nfuncs; rf++) if (f[rf]->tmp == i) break;
/* Find first register, use r31, if none */
for (j = 0; j < MAX_REGS; j++) if (f[rf]->used_regs[j]) break;
GEN ("/* Function %s */\n", prof_func[rf].name);
GEN ("reg main_start%i_r;\n", i);
GEN ("always @(posedge clk or posedge rst)\n");
GEN (" if (rst) main_start%i_r <= #Tp 1'b0;\n", i);
GEN (" else if (main_start%i && (i%i_start_bid < %i || i%i_busy))",
i, i, i, ncallees[i], i);
GEN (" main_start%i_r <= #Tp 1'b1;\n", i);
GEN (" else if (main_end%i && i%i_re) main_start%i_r <= #Tp 1'b0;\n", i, i, i);
}
 
for (i = 0; i < nfuncs; i++) if (f[i]) {
int nf = f[i]->tmp;
GEN ("\n%s i%i(.clk(clk), .rst(rst),\n", prof_func[i].name, nf);
GEN ("");
GEN (" .lwb_adr_o(i%i_lwb_adr), .lwb_dat_i(i%i_lwb_dat), .lwb_cycstb_o(i%i_lwb_cycstb),\n",
nf, nf, nf);
GEN (" .lwb_sel_o(i%i_lwb_sel), .lwb_linbrst_o(i%i_lwb_linbrst), .lwb_ack_i(i%i_lwb_ack),\n",
nf, nf, nf);
GEN (" .swb_adr_o(i%i_swb_adr), .swb_dat_o(i%i_swb_dat), .swb_cycstb_o(i%i_swb_cycstb),\n",
nf, nf, nf);
GEN (" .swb_sel_o(i%i_swb_sel), .swb_linbrst_o(i%i_swb_linbrst), .swb_ack_i(i%i_swb_ack),\n",
nf, nf, nf);
GEN (" ");
for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
GEN (".r%i_i(i%i_r%ii), ", j, nf, j);
 
GEN ("\n ");
for (j = 0, first = 1; j < MAX_REGS; j++)
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
GEN (".r%i_o(i%i_r%io), ", j, nf, j);
GEN ("\n .start_i(i%i_start), .end_o(i%i_end));\n", nf, nf);
}
 
/* output footer */
GEN ("\nendmodule\n");
 
fclose (fo);
}
 
/trunk/or1ksim/cuc/cuc.c
23,6 → 23,7
#include <stdlib.h>
#include <stdarg.h>
#include <assert.h>
#include <ctype.h>
#include "sim-config.h"
#include "cuc.h"
#include "insn.h"
69,6 → 70,7
remove_dead (func);
if (cuc_debug >= 5) print_cuc_bb (func, "AFTER_DEAD");
remove_trivial_regs (func);
set_io (func);
if (cuc_debug >= 2) print_cuc_bb (func, "AFTER_TRIVIAL");
add_latches (func);
if (cuc_debug >= 1) print_cuc_bb (func, "AFTER_LATCHES");
163,6 → 165,7
remove_dead (func);
if (cuc_debug >= 5) print_cuc_bb (func, "AFTER_DEAD");
remove_trivial_regs (func);
set_io (func);
if (cuc_debug >= 2) print_cuc_bb (func, "AFTER_TRIVIAL");
#if 0
173,7 → 176,6
timings.preroll = timings.unroll = 1;
timings.nshared = 0;
add_latches (func);
set_io (func);
 
if (cuc_debug >= 1) print_cuc_bb (func, "AFTER_LATCHES");
analyse_timings (func, &timings);
218,11 → 220,11
do {
pt = cpt;
cpt = preunroll_bb (tmp1, saved, &t[nt++], b, ++j, i);
} while (j <= MAX_PREROLL && pt->new_time >= cpt->new_time);
} while (j <= MAX_PREROLL && pt->new_time > cpt->new_time);
i++;
ut = cut;
cut = preunroll_bb (tmp1, saved, &t[nt++], b, 1, i);
} while (i <= MAX_UNROLL && ut->new_time >= cut->new_time);
} while (i <= MAX_UNROLL && ut->new_time > cut->new_time);
 
/* Sort the timings */
#if 0
353,7 → 355,7
}
 
/* Generates a function, based on specified parameters */
cuc_func *generate_function (cuc_func *rf, char *name)
cuc_func *generate_function (cuc_func *rf, char *name, char *cut_filename)
{
int b, i, j;
char tmp[256];
361,14 → 363,10
cuc_func *f;
assert (f = dup_func (rf));
 
if (cuc_debug >= 2) print_cuc_bb (f, "BEFORE_GENERATE");
log ("Generating function %s.\n", name);
printf ("Generating function %s.\n", name);
 
if (cuc_debug >= 2) print_cuc_bb (f, "BEFORE_GENERATE");
add_latches (f);
set_io (f);
if (cuc_debug >= 1) print_cuc_bb (f, "AFTER_LATCHES");
format_func_options (tmp, rf);
if (strlen (tmp)) printf ("Applying options: %s\n", tmp);
else printf ("Using basic options.\n");
390,6 → 388,8
assert (0);
//csm_gen (f, rf, st->nshared, st->shared);
}
add_latches (f);
if (cuc_debug >= 1) print_cuc_bb (f, "AFTER_LATCHES");
analyse_timings (f, &tt);
add_memory_dep (f, f->memory_order);
if (cuc_debug >= 7) print_cuc_bb (f, "AFTER_MEMORY_DEP");
397,7 → 397,9
if (cuc_debug >= 8) print_cuc_bb (f, "AFTER_DATA_DEP");
schedule_memory (f, f->memory_order);
if (cuc_debug >= 7) print_cuc_bb (f, "AFTER_SCHEDULE_MEM");
output_verilog (f, name);
sprintf (tmp, "%s%s", cut_filename, name);
output_verilog (f, tmp);
return f;
}
 
522,10 → 524,18
{
int i, j;
char tmp1[256];
char filename_cut[256];
for (i = 0; i < 256; i++) {
if (isalpha(filename[i])) filename_cut[i] = filename[i];
else {
filename_cut[i] = '\0';
break;
}
}
 
printf ("Entering OpenRISC Custom Unit Compiler command prompt\n");
printf ("Using profile file \"%s\" and memory profile file \"%s\".\n", config.sim.prof_fn, config.sim.mprof_fn);
sprintf (tmp1, "%s.log", filename);
sprintf (tmp1, "%s.log", filename_cut);
printf ("Analyzing. (log file \"%s\").\n", tmp1);
assert (flog = fopen (tmp1, "wt+"));
 
632,7 → 642,7
/* check for function dependencies */
for (i = 0; i < prof_nfuncs; i++)
if (func[i]) func[i]->tmp = func_v[i];
for (i = 0; i < prof_nfuncs; i++)
for (i = 0; i < prof_nfuncs; i++) if (func[i])
for (j = 0; j < func[i]->nfdeps; j++)
if (!func[i]->fdeps[j] || !func[i]->fdeps[j]->tmp) {
printf ("Function %s must be selected for translation (required by %s)\n",
640,8 → 650,9
goto wait_command;
}
for (i = 0; i < prof_nfuncs; i++)
if (func[i] && func_v[i]) generate_function (func[i], prof_func[i].name);
if (func[i] && func_v[i]) generate_function (func[i], prof_func[i].name, filename_cut);
generate_main (prof_nfuncs, func, filename_cut);
 
/* select command */
} else if (strncmp (tmp1, "s", 1) == 0 || strncmp (tmp1, "select", 6) == 0) {
char tmp[50], ch;
681,6 → 692,15
} else printf ("Invalid function.\n");
}
 
/* selectall command */
} else if (strcmp (tmp1, "sa") == 0 || strcmp (tmp1, "selectall") == 0) {
char tmp[50], ch;
int p, o, b, f;
for (f = 0; f < prof_nfuncs; f++) if (func[f]) {
func_v[f] = 1;
printf ("Function %s selected for translation.\n", prof_func[f].name);
}
/* unselect command */
} else if (strncmp (tmp1, "u", 1) == 0 || strncmp (tmp1, "unselect", 8) == 0) {
char tmp[50], ch;
/trunk/or1ksim/testbench/support/support.h
10,7 → 10,7
#include <limits.h>
 
#if OR1K
#include <_ansi.h>
//#include <_ansi.h>
 
/* Register access macros */
#define REG8(add) *((volatile unsigned char *)(add))
/trunk/or1ksim/testbench/mul.c
95,6 → 95,9
unsigned t2;
unsigned t3;
printf ("%08x\n", MACRC);
MAC (888888887, 0x87654321);
printf ("%08x\n", MACRC);
exit (0);
t1 = test_mul (888888887, 0x87654321);
t2 = test_mac (888888887, 0x87654321);
t3 = test_mul_mac (888888887, 0x87654321);

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