OpenCores

/openrisc/trunk/or1ksim/sim-config.h

53,13 → 53,17

/openrisc/trunk/or1ksim/ltmain.sh

1,6 → 1,6

65,7 → 65,7

73,9 → 73,9

5033,7 → 5033,10

5344,19 → 5347,19

5893,6 → 5896,7

6206,6 → 6210,9

/openrisc/trunk/or1ksim/configure.ac

28,7 → 28,7

352,31 → 352,33

/openrisc/trunk/or1ksim/doc/or1ksim.info

64,7 → 64,7

81,7 → 81,7

243,7 → 243,7

487,11 → 487,13

506,17 → 508,28

3667,7 → 3680,7

3724,15 → 3737,15

4071,43 → 4084,43

/openrisc/trunk/or1ksim/doc/or1ksim.texi

599,7 → 599,13

615,16 → 621,31

/openrisc/trunk/or1ksim/doc/version.texi

1,4 → 1,4

/openrisc/trunk/or1ksim/or1ksim.h

46,16 → 46,19

/openrisc/trunk/or1ksim/ChangeLog

1,3 → 1,22

19,7 → 38,7

29,7 → 48,7

/openrisc/trunk/or1ksim/testsuite/libsim.tests/upcalls.cfg

0,0 → 1,155

/openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in

210,8 → 210,13

/openrisc/trunk/or1ksim/testsuite/libsim.tests/int-edge.exp

0,0 → 1,130

/openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.am

28,5 → 28,10

/openrisc/trunk/or1ksim/testsuite/libsim.tests/int-level.exp

0,0 → 1,113

/openrisc/trunk/or1ksim/testsuite/libsim.tests/int-edge.cfg

0,0 → 1,160

/openrisc/trunk/or1ksim/testsuite/libsim.tests/int-level.cfg

0,0 → 1,160

/openrisc/trunk/or1ksim/testsuite/libsim.tests/upcalls.exp

0,0 → 1,78

/openrisc/trunk/or1ksim/testsuite/test-code-or1k/m4/libtool.m4

2470,13 → 2470,10

2488,6 → 2485,18

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3760,7 → 3769,7

4185,6 → 4194,9

4249,6 → 4261,9

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4606,6 → 4621,7

4844,7 → 4860,7

/openrisc/trunk/or1ksim/testsuite/test-code-or1k/m4/ltversion.m4

9,15 → 9,15

/openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure

2045,8 → 2045,8

4179,7 → 4179,7

7390,6 → 7390,9

7572,7 → 7575,7

7747,6 → 7750,7

8161,7 → 8165,7

9123,13 → 9127,10

9141,6 → 9142,18

10074,7 → 10087,7

10170,7 → 10183,7

12671,7 → 12684,7

13591,6 → 13604,7

13607,6 → 13621,7

/openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.in

278,6 → 278,7

291,7 → 292,8

/openrisc/trunk/or1ksim/testsuite/test-code-or1k/kbdtest/kbdtest.c

69,6 → 69,44

205,7 → 243,7

225,7 → 263,7

307,7 → 345,7

/openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/upcall-basic.c

0,0 → 1,199

openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/upcall-basic.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in =================================================================== --- openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in (nonexistent) +++ openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in (revision 93) @@ -0,0 +1,523 @@ +# Makefile.in generated by automake 1.11.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, +# Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + +# Makefile.am for or1ksim OR1K test program: upcalls + +# Copyright (C) Embecosm Limited, 2010 + +# Contributor Jeremy Bennett + +# This file is part of OpenRISC 1000 Architectural Simulator. + +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 3 of the License, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. 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\ + installcheck-am installdirs maintainer-clean \ + maintainer-clean-generic mostlyclean mostlyclean-compile \ + mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \ + tags uninstall uninstall-am + + +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: Index: openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.am =================================================================== --- openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.am (nonexistent) +++ openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.am (revision 93) @@ -0,0 +1,45 @@ +# Makefile.am for or1ksim OR1K test program: upcalls + +# Copyright (C) Embecosm Limited, 2010 + +# Contributor Jeremy Bennett + +# This file is part of OpenRISC 1000 Architectural Simulator. + +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 3 of the License, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +# You should have received a copy of the GNU General Public License along +# with this program. If not, see . */ + +# ----------------------------------------------------------------------------- +# This code is commented throughout for use with Doxygen. +# ----------------------------------------------------------------------------- + + +# Test programs for upcalls +check_PROGRAMS = upcall-basic \ + upcall-misaligned + +# Basic test +upcall_basic_SOURCES = upcall-basic.c + +upcall_basic_LDFLAGS = -T$(srcdir)/../default.ld + +upcall_basic_LDADD = ../except/except.lo \ + ../support/libsupport.la + +# Test for misaligned calls +upcall_misaligned_SOURCES = upcall-misaligned.c + +upcall_misaligned_LDFLAGS = -T$(srcdir)/../default.ld + +upcall_misaligned_LDADD = ../except/except.lo \ + ../support/libsupport.la

openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.am Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/upcall-misaligned.c =================================================================== --- openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/upcall-misaligned.c (nonexistent) +++ openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/upcall-misaligned.c (revision 93) @@ -0,0 +1,290 @@ +/* upcall-misaligned.c. Test of Or1ksim misaligned handling of upcalls + + Copyright (C) 2010 Embecosm Limited + + Contributors various OpenCores participants + Contributor Jeremy Bennett + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + +/* ---------------------------------------------------------------------------- + This code is commented throughout for use with Doxygen. + --------------------------------------------------------------------------*/ + +#include "support.h" +#include "spr-defs.h" +#include "board.h" + + +/*!Alignment exception handler defined here. */ +unsigned long excpt_align; + +/*!Flag set if we get a misaligned access */ +static int misaligned_p; + +/* --------------------------------------------------------------------------*/ +/*!Write a memory mapped byte register + + Report the result, noting if we get a misalignment exception. + + @param[in] addr Memory mapped address + @param[in] value Value to set */ +/* --------------------------------------------------------------------------*/ +static void +setreg8 (unsigned long int addr, + unsigned char value) +{ + *((volatile unsigned char *) addr) = value; + + if (misaligned_p) + { + printf ("Writing byte at 0x%08lx: misalignment exception.\n", addr); + misaligned_p = 0; + } + else + { + printf ("Wrote byte at 0x%08lx = 0x%02x.\n", addr, value); + } +} /* setreg8 () */ + + +/* --------------------------------------------------------------------------*/ +/*!Write a memory mapped half word register + + Report the result, noting if we get a misalignment exception. + + @param[in] addr Memory mapped address + @param[in] value Value to set */ +/* --------------------------------------------------------------------------*/ +static void +setreg16 (unsigned long int addr, + unsigned short int value) +{ + *((volatile unsigned short int *) addr) = value; + + if (misaligned_p) + { + printf ("Writing half word at 0x%08lx: misalignment exception.\n", addr); + misaligned_p = 0; + } + else + { + printf ("Wrote half word at 0x%08lx = 0x%04x.\n", addr, value); + } +} /* setreg16 () */ + + +/* --------------------------------------------------------------------------*/ +/*!Write a memory mapped full word register + + Report the result, noting if we get a misalignment exception. + + @param[in] addr Memory mapped address + @param[in] value Value to set */ +/* --------------------------------------------------------------------------*/ +static void +setreg32 (unsigned long int addr, + unsigned long int value) +{ + *((volatile unsigned long int *) addr) = value; + + if (misaligned_p) + { + printf ("Writing full word at 0x%08lx: misalignment exception.\n", addr); + misaligned_p = 0; + } + else + { + printf ("Wrote full word at 0x%08lx = 0x%08lx.\n", addr, value); + } +} /* setreg32 () */ + + +/* --------------------------------------------------------------------------*/ +/*!Read a memory mapped byte register + + Report the result, noting if we get a misalignment exception. + + @param[in] addr Memory mapped address + + @return Value read */ +/* --------------------------------------------------------------------------*/ +unsigned char +getreg8 (unsigned long int addr) +{ + unsigned char res = *((volatile unsigned char *) addr); + + if (misaligned_p) + { + printf ("Reading byte at 0x%08lx: misalignment exception.\n", addr); + misaligned_p = 0; + } + else + { + printf ("Read byte at 0x%08lx = 0x%02x.\n", addr, res); + } + + return res; + +} /* getreg8 () */ + + +/* --------------------------------------------------------------------------*/ +/*!Read a memory mapped half word register + + Report the result, noting if we get a misalignment exception. + + @param[in] addr Memory mapped address + + @return Value read */ +/* --------------------------------------------------------------------------*/ +unsigned short int +getreg16 (unsigned long int addr) +{ + unsigned short int res = *((volatile unsigned short int *) addr); + + if (misaligned_p) + { + printf ("Reading half word at 0x%08lx: misalignment exception.\n", addr); + misaligned_p = 0; + } + else + { + printf ("Read half word at 0x%08lx = 0x%04x.\n", addr, res); + } + + return res; + +} /* getreg16 () */ + + +/* --------------------------------------------------------------------------*/ +/*!Read a memory mapped full word register + + Report the result, noting if we get a misalignment exception. + + @param[in] addr Memory mapped address + + @return Value read */ +/* --------------------------------------------------------------------------*/ +unsigned long int +getreg32 (unsigned long int addr) +{ + unsigned long int res = *((volatile unsigned long int *) addr); + + if (misaligned_p) + { + printf ("Reading full word at 0x%08lx: misalignment exception.\n", addr); + misaligned_p = 0; + } + else + { + printf ("Read full word at 0x%08lx = 0x%08lx.\n", addr, res); + } + + return res; + +} /* getreg32 () */ + + +/* --------------------------------------------------------------------------*/ +/*!Exception handler for misalignment. + + Set the flag to indicated we have hit an exception. + + We can't just return, since that will give us the instruction that caused + the problem in the first place. What we do instead is patch the EPCR SPR. + + This is fine, so long as we didn't trap in a delay slot. The crude response + to that then we just exit. */ +/* --------------------------------------------------------------------------*/ +void align_handler (void) +{ + misaligned_p = 1; + + unsigned long int iaddr = mfspr (SPR_EPCR_BASE); + unsigned long int instr = *(unsigned long int *) iaddr; + unsigned char opc = instr >> 26; + + switch (opc) + { + case 0x00: /* l.j */ + case 0x01: /* l.jal */ + case 0x03: /* l.bnf */ + case 0x04: /* l.bf */ + case 0x11: /* l.jr */ + case 0x12: /* l.jalr */ + + printf ("Misalignment exception unable to recover from delay slot.\n"); + exit (1); + break; + + default: + mtspr (SPR_EPCR_BASE, iaddr + 4); /* Step past */ + break; + } +} /* align_handler () */ + + +/* --------------------------------------------------------------------------*/ +/*!Main program to read and write memory mapped registers + + Some of these are misaligned and should cause the appropriate exception. + + @return The return code from the program (always zero). */ +/* --------------------------------------------------------------------------*/ +int +main () +{ + /* Set the exception handler, and note that no exceptions have yet + happened. */ + printf ("Setting alignment exception handler.\n"); + excpt_align = (unsigned long)align_handler; + misaligned_p = 0; + + /* Write some registers */ + printf ("Writing registers.\n"); + + setreg8 (GENERIC_BASE, 0xde); + + setreg16 (GENERIC_BASE + 2, 0xdead); /* Aligned */ + setreg16 (GENERIC_BASE + 5, 0xbeef); /* Unaligned */ + + setreg32 (GENERIC_BASE + 8, 0xdeadbeef); /* Aligned */ + setreg32 (GENERIC_BASE + 13, 0xcafebabe); /* Unaligned */ + setreg32 (GENERIC_BASE + 18, 0xbaadf00d); /* Unaligned */ + setreg32 (GENERIC_BASE + 23, 0xfee1babe); /* Unaligned */ + setreg32 (GENERIC_BASE + 28, 0xbaadbabe); /* Aligned */ + + /* Write some registers */ + printf ("Reading registers.\n"); + + (void)getreg8 (GENERIC_BASE); + + (void)getreg16 (GENERIC_BASE + 2); /* Aligned */ + (void)getreg16 (GENERIC_BASE + 5); /* Unaligned */ + + (void)getreg32 (GENERIC_BASE + 8); /* Aligned */ + (void)getreg32 (GENERIC_BASE + 13); /* Unaligned */ + (void)getreg32 (GENERIC_BASE + 18); /* Unaligned */ + (void)getreg32 (GENERIC_BASE + 23); /* Unaligned */ + (void)getreg32 (GENERIC_BASE + 28); /* Aligned */ + + /* We don't actually ever return */ + report (0xdeaddead); + return 0; + +} /* main () */

openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/upcall-misaligned.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac =================================================================== --- openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac (revision 92) +++ openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac (revision 93) @@ -132,6 +132,7 @@ functest/Makefile \ flag/Makefile \ int-test/Makefile \ + int-logger/Makefile \ inst-set-test/Makefile \ kbdtest/Makefile \ local-global/Makefile \ @@ -147,6 +148,7 @@ mycompress/Makefile \ support/Makefile \ tick/Makefile \ - uos/Makefile]) + uos/Makefile \ + upcalls/Makefile]) AC_OUTPUT

/openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.in

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/openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.am

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openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.am Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/int-logger-edge.c =================================================================== --- openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/int-logger-edge.c (nonexistent) +++ openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/int-logger-edge.c (revision 93) @@ -0,0 +1,132 @@ +/* int-logger-edge.c. Test of Or1ksim handling of edge triggered interrupts + + Copyright (C) 2010 Embecosm Limited + + Contributors various OpenCores participants + Contributor Jeremy Bennett + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + +/* ---------------------------------------------------------------------------- + This code is commented throughout for use with Doxygen. + --------------------------------------------------------------------------*/ + +#include "support.h" +#include "spr-defs.h" +#include "board.h" + + +/* --------------------------------------------------------------------------*/ +/*!Write a memory mapped register + + @param[in] addr Memory mapped address + @param[in] value Value to set */ +/* --------------------------------------------------------------------------*/ +static void +setreg (unsigned long addr, + unsigned char value) +{ + *((volatile unsigned char *) addr) = value; + +} /* setreg () */ + + +/* --------------------------------------------------------------------------*/ +/*!Read a memory mapped register + + @param[in] addr Memory mapped address + + @return Value read */ +/* --------------------------------------------------------------------------*/ +unsigned long +getreg (unsigned long addr) +{ + return *((volatile unsigned char *) addr); + +} /* getreg () */ + + +/* --------------------------------------------------------------------------*/ +/*!Generic interrupt handler + + This should receive the interrupt exception. Report the value in PICSR, + then clear the interrupt and reporting it again */ +/* --------------------------------------------------------------------------*/ +static void +interrupt_handler () +{ + unsigned long int old_picsr = mfspr (SPR_PICSR); + mtspr (SPR_PICSR, 0); + unsigned long int new_picsr = mfspr (SPR_PICSR); + + printf ("PICSR 0x%08lx -> 0x%08lx\n", old_picsr, new_picsr); + +} /* interrupt_handler () */ + + +/* --------------------------------------------------------------------------*/ +/*!Main program to set up interrupt handler + + We make a series of upcalls, after 500 us and then every 1000us, which + prompt some interrupts. By doing this, our upcalls should always be well + clear of any calling function interrupt generation, which is on millisecond + boundaries. + + @return The return code from the program (always zero). */ +/* --------------------------------------------------------------------------*/ +int +main () +{ + printf ("Starting interrupt handler\n"); + excpt_int = (unsigned long)interrupt_handler; + + /* Enable interrupts */ + printf ("Enabling interrupts.\n"); + mtspr (SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE); + mtspr (SPR_PICMR, 0xffffffff); + + /* Loop forever, upcalling at the desired intervals. */ + unsigned long int start = read_timer (); + + while (1) + { + static int do_read_p = 1; + static long int end_time = 500; + + while ((read_timer () - start) < end_time) + { + } + + /* Do our memory mapped upcall, alternating reads and writes. */ + if (do_read_p) + { + (void)getreg (GENERIC_BASE); + do_read_p = 0; + } + else + { + setreg (GENERIC_BASE, 0); + do_read_p = 1; + } + + /* Wait 1000us before next upcall. */ + end_time += 1000; + } + + /* We don't actually ever return */ + return 0; + +} /* main () */

openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/int-logger-edge.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/int-logger-level.c =================================================================== --- openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/int-logger-level.c (nonexistent) +++ openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/int-logger-level.c (revision 93) @@ -0,0 +1,116 @@ +/* int-logger-level.c. Test of Or1ksim handling of level triggered interrupts + + Copyright (C) 2010 Embecosm Limited + + Contributors various OpenCores participants + Contributor Jeremy Bennett + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + +/* ---------------------------------------------------------------------------- + This code is commented throughout for use with Doxygen. + --------------------------------------------------------------------------*/ + +#include "support.h" +#include "spr-defs.h" +#include "board.h" + + +/* --------------------------------------------------------------------------*/ +/*!Write a memory mapped register + + @param[in] addr Memory mapped address + @param[in] value Value to set */ +/* --------------------------------------------------------------------------*/ +static void +setreg (unsigned long addr, + unsigned char value) +{ + *((volatile unsigned char *) addr) = value; + +} /* setreg () */ + + +/* --------------------------------------------------------------------------*/ +/*!Read a memory mapped register + + @param[in] addr Memory mapped address + + @return Value read */ +/* --------------------------------------------------------------------------*/ +unsigned long +getreg (unsigned long addr) +{ + return *((volatile unsigned char *) addr); + +} /* getreg () */ + + +/* --------------------------------------------------------------------------*/ +/*!Generic interrupt handler + + This should receive the interrupt exception. Report the value in + PICSR. Clearing will be done externally. */ +/* --------------------------------------------------------------------------*/ +static void +interrupt_handler () +{ + unsigned long int picsr = mfspr (SPR_PICSR); + + /* Report the interrupt */ + printf ("PICSR = 0x%08lx\n", picsr); + + /* Request the interrupt be cleared with a write upcall. */ + setreg (GENERIC_BASE, 0); + +} /* interrupt_handler () */ + + +/* --------------------------------------------------------------------------*/ +/*!Main program to set up interrupt handler + + @return The return code from the program (always zero). */ +/* --------------------------------------------------------------------------*/ +int +main () +{ + printf ("Starting interrupt handler\n"); + excpt_int = (unsigned long)interrupt_handler; + + /* Enable interrupts */ + printf ("Enabling interrupts.\n"); + mtspr (SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE); + mtspr (SPR_PICMR, 0xffffffff); + + /* Loop forever, upcalling reads every 500us to generate interrupts. */ + unsigned long int start = read_timer (); + + while (1) + { + static long int end_time = 500; + + while ((read_timer () - start) < end_time) + { + } + + /* Do our memory mapped upcall read to generate an interrupt. */ + (void)getreg (GENERIC_BASE); + } + + /* We don't actually ever return */ + return 0; + +} /* main () */

openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/int-logger-level.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog =================================================================== --- openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog (revision 92) +++ openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog (revision 93) @@ -1,3 +1,28 @@ +2010-04-28 Jeremy Bennett + * int-logger/int-logger-edge.c: Created. + * int-logger/Makefile.am: Added int-logger-edge. + * int-logger/Makefile.in: Regenerated. + * upcalls/upcall-basic.c: Created. + * upcalls/upcall-misaligned.c: Created. + * upcalls/Makefile.am: Created. + * upcalls/Makefile.in: Regenerated. + +2010-04-25 Jeremy Bennett + * kbdtest/kbdtest.c (print_escaped_char): Added function to print + chars more clearly. + +2010-04-23 Jeremy Bennett + * configure.ac: Added new interrupt test make files. + * configure: Regenerated. + * int-logger/int-logger-level.c: Created. + * int-logger/Makefile.am: Created. + * int-logger/Makefile.in: Regenerated. + +2010-04-22 Jeremy Bennett + * support/support.c (print_base, printf_unsigned_base): Value and + base made unsigned. + (print_decimal): cast value to unsigned for call to print_base. + 2010-04-21 Jeremy Bennett * AUTHORS: Moved from parent directory * configure: Regenerated. Index: openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/int-test.S =================================================================== --- openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/int-test.S (revision 92) +++ openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/int-test.S (revision 93) @@ -1,4 +1,4 @@ -/* int-test.S. Test of Or1ksim interrupt controller +/* int-test.S. Test of Or1ksim interrupt handling Copyright (C) 1999-2006 OpenCores Copyright (C) 2010 Embecosm Limited @@ -25,7 +25,9 @@ This code is commented throughout for use with Doxygen. --------------------------------------------------------------------------*/ -/* Within the test we'll use following global variables: +/* NOTE. This is not a test of the Programmable Interrupt Controller. + + Within the test we'll use following global variables: r16 interrupt counter r17 current tick timer comparison counter @@ -38,10 +40,11 @@ r25-r31 used by int handler The test do the following: - We set up the tick timer to trigger once and then we trigger interrupts incrementally - on every cycle in the specified test program; on interrupt handler we check if data computed - so far exactly matches precalculated values. If interrupt has returned incorreclty, we can - detect this using assertion routine at the end. + We set up the tick timer to trigger once and then we trigger interrupts + incrementally on every cycle in the specified test program; on interrupt + handler we check if data computed so far exactly matches precalculated + values. If interrupt has returned incorreclty, we can detect this using + assertion routine at the end. */ #include "spr-defs.h"

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/openrisc/trunk/or1ksim/testsuite/or1ksim.tests/int-test.exp

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/openrisc/trunk/or1ksim/testsuite/ChangeLog

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/openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in

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openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/lib-upcalls.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.am =================================================================== --- openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.am (nonexistent) +++ openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.am (revision 93) @@ -0,0 +1,33 @@ +# Makefile.am for libor1ksim test program: lib-upcalls + +# Copyright (C) Embecosm Limited, 2010 + +# Contributor Jeremy Bennett + +# This file is part of OpenRISC 1000 Architectural Simulator. + +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 3 of the License, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +# You should have received a copy of the GNU General Public License along +# with this program. If not, see . */ + +# ----------------------------------------------------------------------------- +# This code is commented throughout for use with Doxygen. +# ----------------------------------------------------------------------------- + + +# A generic program to handle upcalls. +check_PROGRAMS = lib-upcalls + +# Edge based interrupt +lib_upcalls_SOURCES = lib-upcalls.c + +lib_upcalls_LDADD = $(top_builddir)/libsim.la

openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.am Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: openrisc/trunk/or1ksim/testsuite/test-code/Makefile.am =================================================================== --- openrisc/trunk/or1ksim/testsuite/test-code/Makefile.am (revision 92) +++ openrisc/trunk/or1ksim/testsuite/test-code/Makefile.am (revision 93) @@ -26,4 +26,6 @@ # Subdirs for each test program. -SUBDIRS = lib-iftest +SUBDIRS = lib-iftest \ + lib-inttest \ + lib-upcalls

/openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/lib-inttest-edge.c

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openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/lib-inttest-edge.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in =================================================================== --- openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in (nonexistent) +++ openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in (revision 93) @@ -0,0 +1,527 @@ +# Makefile.in generated by automake 1.11.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, +# Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + +# Makefile.am for libor1ksim test program: lib-inttest + +# Copyright (C) Embecosm Limited, 2010 + +# Contributor Jeremy Bennett + +# This file is part of OpenRISC 1000 Architectural Simulator. + +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 3 of the License, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. 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Test of Or1ksim library level triggered interrupt funcs. + + Copyright (C) 1999-2006 OpenCores + Copyright (C) 2010 Embecosm Limited + + Contributors various OpenCores participants + Contributor Jeremy Bennett + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + +/* ---------------------------------------------------------------------------- + This code is commented throughout for use with Doxygen. + --------------------------------------------------------------------------*/ + +#include +#include +#include + +#include "or1ksim.h" + + +/*! Number of interrupts in PIC */ +#define NUM_INTS 32 + +/*! Vector of interrupts to be raised */ +static int *raisev; + +/*! Count of interrupts to be raised */ +static int raisec = 0; + +/*! Next interrupt to be raised */ +static int next_raise = 0; + +/*! Vector of interrupts to be cleared */ +static int *clearv; + +/*! Count of interrupts to be cleared */ +static int clearc = 0; + +/*! Next interrupt to be cleared */ +static int next_clear = 0; + + +/* --------------------------------------------------------------------------*/ +/*!Read upcall + + Upcall from Or1ksim to read a word from an external peripheral. If called + this will raise the next interrupt. + + @param[in] class_ptr A handle pass back from the initalization. Intended + for C++ callers, not used here. + @param[in] addr Address to read from. Ignored here. + @param[in] mask Byte mask for the read. Ignored here. + @param[out] rdata Buffer for the data read. Ignored here. + @param[in] data_len Number of bytes in mask and rdata. + + @return Zero on success, non-zero on failure. Always zero here. */ +/* --------------------------------------------------------------------------*/ +static int +read_upcall (void *class_ptr, + unsigned long int addr, + unsigned char mask[], + unsigned char rdata[], + int data_len) +{ + /* Raise an interrupt if there is one left to raise. */ + if ((NULL != raisev) && (next_raise < raisec)) + { + printf ("Raising interrupt %d\n", raisev[next_raise]); + or1ksim_interrupt_set (raisev[next_raise++]); + } + + return 0; /* Success */ + +} /* read_upcall () */ + + +/* --------------------------------------------------------------------------*/ +/*!Write upcall + + Upcall from Or1ksim to write a word to an external peripheral. If called + this will clear the next interrupt. + + @param[in] class_ptr A handle pass back from the initalization. Intended + for C++ callers, not used here. + @param[in] addr Address to write to. Ignored here. + @param[in] mask Byte mask for the write. Ignored here. + @param[in] wdata The data to write. Ignored here. + @param[in] data_len Number of bytes in mask and rdata. + + @return Zero on success, non-zero on failure. Always zero here. */ +/* --------------------------------------------------------------------------*/ +static int +write_upcall (void *class_ptr, + unsigned long int addr, + unsigned char mask[], + unsigned char wdata[], + int data_len) +{ + /* Clear an interrupt if there is one left to clear. */ + if ((NULL != clearv) && (next_clear < clearc)) + { + printf ("Clearing interrupt %d\n", clearv[next_clear]); + or1ksim_interrupt_clear (clearv[next_clear++]); + } + + return 0; /* Success */ + +} /* write_upcall () */ + + +/* --------------------------------------------------------------------------*/ +/*!Main program + + Build an or1ksim program using the library which loads a program and config + from the command line, and then drives interrupts. Usage: + + lib-inttest-level +|- +|- ... + + is run continuously. It requests that an interrupt be raised by a + read upcall and cleared by a write upcall. The sequence of interrupts is + specified to be raised (if preceded by '+') or cleared (if preceded by + '-'). This allows the program to test the effect of clearing the wrong + interrupt. + + @param[in] argc Number of elements in argv + @param[in] argv Vector of program name and arguments + + @return Return code for the program. */ +/* --------------------------------------------------------------------------*/ +int +main (int argc, + char *argv[]) +{ + /* Parse args */ + if (argc < 4) + { + fprintf (stderr, + "usage: lib-inttest-level " + "+|- +|- ...\n"); + return 1; + } + + /* Get all the interrupts sorted out. Count them, then place them in a + vector. */ + int i; + + for (i = 3; i < argc; i++) + { + int inum; + + switch (argv[i][0]) + { + case '+': + inum = atoi (&(argv[i][1])); + + if ((0 <= inum) && (inum < NUM_INTS)) + { + raisec++; + } + else + { + printf ("Warning: Invalid interrupt # %d to raise.\n", inum); + } + + break; + + case '-': + inum = atoi (&(argv[i][1])); + + if ((0 <= inum) && (inum < NUM_INTS)) + { + clearc++; + } + else + { + printf ("Warning: Invalid interrupt # %d to clear.\n", inum); + } + + break; + + + default: + printf ("Warning: No raise/clear specified - ignored\n"); + break; + } + } + + if ((0 == raisec) && (0 == clearc)) + { + printf ("ERROR: No interrupts specified.\n"); + return 1; + } + + /* Allocate space and populate the vectors. */ + raisev = (raisec > 0) ? calloc (raisec, sizeof (int)) : NULL; + clearv = (clearc > 0) ? calloc (clearc, sizeof (int)) : NULL; + + raisec = 0; + clearc = 0; + + for (i = 3; i < argc; i++) + { + int inum; + + switch (argv[i][0]) + { + case '+': + inum = atoi (&(argv[i][1])); + + if ((0 <= inum) && (inum < NUM_INTS)) + { + raisev[raisec++] = inum; + } + + break; + + case '-': + inum = atoi (&(argv[i][1])); + + if ((0 <= inum) && (inum < NUM_INTS)) + { + clearv[clearc++] = inum; + } + + break; + + + default: + printf ("Warning: No raise/clear specified - ignored\n"); + break; + } + } + + /* Start the counts */ + next_raise = 0; + next_clear = 0; + + /* Initialize the program. Put the initialization message afterwards, or it + will get swamped by the Or1ksim header. */ + if (0 == or1ksim_init (argv[1], argv[2], NULL, &read_upcall, &write_upcall)) + { + printf ("Initalization succeeded.\n"); + } + else + { + printf ("Initalization failed.\n"); + free (raisev); + free (clearv); + return 1; + } + + /* Run in bursts of 1ms until all interrupts have been set and cleared. */ + do + { + if (OR1KSIM_RC_OK != or1ksim_run (1.0e-3)) + { + printf ("ERROR: run failed\n"); + free (raisev); + free (clearv); + return 1; + } + } + while ((next_raise < raisec) || (next_clear < clearc)); + + /* One more burst to allow the device driver time to complete. */ + if (OR1KSIM_RC_OK != or1ksim_run (1.0e-3)) + { + printf ("ERROR: run failed\n"); + free (raisev); + free (clearv); + return 1; + } + + /* All interrupts should have been handled. */ + free (raisev); + free (clearv); + + printf ("Test completed successfully.\n"); + return 0; + +} /* main () */

openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/lib-inttest-level.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.am =================================================================== --- openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.am (nonexistent) +++ openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.am (revision 93) @@ -0,0 +1,40 @@ +# Makefile.am for libor1ksim test program: lib-inttest + +# Copyright (C) Embecosm Limited, 2010 + +# Contributor Jeremy Bennett + +# This file is part of OpenRISC 1000 Architectural Simulator. + +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 3 of the License, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +# You should have received a copy of the GNU General Public License along +# with this program. If not, see . */ + +# ----------------------------------------------------------------------------- +# This code is commented throughout for use with Doxygen. +# ----------------------------------------------------------------------------- + + +# Test programs of the library interrupt driving functions. Two versions, one +# to drive edge based interrupts, one to drive level based interrupts. +check_PROGRAMS = lib-inttest-edge \ + lib-inttest-level + +# Edge based interrupt +lib_inttest_edge_SOURCES = lib-inttest-edge.c + +lib_inttest_edge_LDADD = $(top_builddir)/libsim.la + +# Level based interrupt +lib_inttest_level_SOURCES = lib-inttest-level.c + +lib_inttest_level_LDADD = $(top_builddir)/libsim.la

openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.am Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: openrisc/trunk/or1ksim/testsuite/README =================================================================== --- openrisc/trunk/or1ksim/testsuite/README (revision 92) +++ openrisc/trunk/or1ksim/testsuite/README (revision 93) @@ -12,8 +12,8 @@ Tests are provided for the standalone simulator (or1ksim) and for the library (libsim.a). -At the time of writing a total of 21 tests of the standalone simulator compile -run and pass and 1 test of the library. +At the time of writing a total of 21 tests of the standalone simulator and 14 +tests of the library compile, run and pass. Configuration and make files are provided for further test programs. These come in three categories. @@ -45,8 +45,15 @@ Working tests ============= -A total of 21 tests: +A total of 14 tests of the libsim library: +int-edge: 6 tests of edge triggered interrupts. +int-level: 5 tests of level triggered interrupts. +lib-iftest: A test of the basic library interface functions. +upcalls: 2 tests of the upcall interface. + +A total of 21 tests of standalone Or1ksim: + basic: A test or a wide range of instructions and registers. cache: A test of the Or1ksim cache modeling cbasic: A minimal test in C @@ -72,8 +79,8 @@ Tests which build, but do not run to completion =============================================== -The following tests rely on VAPI in Or1ksim, so need a client to provide test -data over TCP/IP. +The following tests of standalone Or1ksim rely on VAPI in Or1ksim, so need a +client to provide test data over TCP/IP. acv-gpio: a test of the GPIO. acv-uart: a test of the UART @@ -81,8 +88,9 @@ Tests which build, but do not run at all ======================================== -These tests (which are built by the make file), do not appear to run at -all. The problem is in the linker script and/or the configuration for Or1ksim. +These tests of standalone Or1ksim (which are built by the make file), do not +appear to run at all. The problem is in the linker script and/or the +configuration for Or1ksim. mc-async: a test of the memory controller with asynchronous memory. mc-dram: a test of the memory controller with DRAM. @@ -93,10 +101,10 @@ Tests which do not build ======================== -The following test builds with a myriad of warnings. +The following test of standalone Or1ksim builds with a myriad of warnings. inst-set-test: a comprehensive test of the instruction set using C. -Upated by Jeremy Bennett (jeremy@jeremybennett.com) -19 April 2010 +Updated by Jeremy Bennett (jeremy@jeremybennett.com) +28 April 2010

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/openrisc/trunk/or1ksim/sim-config.c

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