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URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 93 to Rev 94
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  •

Rev 93 → Rev 94

/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/Files.tcl
8,6 → 8,7
Sd SdCmd {Rtl}
StrobesClocks TimeoutGenerator {Rtl}
Sd SdController {Rtl}
Sd SdData {Rtl}
Sd SdTop {Rtl}
Rs232 Rs232Tx {Rtl}
Components Ics307Configurator {Rtl}
/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/src/TbdSd-Rtl-ea.vhdl
49,12 → 49,9
signal iRs232Tx : aiRs232Tx;
signal oRs232Tx : aoRs232Tx;
 
signal SdCardStatus : std_ulogic_vector(31 downto 0);
 
type aState is (id, arg, waitforchange);
type aReg is record
State : aState;
SdCardStatus : std_ulogic_vector(31 downto 0);
Counter : natural;
ReceivedContent : aSdCmdContent;
ValidContent : aSdCmdContent;
80,7 → 77,6
begin
if (inResetAsync = cnActivated) then
R.State <= id;
R.SdCardStatus <= (others => '0');
R.Counter <= 3;
R.ReceivedContent <= cDefaultSdCmdContent;
R.ValidContent <= cDefaultSdCmdContent;
141,15 → 137,14
SDTop_inst : entity work.SdTop(Rtl)
port map (
iClk => iClk,
inResetAsync => inResetAsync,
ioCmd => ioCmd,
oSclk => oSclk,
ioData => ioData,
oSdCardStatus => SdCardStatus,
oReceivedContent => ReceivedContent,
iClk => iClk,
inResetAsync => inResetAsync,
ioCmd => ioCmd,
oSclk => oSclk,
ioData => ioData,
oReceivedContent => ReceivedContent,
oReceivedContentValid => oReceivedContentValid,
oLedBank => oLedBank
oLedBank => oLedBank
);
 
Rs232Tx_inst : entity work.Rs232Tx
/sdhc-sc-core/trunk/src/grpSd/unitSdTop/src/SdTop-Rtl-ea.vhdl
13,16 → 13,15
 
entity SdTop is
port (
iClk : in std_ulogic;
inResetAsync : in std_ulogic;
iClk : in std_ulogic;
inResetAsync : in std_ulogic;
 
-- SD Card
ioCmd : inout std_logic; -- Cmd line to and from card
oSclk : out std_ulogic;
ioCmd : inout std_logic;
oSclk : out std_ulogic;
ioData : inout std_logic_vector(3 downto 0);
 
-- Status
oSdCardStatus : out aSdCardStatus;
oReceivedContent : out aSdCmdContent;
oReceivedContentValid : out std_ulogic;
oLedBank : out aLedBank
31,36 → 30,44
 
architecture Rtl of SdTop is
 
signal ToController : aSdCmdToController;
signal FromController : aSdCmdFromController;
signal SdRegisters : aSdRegisters;
signal SdCmdToController : aSdCmdToController;
signal SdCmdFromController : aSdCmdFromController;
signal SdRegisters : aSdRegisters;
signal SdDataToController : aSdDataToController;
signal SdDataFromController : aSdDataFromController;
 
begin
ioData <= "ZZZZ";
oSclk <= iClk;
oSdCardStatus <= SdRegisters.CardStatus;
oReceivedContent <= ToController.Content;
oReceivedContentValid <= ToController.Valid;
oReceivedContent <= SdCmdToController.Content;
oReceivedContentValid <= SdCmdToController.Valid;
 
SdController_inst: entity work.SdController(Rtl)
port map (
iClk => iClk,
inResetAsync => inResetAsync,
iSdCmd => ToController,
oSdCmd => FromController,
iSdCmd => SdCmdToController,
oSdCmd => SdCmdFromController,
oSdRegisters => SdRegisters,
oLedBank => oLedBank
);
 
 
SdCmd_inst: entity work.SdCmd(Rtl)
port map (
iClk => iClk,
inResetAsync => inResetAsync,
iFromController => FromController,
oToController => ToController,
iFromController => SdCmdFromController,
oToController => SdCmdToController,
ioCmd => ioCmd
);
 
SdData_inst: entity work.SdData
port map (
iClk => iClk,
inResetAsync => inResetAsync,
iSdDataFromController => SdDataFromController,
oSdDataToController => SdDataToController,
ioData => ioData
);
 
end architecture Rtl;
 
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/Files.tcl
9,6 → 9,7
Sd SdCmd {Rtl}
StrobesClocks TimeoutGenerator {Rtl}
Sd SdController {Rtl}
Sd SdData {Rtl}
Sd SdTop {Rtl}
Rs232 Rs232Tx {Rtl}
Components Ics307Configurator {Rtl}
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/wave.do
14,7 → 14,6
add wave -noupdate -format Literal /Testbed/top/odigitadr
add wave -noupdate -format Literal /Testbed/top/irs232tx
add wave -noupdate -format Literal /Testbed/top/ors232tx
add wave -noupdate -format Literal /Testbed/top/sdcardstatus
add wave -noupdate -format Literal /Testbed/top/r
add wave -noupdate -format Literal /Testbed/top/nextr
add wave -noupdate -format Literal /Testbed/top/receivedcontent
28,6 → 27,8
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/nextr
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sdcontroller_inst/timeoutenable
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sdcontroller_inst/timeout
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sdcontroller_inst/nextcmdtimeout
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sdcontroller_inst/nextcmdtimeoutenable
add wave -noupdate -divider cmd
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcmd_inst/ifromcontroller
add wave -noupdate -format Literal -expand /Testbed/top/sdtop_inst/sdcmd_inst/otocontroller
45,7 → 46,7
add wave -noupdate -format Literal /Testbed/top/rs232tx_inst/ors232tx
add wave -noupdate -format Literal /Testbed/top/rs232tx_inst/irs232tx
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1006060 ns} 0}
WaveRestoreCursors {{Cursor 1} {0 ns} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
60,4 → 61,4
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ns} {2649759 ns}
WaveRestoreZoom {0 ns} {632624601 ns}
/sdhc-sc-core/trunk/src/grpSd/unitSdController/src/SdController-Rtl-ea.vhdl
63,6 → 63,9
signal TimeoutEnable : std_ulogic;
signal Timeout : std_ulogic;
 
signal NextCmdTimeout : std_ulogic;
signal NextCmdTimeoutEnable : std_ulogic;
 
begin
 
oSdRegisters.CardStatus <= R.CardStatus;
76,14 → 79,15
end if;
end process Regs;
 
Comb : process (iSdCmd, Timeout, R)
Comb : process (iSdCmd, Timeout, NextCmdTimeout, R)
variable ocr : aSdRegOCR;
variable arg : aSdCmdArg;
begin
-- default assignments
oSdCmd <= cDefaultoSdCmd;
NextR <= R;
TimeoutEnable <= cInactivated;
oSdCmd <= cDefaultoSdCmd;
NextR <= R;
TimeoutEnable <= cInactivated;
NextCmdTimeoutEnable <= cInactivated;
 
-- Status
oLedBank <= (others => cInactivated);
112,10 → 116,10
end if;
 
when waitstate =>
TimeoutEnable <= cActivated;
NextCmdTimeoutEnable <= cActivated;
 
if (Timeout = cActivated) then
TimeoutEnable <= cInactivated;
if (NextCmdTimeout = cActivated) then
NextCmdTimeoutEnable <= cInactivated;
NextR.Region <= send;
NextR.CmdRegion <= CMD8;
end if;
154,12 → 158,12
end if;
 
when waitstate =>
TimeoutEnable <= cActivated;
NextCmdTimeoutEnable <= cActivated;
 
if (Timeout = cActivated) then
TimeoutEnable <= cInactivated;
NextR.CmdRegion <= CMD55;
NextR.Region <= send;
if (NextCmdTimeout = cActivated) then
NextCmdTimeoutEnable <= cInactivated;
NextR.CmdRegion <= CMD55;
NextR.Region <= send;
end if;
 
when others =>
201,9 → 205,9
end if;
 
when waitstate =>
TimeoutEnable <= cActivated;
NextCmdTimeoutEnable <= cActivated;
 
if (Timeout = cActivated) then
if (NextCmdTimeout = cActivated) then
NextR.CmdRegion <= ACMD41;
NextR.Region <= send;
end if;
255,9 → 259,9
end if;
when waitstate =>
TimeoutEnable <= cActivated;
NextCmdTimeoutEnable <= cActivated;
 
if (Timeout = cActivated) then
if (NextCmdTimeout = cActivated) then
NextR.CmdRegion <= CMD2;
NextR.Region <= send;
end if;
296,9 → 300,9
end if;
when waitstate =>
TimeoutEnable <= cActivated;
NextCmdTimeoutEnable <= cActivated;
 
if (Timeout = cActivated) then
if (NextCmdTimeout = cActivated) then
NextR.CmdRegion <= CMD3;
NextR.Region <= send;
end if;
354,7 → 358,7
TimeoutGenerator_inst: entity work.TimeoutGenerator
generic map (
gClkFrequency => 25E6,
gTimeoutTime => 1 ms
gTimeoutTime => 100 ms
)
port map (
iClk => iClk,
362,5 → 366,16
iEnable => TimeoutEnable,
oTimeout => Timeout);
 
NextCmdTimeoutGenerator_inst: entity work.TimeoutGenerator
generic map (
gClkFrequency => 25E6,
gTimeoutTime => 320 ns
)
port map (
iClk => iClk,
inResetAsync => inResetAsync,
iEnable => NextCmdTimeoutEnable,
oTimeout => NextCmdTimeout);
 
end architecture Rtl;
 

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