OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 94 to Rev 95
    ↔ Reverse comparison
  •

Rev 94 → Rev 95

/trunk/rtl/verilog/oc8051_multiply.v
1,109 → 1,112
//////////////////////////////////////////////////////////////////////
//// ////
//// multiply for 8051 Core ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// Implementation of multipication used in alu.v ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// - Marko Mlinar, markom@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
// ver: 2 markom
// changed to two cycle multiplication, to save resources and
// increase speed
//
// ver: 3 markom
// changed to four cycle multiplication, to save resources and
// increase speed
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
 
module oc8051_multiply (clk, rst, enable, src1, src2, des1, des2, desOv);
//
// this module is part of alu
// clk (in)
// rst (in)
// enable (in)
// src1 (in) first operand
// src2 (in) second operand
// des1 (out) first result
// des2 (out) second result
// desOv (out) Overflow output
//
 
input clk, rst, enable;
input [7:0] src1, src2;
output desOv;
output [7:0] des1, des2;
 
// wires
wire [15:0] mul_result1, mul_result, shifted;
 
// real registers
reg [1:0] cycle;
reg [15:0] tmp_mul;
 
assign mul_result1 = src1 * (cycle == 2'h0 ? src2[7:6]
: cycle == 2'h1 ? src2[5:4]
: cycle == 2'h2 ? src2[3:2]
: src2[1:0]);
 
assign shifted = (cycle == 2'h0 ? 16'h0 : {tmp_mul[13:0], 2'b00});
assign mul_result = mul_result1 + shifted;
assign des1 = mul_result[15:8];
assign des2 = mul_result[7:0];
assign desOv = | des1;
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
cycle <= #1 2'b0;
tmp_mul <= #1 16'b0;
end else begin
if (enable) cycle <= #1 cycle + 2'b1;
tmp_mul <= #1 mul_result;
end
end
 
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// multiply for 8051 Core ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// Implementation of multipication used in alu.v ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// - Marko Mlinar, markom@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2002/09/30 17:33:59 simont
// prepared header
//
//
// ver: 2 markom
// changed to two cycle multiplication, to save resources and
// increase speed
//
// ver: 3 markom
// changed to four cycle multiplication, to save resources and
// increase speed
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
 
module oc8051_multiply (clk, rst, enable, src1, src2, des1, des2, desOv);
//
// this module is part of alu
// clk (in)
// rst (in)
// enable (in)
// src1 (in) first operand
// src2 (in) second operand
// des1 (out) first result
// des2 (out) second result
// desOv (out) Overflow output
//
 
input clk, rst, enable;
input [7:0] src1, src2;
output desOv;
output [7:0] des1, des2;
 
// wires
wire [15:0] mul_result1, mul_result, shifted;
 
// real registers
reg [1:0] cycle;
reg [15:0] tmp_mul;
 
assign mul_result1 = src1 * (cycle == 2'h0 ? src2[7:6]
: cycle == 2'h1 ? src2[5:4]
: cycle == 2'h2 ? src2[3:2]
: src2[1:0]);
 
assign shifted = (cycle == 2'h0 ? 16'h0 : {tmp_mul[13:0], 2'b00});
assign mul_result = mul_result1 + shifted;
assign des1 = mul_result[15:8];
assign des2 = mul_result[7:0];
assign desOv = | des1;
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
cycle <= #1 2'b0;
tmp_mul <= #1 16'b0;
end else begin
if (enable) cycle <= #1 cycle + 2'b1;
tmp_mul <= #1 mul_result;
end
end
 
endmodule
/trunk/rtl/verilog/oc8051_comp.v
1,88 → 1,91
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 compare ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// compares selected inputs and set eq to 1 if they are equal ////
//// Is used for conditional jumps. ////
//// ////
//// To Do: ////
//// replace CSS_AZ with CSS_DES ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_comp (sel, b_in, cy, acc, des, eq);
//
// sel (in) select whithc sourses to compare (look defines.v) [oc8051_decoder.comp_sel]
// b_in (in) bit in - output from bit addressable memory space [oc8051_ram_sel.bit_out]
// cy (in) carry flag [oc8051_psw.data_out[7] ]
// acc (in) accumulator [oc8051_acc.data_out]
// ram (in) input from ram [oc8051_ram_sel.out_data]
// op2 (in) immediate data [oc8051_op_select.op2_out -r]
// des (in) destination from alu [oc8051_alu.des1 -r]
// eq (out) if (src1 == src2) eq = 1 [oc8051_decoder.eq]
//
 
 
input [1:0] sel;
input b_in, cy;
input [7:0] acc, des;
 
output eq;
reg eq;
 
always @(sel or b_in or cy or acc or des)
begin
case (sel)
`OC8051_CSS_AZ : eq = (acc == 8'h00);
`OC8051_CSS_DES : eq = (des == 8'h00);
`OC8051_CSS_CY : eq = cy;
`OC8051_CSS_BIT : eq = b_in;
default: eq = 1'bx;
endcase
end
 
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 compare ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// compares selected inputs and set eq to 1 if they are equal ////
//// Is used for conditional jumps. ////
//// ////
//// To Do: ////
//// replace CSS_AZ with CSS_DES ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/09/30 17:33:59 simont
// prepared header
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_comp (sel, b_in, cy, acc, des, eq);
//
// sel (in) select whithc sourses to compare (look defines.v) [oc8051_decoder.comp_sel]
// b_in (in) bit in - output from bit addressable memory space [oc8051_ram_sel.bit_out]
// cy (in) carry flag [oc8051_psw.data_out[7] ]
// acc (in) accumulator [oc8051_acc.data_out]
// ram (in) input from ram [oc8051_ram_sel.out_data]
// op2 (in) immediate data [oc8051_op_select.op2_out -r]
// des (in) destination from alu [oc8051_alu.des1 -r]
// eq (out) if (src1 == src2) eq = 1 [oc8051_decoder.eq]
//
 
 
input [1:0] sel;
input b_in, cy;
input [7:0] acc, des;
 
output eq;
reg eq;
 
always @(sel or b_in or cy or acc or des)
begin
case (sel)
`OC8051_CSS_AZ : eq = (acc == 8'h00);
`OC8051_CSS_DES : eq = (des == 8'h00);
`OC8051_CSS_CY : eq = cy;
`OC8051_CSS_BIT : eq = b_in;
default: eq = 1'bx;
endcase
end
 
endmodule
/trunk/rtl/verilog/oc8051_ram_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2003/01/26 14:19:22 rherveille
// Replaced oc8051_ram by generic_dpram.
//
// Revision 1.5 2003/01/13 14:14:41 simont
// replace some modules
//
97,11 → 100,11
assign bit_data_out = rd_data[bit_select];
 
 
/*
 
oc8051_ram oc8051_ram1(.clk(clk), .rst(rst), .rd_addr(rd_addr_m), .rd_data(rd_data), .wr_addr(wr_addr_m),
.wr_data(wr_data_m), .wr(wr));
*/
 
/*
generic_dpram #(ram_aw, 8) oc8051_ram1(
.rclk ( clk ),
.rrst ( rst ),
117,8 → 120,8
.waddr ( wr_addr_m ),
.di ( wr_data_m )
);
*/
 
 
always @(posedge clk or posedge rst)
if (rst) begin
bit_addr_r <= #1 1'b0;
/trunk/rtl/verilog/oc8051_divide.v
1,127 → 1,129
//////////////////////////////////////////////////////////////////////
//// ////
//// divide for 8051 Core ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// Four cycle implementation of division used in alu.v ////
//// ////
//// To Do: ////
//// check if compiler does proper optimizations of the code ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// - Marko Mlinar, markom@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
module oc8051_divide (clk, rst, enable, src1, src2, des1, des2, desOv);
//
// this module is part of alu
// clk (in)
// rst (in)
// enable (in) starts divison
// src1 (in) first operand
// src2 (in) second operand
// des1 (out) first result
// des2 (out) second result
// desOv (out) Overflow output
//
 
input clk, rst, enable;
input [7:0] src1, src2;
output desOv;
output [7:0] des1, des2;
 
// wires
wire desOv;
wire div0, div1;
wire [7:0] rem0, rem1, rem2;
wire [8:0] sub0, sub1;
wire [15:0] cmp0, cmp1;
wire [7:0] div_out, rem_out;
 
// real registers
reg [1:0] cycle;
reg [5:0] tmp_div;
reg [7:0] tmp_rem;
 
// The main logic
assign cmp1 = src2 << ({2'h3 - cycle, 1'b0} + 3'h1);
assign cmp0 = src2 << ({2'h3 - cycle, 1'b0} + 3'h0);
 
assign rem2 = cycle != 0 ? tmp_rem : src1;
 
assign sub1 = {1'b0, rem2} - {1'b0, cmp1[7:0]};
assign div1 = |cmp1[15:8] ? 1'b0 : !sub1[8];
assign rem1 = div1 ? sub1[7:0] : rem2[7:0];
 
assign sub0 = {1'b0, rem1} - {1'b0, cmp0[7:0]};
assign div0 = |cmp0[15:8] ? 1'b0 : !sub0[8];
assign rem0 = div0 ? sub0[7:0] : rem1[7:0];
 
//
// in clock cycle 0 we first calculate two MSB bits, ...
// till finally in clock cycle 3 we calculate two LSB bits
assign div_out = {tmp_div, div1, div0};
assign rem_out = rem0;
assign desOv = src2 == 8'h0;
 
//
// divider works in four clock cycles -- 0, 1, 2 and 3
always @(posedge clk or posedge rst)
begin
if (rst) begin
cycle <= #1 2'b0;
tmp_div <= #1 6'h0;
tmp_rem <= #1 8'h0;
end else begin
if (enable) cycle <= #1 cycle + 2'b1;
tmp_div <= #1 div_out[5:0];
tmp_rem <= #1 rem_out;
end
end
 
//
// assign outputs
assign des1 = rem_out;
assign des2 = div_out;
 
endmodule
 
//////////////////////////////////////////////////////////////////////
//// ////
//// divide for 8051 Core ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// Four cycle implementation of division used in alu.v ////
//// ////
//// To Do: ////
//// check if compiler does proper optimizations of the code ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// - Marko Mlinar, markom@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2002/09/30 17:15:31 simont
// prepared header
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
module oc8051_divide (clk, rst, enable, src1, src2, des1, des2, desOv);
//
// this module is part of alu
// clk (in)
// rst (in)
// enable (in) starts divison
// src1 (in) first operand
// src2 (in) second operand
// des1 (out) first result
// des2 (out) second result
// desOv (out) Overflow output
//
 
input clk, rst, enable;
input [7:0] src1, src2;
output desOv;
output [7:0] des1, des2;
 
// wires
wire desOv;
wire div0, div1;
wire [7:0] rem0, rem1, rem2;
wire [8:0] sub0, sub1;
wire [15:0] cmp0, cmp1;
wire [7:0] div_out, rem_out;
 
// real registers
reg [1:0] cycle;
reg [5:0] tmp_div;
reg [7:0] tmp_rem;
 
// The main logic
assign cmp1 = src2 << ({2'h3 - cycle, 1'b0} + 3'h1);
assign cmp0 = src2 << ({2'h3 - cycle, 1'b0} + 3'h0);
 
assign rem2 = cycle != 0 ? tmp_rem : src1;
 
assign sub1 = {1'b0, rem2} - {1'b0, cmp1[7:0]};
assign div1 = |cmp1[15:8] ? 1'b0 : !sub1[8];
assign rem1 = div1 ? sub1[7:0] : rem2[7:0];
 
assign sub0 = {1'b0, rem1} - {1'b0, cmp0[7:0]};
assign div0 = |cmp0[15:8] ? 1'b0 : !sub0[8];
assign rem0 = div0 ? sub0[7:0] : rem1[7:0];
 
//
// in clock cycle 0 we first calculate two MSB bits, ...
// till finally in clock cycle 3 we calculate two LSB bits
assign div_out = {tmp_div, div1, div0};
assign rem_out = rem0;
assign desOv = src2 == 8'h0;
 
//
// divider works in four clock cycles -- 0, 1, 2 and 3
always @(posedge clk or posedge rst)
begin
if (rst) begin
cycle <= #1 2'b0;
tmp_div <= #1 6'h0;
tmp_rem <= #1 8'h0;
end else begin
if (enable) cycle <= #1 cycle + 2'b1;
tmp_div <= #1 div_out[5:0];
tmp_rem <= #1 rem_out;
end
end
 
//
// assign outputs
assign des1 = rem_out;
assign des2 = div_out;
 
endmodule
/trunk/rtl/verilog/oc8051_cy_select.v
1,81 → 1,84
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 alu carry select module ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// Multiplexer wiht whitch we select carry in alu ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_cy_select (cy_sel, cy_in, data_in, data_out);
//
// cy_sel (in) carry select, from decoder (see defines.v) [oc8051_decoder.cy_sel -r]
// cy_in (in) carry input [oc8051_psw.data_out[7] ]
// data_in (in) ram data input [oc8051_ram_sel.bit_out]
// data_out (out) data output [oc8051_alu.srcCy]
//
 
input [1:0] cy_sel;
input cy_in, data_in;
 
output data_out;
reg data_out;
 
always @(cy_sel or cy_in or data_in)
begin
case (cy_sel)
`OC8051_CY_0: data_out = 1'b0;
`OC8051_CY_PSW: data_out = cy_in;
`OC8051_CY_RAM: data_out = data_in;
`OC8051_CY_1: data_out = 1'b1;
default: data_out = 1'bx;
endcase
end
 
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 alu carry select module ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// Multiplexer wiht whitch we select carry in alu ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/09/30 17:33:59 simont
// prepared header
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_cy_select (cy_sel, cy_in, data_in, data_out);
//
// cy_sel (in) carry select, from decoder (see defines.v) [oc8051_decoder.cy_sel -r]
// cy_in (in) carry input [oc8051_psw.data_out[7] ]
// data_in (in) ram data input [oc8051_ram_sel.bit_out]
// data_out (out) data output [oc8051_alu.srcCy]
//
 
input [1:0] cy_sel;
input cy_in, data_in;
 
output data_out;
reg data_out;
 
always @(cy_sel or cy_in or data_in)
begin
case (cy_sel)
`OC8051_CY_0: data_out = 1'b0;
`OC8051_CY_PSW: data_out = cy_in;
`OC8051_CY_RAM: data_out = data_in;
`OC8051_CY_1: data_out = 1'b1;
default: data_out = 1'bx;
endcase
end
 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.