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https://opencores.org/ocsvn/or1k/or1k/trunk
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- This comparison shows the changes necessary to convert path
/
- from Rev 942 to Rev 943
- ↔ Reverse comparison
Rev 942 → Rev 943
/trunk/or1200/rtl/verilog/or1200_wb_biu.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/07/14 22:17:17 lampret |
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. |
// |
// Revision 1.1 2002/01/03 08:16:15 lampret |
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. |
// |
156,6 → 159,12
wire long_ack_o; // normal termination |
wire long_err_o; // error termination |
`endif |
wire aborted; // Graceful abort |
reg aborted_r; // Graceful abort |
wire retry; // Retry |
`ifdef OR1200_WB_RETRY |
reg [`OR1200_WB_RETRY-1:0] retry_cntr; // Retry counter |
`endif |
|
// |
// WISHBONE I/F <-> Internal RISC I/F conversion |
168,7 → 177,7
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
wb_adr_o <= #1 {aw{1'b0}}; |
else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i) |
else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted & ~(wb_stb_o & ~wb_ack_i)) |
wb_adr_o <= #1 biu_adr_i; |
`else |
assign wb_adr_o = biu_adr_i; |
194,7 → 203,7
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
wb_dat_o <= #1 {dw{1'b0}}; |
else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i) |
else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted) |
wb_dat_o <= #1 biu_dat_i; |
`else |
assign wb_dat_o = biu_dat_i; |
235,9 → 244,9
if (wb_rst_i) |
long_ack_o <= #1 1'b0; |
else |
long_ack_o <= #1 wb_ack_i; |
long_ack_o <= #1 wb_ack_i & ~aborted; |
`else |
assign long_ack_o = wb_ack_i; |
assign long_ack_o = wb_ack_i & ~aborted; |
`endif |
|
// |
264,14 → 273,60
if (wb_rst_i) |
long_err_o <= #1 1'b0; |
else |
long_err_o <= #1 wb_err_i; |
long_err_o <= #1 wb_err_i & ~aborted; |
`else |
assign long_err_o = wb_err_i; |
assign long_err_o = wb_err_i & ~aborted; |
`endif |
|
// |
// Retry counter |
// |
// Assert 'retry' when 'wb_rty_i' is sampled high and keep it high |
// until retry counter doesn't expire |
// |
`ifdef OR1200_WB_RETRY |
assign retry = wb_rty_i | (|retry_cntr); |
`else |
assign retry = 1'b0; |
`endif |
`ifdef OR1200_WB_RETRY |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
retry_cntr <= #1 1'b0; |
else if (wb_rty_i) |
retry_cntr <= #1 {`OR1200_WB_RETRY{1'b1}}; |
else if (retry_cntr) |
retry_cntr <= #1 retry_cntr - 7'd1; |
`endif |
|
// |
// Graceful completion of aborted transfers |
// |
// Assert 'aborted' when 1) current transfer is in progress (wb_stb_o; which |
// we know is only asserted together with wb_cyc_o) 2) and in next WB clock cycle |
// wb_stb_o would be deasserted (biu_cyc_i and biu_stb_i are low) 3) and |
// there is no termination of current transfer in this WB clock cycle (wb_ack_i |
// and wb_err_i are low). |
// Extend 'aborted' signal with 'aborted_r' until this "aborted" transfer |
// is properly terminated with wb_ack_i/wb_err_i. |
// |
// |
assign aborted = wb_stb_o & ~(biu_cyc_i & biu_stb_i) & ~(wb_ack_i | wb_err_i) | aborted_r; |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
aborted_r <= #1 1'b0; |
else if (wb_ack_i | wb_err_i) |
aborted_r <= #1 1'b0; |
else if (aborted) |
aborted_r <= #1 1'b1; |
|
// |
// WB cyc_o |
// |
// Either 1) normal transfer initiated by biu_cyc_i (and biu_cab_i if |
// bursts are enabled) and possibly suspended by 'retry' |
// or 2) extended "aborted" transfer |
// |
`ifdef OR1200_REGISTERED_OUTPUTS |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
278,15 → 333,15
wb_cyc_o <= #1 1'b0; |
else |
`ifdef OR1200_NO_BURSTS |
wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i; |
wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry | aborted & ~wb_ack_i; |
`else |
wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i | biu_cab_i; |
wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry | biu_cab_i | aborted & ~wb_ack_i; |
`endif |
`else |
`ifdef OR1200_NO_BURSTS |
assign wb_cyc_o = biu_cyc_i; |
assign wb_cyc_o = biu_cyc_i & ~retry; |
`else |
assign wb_cyc_o = biu_cyc_i | biu_cab_i; |
assign wb_cyc_o = biu_cyc_i | biu_cab_i & ~retry; |
`endif |
`endif |
|
298,7 → 353,7
if (wb_rst_i) |
wb_stb_o <= #1 1'b0; |
else |
wb_stb_o <= #1 (biu_cyc_i & biu_stb_i) & ~wb_ack_i; |
wb_stb_o <= #1 (biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~retry | aborted & ~wb_ack_i; |
`else |
assign wb_stb_o = biu_cyc_i & biu_stb_i; |
`endif |
311,7 → 366,7
if (wb_rst_i) |
wb_we_o <= #1 1'b0; |
else |
wb_we_o <= #1 biu_cyc_i & biu_stb_i & biu_we_i; |
wb_we_o <= #1 biu_cyc_i & biu_stb_i & biu_we_i | aborted & wb_we_o; |
`else |
assign wb_we_o = biu_cyc_i & biu_stb_i & biu_we_i; |
`endif |