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Rev 943 → Rev 944
/trunk/or1200/rtl/verilog/or1200_defines.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.16 2002/07/14 22:17:17 lampret |
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. |
// |
// Revision 1.15 2002/06/08 16:20:21 lampret |
// Added defines for enabling generic FF based memory macro for register file. |
// |
196,20 → 199,10
//`define OR1200_NO_IMMU |
|
// |
// Register OR1200 WISHBONE outputs |
// (at the moment correct operation |
// only with registered outputs) |
// Select between ASIC optimized and generic multiplier |
// |
`define OR1200_REGISTERED_OUTPUTS |
|
// (Generic seems to trigger a bug in the Cadence Ncsim simulator) |
// |
// Register OR1200 WISHBNE inputs |
// |
//`define OR1200_REGISTERED_INPUTS |
|
// |
// Select between ASIC optimized and generic multiplier |
// |
//`define OR1200_ASIC_MULTP2_32X32 |
`define OR1200_GENERIC_MULTP2_32X32 |
|
257,20 → 250,10
//`define OR1200_NO_IMMU |
|
// |
// Register OR1200 WISHBONE outputs |
// (at the moment works only with |
// registered outputs) |
// Select between ASIC and generic multiplier |
// |
`define OR1200_REGISTERED_OUTPUTS |
|
// (Generic seems to trigger a bug in the Cadence Ncsim simulator) |
// |
// Register OR1200 WISHBONE inputs |
// |
//`define OR1200_REGISTERED_INPUTS |
|
// |
// Select between ASIC and generic multiplier |
// |
//`define OR1200_ASIC_MULTP2_32X32 |
`define OR1200_GENERIC_MULTP2_32X32 |
|
292,6 → 275,19
// |
|
// |
// Register OR1200 WISHBONE outputs |
// (must be defined/enabled) |
// |
`define OR1200_REGISTERED_OUTPUTS |
|
// |
// Register OR1200 WISHBONE inputs |
// |
// (must be undefined/disabled) |
// |
//`define OR1200_REGISTERED_INPUTS |
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// |
// Disable bursts if they are not supported by the |
// memory subsystem (only affect cache line fill) |
// |
299,6 → 295,19
// |
|
// |
// WISHBONE retry counter range |
// |
// 2^value range for retry counter. Retry counter |
// is activated whenever *wb_rty_i is asserted and |
// until retry counter expires, corresponding |
// WISHBONE interface is deactivated. |
// |
// To disable retry counters and *wb_rty_i all together, |
// undefine this macro. |
// |
//`define OR1200_WB_RETRY 7 |
|
// |
// Enable additional synthesis directives if using |
// _Synopsys_ synthesis tool |
// |