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Rev 948 → Rev 949

/trunk/orp/orp_soc/bench/verilog/or1200_monitor.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/03/28 19:59:55 lampret
// Added bench directory
//
// Revision 1.9 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
99,8 → 102,10
integer fexe;
reg [23:0] ref;
integer fspr;
integer fnop;
integer fgeneral;
integer flookup;
integer r3;
integer insns;
 
//
// Initialization
110,7 → 115,9
fexe = $fopen("executed.log");
$timeformat (-9, 2, " ns", 12);
fspr = $fopen("sprs.log");
fnop = $fopen("nop.log");
fgeneral = $fopen("general.log");
flookup = $fopen("lookup.log");
insns = 0;
end
 
//
185,7 → 192,8
begin
`ifdef OR1200_DISPLAY_ARCH_STATE
ref = ref + 1;
$fwrite(fexe, "\nEXECUTED(): %h: %h", `OR1200_TOP.or1200_cpu.or1200_except.wb_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn);
$fdisplay(flookup, "Instruction %d: %t", insns, $time);
$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns, `OR1200_TOP.or1200_cpu.or1200_except.wb_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn);
for(i = 0; i < 32; i = i + 1) begin
if (i % 4 == 0)
$fdisplay(fexe);
201,11 → 209,102
$fwrite(fexe, "EEAR0: %h ", r);
r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
$fdisplay(fexe, "ESR0 : %h", r);
insns = insns + 1;
`endif
end
endtask
 
integer iwb_progress;
reg [31:0] iwb_progress_addr;
//
// WISHBONE bus checker
//
always @(posedge `OR1200_TOP.iwb_clk_i)
if (`OR1200_TOP.iwb_rst_i) begin
iwb_progress = 0;
iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
end
else begin
if (`OR1200_TOP.iwb_cyc_o && (iwb_progress != 2)) begin
iwb_progress = 1;
end
if (`OR1200_TOP.iwb_stb_o) begin
if (iwb_progress >= 1) begin
if (iwb_progress == 1)
iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
iwb_progress = 2;
end
else begin
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o raised without `OR1200_TOP.iwb_cyc_o, at %t\n", $time);
#100 $finish;
end
end
if (`OR1200_TOP.iwb_ack_i & `OR1200_TOP.iwb_err_i) begin
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i and `OR1200_TOP.iwb_err_i raised at the same time, at %t\n", $time);
end
if ((iwb_progress == 2) && (iwb_progress_addr != `OR1200_TOP.iwb_adr_o)) begin
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_adr_o changed while waiting for `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
#100 $finish;
end
if (`OR1200_TOP.iwb_ack_i | `OR1200_TOP.iwb_err_i)
if (iwb_progress == 2) begin
iwb_progress = 0;
iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
end
else begin
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i/`OR1200_TOP.iwb_err_i raised without `OR1200_TOP.iwb_cyc_i/`OR1200_TOP.iwb_stb_i, at %t\n", $time);
#100 $finish;
end
if ((iwb_progress == 2) && !`OR1200_TOP.iwb_stb_o) begin
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o lowered without `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
/* #100 $finish;*/
end
end
 
integer dwb_progress;
reg [31:0] dwb_progress_addr;
//
// WISHBONE bus checker
//
always @(posedge `OR1200_TOP.dwb_clk_i)
if (`OR1200_TOP.dwb_rst_i)
dwb_progress = 0;
else begin
if (`OR1200_TOP.dwb_cyc_o && (dwb_progress != 2))
dwb_progress = 1;
if (`OR1200_TOP.dwb_stb_o)
if (dwb_progress >= 1) begin
if (dwb_progress == 1)
dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
dwb_progress = 2;
end
else begin
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o raised without `OR1200_TOP.dwb_cyc_o, at %t\n", $time);
#100 $finish;
end
if (`OR1200_TOP.dwb_ack_i & `OR1200_TOP.dwb_err_i) begin
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i and `OR1200_TOP.dwb_err_i raised at the same time, at %t\n", $time);
end
if ((dwb_progress == 2) && (dwb_progress_addr != `OR1200_TOP.dwb_adr_o)) begin
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_adr_o changed while waiting for `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
#100 $finish;
end
if (`OR1200_TOP.dwb_ack_i | `OR1200_TOP.dwb_err_i)
if (dwb_progress == 2) begin
dwb_progress = 0;
dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
end
else begin
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i/`OR1200_TOP.dwb_err_i raised without `OR1200_TOP.dwb_cyc_i/`OR1200_TOP.dwb_stb_i, at %t\n", $time);
#100 $finish;
end
if ((dwb_progress == 2) && !`OR1200_TOP.dwb_stb_o) begin
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o lowered without `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
#100 $finish;
end
end
 
//
// Hooks for:
// - displaying registers
// - end of simulation
219,16 → 318,16
display_arch_state;
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0001) begin // small hack to stop simulation (l.nop 1)
get_gpr(3, r3);
$fdisplay(fnop, "%t: l.nop exit (%h)", $time, r3);
$fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
$finish;
end
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0002) begin // simulation reports (l.nop 2)
get_gpr(3, r3);
$fdisplay(fnop, "%t: l.nop report (%h)", $time, r3);
$fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);
end
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0003) begin // simulation printfs (l.nop 3)
get_gpr(3, r3);
$fdisplay(fnop, "%t: l.nop printf (%h)", $time, r3);
$fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);
end
if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MTSR) // l.mtspr
$fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,

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