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    from Rev 95 to Rev 96
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Rev 95 → Rev 96

/ion/trunk/vhdl/mips_cache_stub.vhdl
2,13 → 2,14
-- mips_cache_stub.vhdl -- 1-word cache module
--
-- This module has the same interface and logic as a real cache but the cache
-- memory is just 1 word for each of code and data.
-- memory is just 1 word for each of code and data, and it's missing any tag
-- matching logic so all accesses 'miss'.
--
-- It interfaces the CPU to the following:
--
-- 1.- Internal 32-bit-wide BRAM for read only
-- 2.- Internal 32-bit I/O bus
-- 3.- External 16-bit wide SRAM
-- 3.- External 16-bit or 8-bit wide static memory (SRAM or FLASH)
--
-- The SRAM memory interface signals are meant to connect directly to FPGA pins
-- and all outputs are registered (tco should be minimal).
60,10 → 61,7
-- to unmapped areas. I haven't yet decided how to handle that (return
-- zero, trigger trap, mirror another mapped area...).
--
-- 3.- Code refills from SRAM is unimplemented yet
-- To be done for sheer lack of time.
--
-- 4.- Does not work as a real 1-word cache yet
-- 3.- Does not work as a real 1-word cache yet
-- That functionality is still missing, all accesses 'miss'. It should be
-- implemented, as a way to test the real cache logic on a small scale.
--
78,8 → 76,13
 
entity mips_cache_stub is
generic (
BRAM_ADDR_SIZE : integer := 10;
SRAM_ADDR_SIZE : integer := 17
BRAM_ADDR_SIZE : integer := 10; -- BRAM address size
SRAM_ADDR_SIZE : integer := 17; -- Static RAM/Flash address size
-- these cache parameters are unused in thie implementation, they're
-- here for compatibility to the real cache module.
LINE_SIZE : integer := 4; -- Line size in words
CACHE_SIZE : integer := 256 -- I- and D- cache size in lines
);
port(
clk : in std_logic;
86,18 → 89,18
reset : in std_logic;
 
-- Interface to CPU core
data_rd_addr : in std_logic_vector(31 downto 0);
data_addr : in std_logic_vector(31 downto 0);
data_rd : out std_logic_vector(31 downto 0);
data_rd_vma : in std_logic;
 
byte_we : in std_logic_vector(3 downto 0);
data_wr : in std_logic_vector(31 downto 0);
 
code_rd_addr : in std_logic_vector(31 downto 2);
code_rd : out std_logic_vector(31 downto 0);
code_rd_vma : in std_logic;
 
data_wr_addr : in std_logic_vector(31 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_wr : in std_logic_vector(31 downto 0);
 
mem_wait : out std_logic;
cache_enable : in std_logic;
 
624,7 → 627,7
-- data_rd_addr_reg always has the addr of any pending read
if data_rd_vma='1' then
read_pending <= '1';
data_rd_addr_reg <= data_rd_addr(31 downto 2);
data_rd_addr_reg <= data_addr(31 downto 2);
elsif ps=data_refill_sram_1 or
ps=data_refill_sram8_3 or
ps=data_refill_bram_1 or
639,7 → 642,7
if byte_we/="0000" and ps=idle then
byte_we_reg <= byte_we;
data_wr_reg <= data_wr;
data_wr_addr_reg <= data_wr_addr;
data_wr_addr_reg <= data_addr(31 downto 2);
write_pending <= '1';
elsif ps=data_writethrough_sram_1b or
ps=data_write_io_0 or
828,7 → 831,8
else '0';
 
-- The lowest addr bit will only be used when accessing byte-wide memory, and
-- even when we're reading word-aligned code (we need to read the four bytes)
-- even when we're reading word-aligned code (because we need to read the four
-- bytes one by one).
sram_address(0) <=
'0' when (ps=data_refill_sram8_0 or ps=data_refill_sram8_2 or
ps=code_refill_sram8_0 or ps=code_refill_sram8_2) else
/ion/trunk/vhdl/tb/mips_tb_pkg.vhdl
61,7 → 61,7
code_rd_vma : std_logic;
data_byte_we : std_logic_vector(3 downto 0);
 
present_data_wr_addr : t_pc;
present_data_wr_addr : t_word;
present_data_wr : t_word;
present_data_rd_addr : t_word;
present_code_rd_addr : t_pc;
246,7 → 246,7
if info.data_byte_we/="0000" then
info.write_pending <= true;
info.pending_data_wr_we <= info.data_byte_we;
info.pending_data_wr_addr <= info.present_data_wr_addr & "00";
info.pending_data_wr_addr <= info.present_data_wr_addr;
info.pending_data_wr_pc <= info.pc_m(k-1);
info.pending_data_wr <= info.present_data_wr;
end if;
285,11 → 285,11
init_signal_spy("/"&entity_name&"/data_rd_vma", signal_name&".data_rd_vma", 0, -1);
init_signal_spy("/"&entity_name&"/code_rd_vma", signal_name&".code_rd_vma", 0, -1);
init_signal_spy("/"&entity_name&"/p2_do_load", signal_name&".load", 0, -1);
init_signal_spy("/"&entity_name&"/data_wr_addr", signal_name&".present_data_wr_addr", 0, -1);
init_signal_spy("/"&entity_name&"/data_addr", signal_name&".present_data_wr_addr", 0, -1);
init_signal_spy("/"&entity_name&"/data_wr", signal_name&".present_data_wr", 0, -1);
init_signal_spy("/"&entity_name&"/byte_we", signal_name&".data_byte_we", 0, -1);
init_signal_spy("/"&entity_name&"/p2_data_word_rd", signal_name&".word_loaded", 0, -1);
init_signal_spy("/"&entity_name&"/data_rd_addr", signal_name&".present_data_rd_addr", 0, -1);
init_signal_spy("/"&entity_name&"/data_addr", signal_name&".present_data_rd_addr", 0, -1);
 
while done='0' loop
wait until clk'event and clk='1';
/ion/trunk/vhdl/mips_cpu.vhdl
4,7 → 4,7
-- project: ION (http://www.opencores.org/project,ion_cpu)
-- author: Jose A. Ruiz (ja_rd@hotmail.com)
-- created: Jan/11/2011
-- last modified: Jan/31/2011 (ja_rd@hotmail.com)
-- last modified: Mar/03/2011 (ja_rd@hotmail.com)
--------------------------------------------------------------------------------
-- Software placed into the public domain by the author. Use under the terms of
-- the GPL.
52,18 → 52,18
reset : in std_logic;
interrupt : in std_logic;
 
data_rd_addr : out std_logic_vector(31 downto 0);
data_addr : out std_logic_vector(31 downto 0);
 
data_rd : in std_logic_vector(31 downto 0);
data_rd_vma : out std_logic;
 
byte_we : out std_logic_vector(3 downto 0);
data_wr : out std_logic_vector(31 downto 0);
code_rd_addr : out std_logic_vector(31 downto 2);
code_rd : in std_logic_vector(31 downto 0);
code_rd_vma : out std_logic;
data_wr_addr : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_wr : out std_logic_vector(31 downto 0);
 
mem_wait : in std_logic
);
end; --entity mips_cpu
470,8 → 470,8
end if;
end process pc_register;
 
-- FIXME we should not output the lowest 2 bits
data_rd_addr <= p1_data_addr(31 downto 0);
-- Common rd/wr address; lowest 2 bits are output as debugging aid only
data_addr <= p1_data_addr(31 downto 0);
 
-- FIXME these two need to pushed behind a register, they are glitch-prone
data_rd_vma <= p1_do_load and not pipeline_stalled; -- FIXME register
479,7 → 479,6
 
code_rd_addr <= p0_pc_next;
 
data_wr_addr <= p1_data_addr(31 downto 2);
 
-- compute target of J/JR instructions
p0_pc_jump <= p1_rs(31 downto 2) when p1_do_reg_jump='1' else

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