URL
https://opencores.org/ocsvn/pci/pci/trunk
Subversion Repositories pci
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- This comparison shows the changes necessary to convert path
/
- from Rev 95 to Rev 96
- ↔ Reverse comparison
Rev 95 → Rev 96
/trunk/apps/crt/syn/synplify/pci_crt.sdc
1,7 → 1,7
# Synplicity, Inc. constraint file |
# /shared/projects/pci/mihad/pci/apps/crt/syn/synplify/pci_crt.sdc |
# Written on Fri Sep 27 11:42:06 2002 |
# by Amplify, Amplify 3.1 Scope Editor |
# Written on Mon Mar 10 13:33:22 2003 |
# by Synplify Pro, 7.2 Scope Editor |
|
# |
# Clocks |
108,50 → 108,9
# |
# Registers |
# |
#define_reg_output_delay {bridge.pci_target_unit.del_sync.comp_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.pci_target_unit.del_sync.done_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.configuration.cache_lsize_to_wb_bits_sync.sync_data_out[6:0]} -route 15.00 |
#define_reg_output_delay {bridge.configuration.command_bit_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.configuration.int_pin_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.configuration.isr_bit0_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.configuration.isr_bit2_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.configuration.pci_err_cs_bits_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.configuration.sync_isr_2.clear_delete_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.configuration.sync_isr_2.delete_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.configuration.sync_pci_err_cs_8.clear_delete_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.configuration.sync_pci_err_cs_8.delete_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.pci_target_unit.del_sync.comp_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.pci_target_unit.del_sync.done_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.pci_target_unit.del_sync.req_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.pci_target_unit.del_sync.rty_exp_back_prop_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.pci_target_unit.del_sync.rty_exp_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.pci_target_unit.fifos.pcir_fifo_ctrl.almost_empty} -route 15.00 |
#define_reg_output_delay {bridge.pci_target_unit.fifos.pcir_fifo_ctrl.empty} -route 15.00 |
#define_reg_output_delay {bridge.pci_target_unit.fifos.pcir_fifo_ctrl.full_out} -route 15.00 |
#define_reg_output_delay {bridge.pci_target_unit.fifos.pcir_fifo_ctrl.stretched_empty} -route 15.00 |
#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_fifo_ctrl.almost_empty} -route 15.00 |
#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_fifo_ctrl.almost_full} -route 15.00 |
#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_fifo_ctrl.empty} -route 15.00 |
#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_fifo_ctrl.full_out} -route 15.00 |
#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_fifo_ctrl.stretched_empty} -route 15.00 |
#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_fifo_ctrl.two_left_out} -route 15.00 |
#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_transaction_ready_out} -route 15.00 |
#define_reg_output_delay {bridge.wishbone_slave_unit.del_sync.comp_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.wishbone_slave_unit.del_sync.done_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.wishbone_slave_unit.del_sync.req_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.wishbone_slave_unit.del_sync.rty_exp_back_prop_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.wishbone_slave_unit.del_sync.rty_exp_sync.sync_data_out[0]} -route 15.00 |
#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbr_fifo_ctrl.empty} -route 15.00 |
#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbr_fifo_ctrl.stretched_empty} -route 15.00 |
#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbw_fifo_ctrl.almost_full} -route 15.00 |
#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbw_fifo_ctrl.empty} -route 15.00 |
#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbw_fifo_ctrl.full_out} -route 15.00 |
#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbw_fifo_ctrl.stretched_empty} -route 15.00 |
#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbw_transaction_ready_out} -route 15.00 |
define_reg_output_delay {*sync_data_out*} -route 20.00 |
define_reg_output_delay {*meta_q_o*} -route 20.00 |
|
define_reg_output_delay {*sync_data_out*} -route 20.00 |
define_reg_output_delay {*meta_q_o*} -route 20.00 |
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# |
# Multicycle Path |
# |
235,7 → 194,7
define_attribute {v:work.pci_frame_en_crit} syn_hier {hard} |
define_attribute {v:work.pci_frame_load_crit} syn_hier {hard} |
define_attribute {v:work.pci_irdy_out_crit} syn_hier {hard} |
define_attribute {v:work.pci_mad_ad_en_crit} syn_hier {hard} |
define_attribute {v:work.pci_mas_ad_en_crit} syn_hier {hard} |
define_attribute {v:work.pci_mas_ad_load_crit} syn_hier {hard} |
define_attribute {v:work.pci_mas_ch_state_crit} syn_hier {hard} |
define_attribute {v:work.pci_par_crit} syn_hier {hard} |
251,9 → 210,9
define_attribute {v:work.pci_serr_en_crit} syn_hier {hard} |
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# |
# Other Constraints |
# Compile Points |
# |
|
# |
# Order of waveforms |
# Other Constraints |
# |
/trunk/apps/crt/syn/synplify/pci_crt.prj
1,7 → 1,7
#-- Synplicity, Inc. |
#-- Version Amplify 3.1 |
#-- Version 7.2 |
#-- Project file /shared/projects/pci/mihad/pci/apps/crt/syn/synplify/pci_crt.prj |
#-- Written on Fri Sep 27 16:20:50 2002 |
#-- Written on Mon Mar 10 13:16:14 2003 |
|
|
#add_file options |
69,9 → 69,7
add_file -constraint "pci_crt.sdc" |
add_file -verilog "../../rtl/verilog/top.v" |
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#reporting options |
|
|
#implementation: "rev_1" |
impl -add rev_1 |
|
83,7 → 81,7
|
#compilation/mapping options |
set_option -default_enum_encoding default |
set_option -symbolic_fsm_compiler 0 |
set_option -symbolic_fsm_compiler 1 |
set_option -resource_sharing 0 |
set_option -use_fsm_explorer 0 |
|
91,10 → 89,11
set_option -frequency 50.000 |
set_option -fanout_limit 50 |
set_option -disable_io_insertion 0 |
set_option -pipe 0 |
set_option -fixgatedclocks 0 |
set_option -retiming 0 |
set_option -pipe 1 |
set_option -retiming 1 |
set_option -modular 0 |
set_option -update_models_cp 0 |
set_option -verification_mode 0 |
|
#simulation options |
set_option -write_verilog 0 |
107,19 → 106,13
project -result_file "rev_1/top.edf" |
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#implementation attributes |
set_option -vlog_std v95 |
set_option -compiler_compatible 0 |
set_option -random_floorplan 0 |
set_option -include_path "../../rtl/verilog/;../../../../rtl/verilog/" |
|
#netlist optimizer options |
set_option -enable_nfilter 0 |
set_option -feedthrough 1 |
set_option -constant_prop 1 |
set_option -level_hierarchy 0 |
|
#physical constraint options |
set_option -popfeed 1 |
set_option -constprop 1 |
set_option -createhierarchy 0 |
set_option -floorplan "" |
set_option -nfilter_user_path "" |
set_option -pin_assignment "" |
set_option -include_path "../../rtl/verilog/;../../../../rtl/verilog/" |
impl -active "rev_1" |