URL
https://opencores.org/ocsvn/xgate/xgate/trunk
Subversion Repositories xgate
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 95 to Rev 96
- ↔ Reverse comparison
Rev 95 → Rev 96
/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
51,7 → 51,6
input wbs_rst_i, // synchronous active high reset |
input arst_i, // asynchronous reset |
input [ 6:1] wbs_adr_i, // lower address bits |
input [DWIDTH-1:0] wbs_dat_i, // databus input |
input wbs_we_i, // write enable input |
input wbs_stb_i, // stobe/core select signal |
input wbs_cyc_i, // valid bus cycle input |
/xgate/trunk/rtl/verilog/xgate_irq_encode.v
1,6 → 1,6
//////////////////////////////////////////////////////////////////////////////// |
// |
// Computer Operating Properly - XGATE interrupt encoder |
// XGATE Coprocessor - XGATE interrupt encoder |
// |
// Author: Bob Hayes |
// rehayes@opencores.org |
49,6 → 49,7
input [MAX_CHANNEL:1] xgif_status // Interrupt outputs from RISC core |
); |
|
integer i; // Loop Counter for array index |
wire [MAX_CHANNEL:1] chan_ena_gate; // Ouptut of channel enable gating |
|
// Pass non-bypassed interrupt inputs to XGATE RISC |
55,7 → 56,6
assign chan_ena_gate = ~chan_bypass & chan_req_i; |
|
// Set int_reg to the index of the index of the lowest chan_req_i input that is active |
integer i = 0; |
always @(chan_ena_gate) |
begin |
int_req = 0; |
/xgate/trunk/rtl/verilog/xgate_wbm_bus.v
51,9 → 51,6
output [15:0] wbm_adr_o, // Address bits |
input [DWIDTH-1:0] wbm_dat_i, // databus input |
input wbm_ack_i, // bus cycle acknowledge input |
input wbs_clk_i, // master clock input |
input wbs_rst_i, // synchronous active high reset |
input arst_i, // asynchronous reset |
// XGATE Control Signals |
output [DWIDTH-1:0] read_mem_data, // Data from system memory |
output mem_req_ack, // Memory bus transaction complete |
/xgate/trunk/rtl/verilog/xgate_regs.v
1,6 → 1,6
//////////////////////////////////////////////////////////////////////////////// |
// |
// Computer Operating Properly - Control registers |
// XGATE Coprocessor - Control registers |
// |
// Author: Bob Hayes |
// rehayes@opencores.org |
60,10 → 60,9
output reg clear_xgif_1, // Strobe for decode to clear interrupt flag bank 1 |
output reg clear_xgif_0, // Strobe for decode to clear interrupt flag bank 0 |
output reg [15:0] clear_xgif_data, // Data for decode to clear interrupt flag |
output semaph_stat, // Return Status of Semaphore bit |
output reg brk_irq_ena, // Enable BRK instruction to generate interrupt |
output [MAX_CHANNEL:1] chan_bypass, // XGATE Interrupt enable or bypass |
output reg [127:1] irq_bypass, // Register to hold irq bypass control state |
output reg [MAX_CHANNEL:1] irq_bypass, // Register to hold irq bypass control state |
|
input bus_clk, // Control register bus clock |
input async_rst_b, // Async reset signal |
96,7 → 95,7
integer k; // Loop counter for channel bypass counter assigments |
|
// registers |
reg [127:1] irq_bypass_d; // Pseudo regester for routing address and data to irq bypass register |
reg [MAX_CHANNEL:1] irq_bypass_d; // Pseudo regester for routing address and data to irq bypass register |
|
// Wires |
wire [ 1:0] write_any_xgif; |
278,9 → 277,9
// Synthesys should eliminate bits that with D input tied to zero |
always @(posedge bus_clk or negedge async_rst_b) |
if ( !async_rst_b ) |
irq_bypass <= {127{1'b1}}; |
irq_bypass <= {MAX_CHANNEL{1'b1}}; |
else if (sync_reset) |
irq_bypass <= {127{1'b1}}; |
irq_bypass <= {MAX_CHANNEL{1'b1}}; |
else |
irq_bypass <= irq_bypass_d; |
|
/xgate/trunk/rtl/verilog/xgate_top.v
67,7 → 67,7
input [DWIDTH-1:0] wbm_dat_i, // databus input |
input wbm_ack_i, // bus cycle acknowledge input |
// XGATE IO Signals |
output [ 7:0] xgswt, // XGATE Software Trigger Register |
output [ 7:0] xgswt, // XGATE Software Trigger Register |
output xg_sw_irq, // Xgate Software interrupt |
output [MAX_CHANNEL:1] xgif, // XGATE Interrupt Flag to Host |
input [MAX_CHANNEL:1] chan_req_i, // XGATE Interrupt request |
162,6 → 162,8
wire [ 7:0] host_semap; // Semaphore status for host |
wire write_mem_strb_l; // Strobe for writing low data byte |
wire write_mem_strb_h; // Strobe for writing high data bye |
wire sync_reset; |
wire async_rst_b; |
|
// --------------------------------------------------------------------------- |
// Wishbone Slave Bus interface |
176,7 → 178,6
.wbs_rst_i( wbs_rst_i ), |
.arst_i( arst_i ), |
.wbs_adr_i( wbs_adr_i ), |
.wbs_dat_i( wbs_dat_i ), |
.wbs_we_i( wbs_we_i ), |
.wbs_stb_i( wbs_stb_i ), |
.wbs_cyc_i( wbs_cyc_i ), |
395,9 → 396,6
.wbm_adr_o( wbm_adr_o ), |
.wbm_dat_i( wbm_dat_i ), |
.wbm_ack_i( wbm_ack_i ), |
.wbs_clk_i( wbs_clk_i ), |
.wbs_rst_i( wbs_rst_i ), |
.arst_i( arst_i ), |
// XGATE Control Signals |
.risc_clk( risc_clk ), |
.async_rst_b( async_rst_b ), |