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Rev 96 → Rev 97

/trunk/bench/verilog/oc8051_xrom.v
0,0 → 1,103
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 exteranl program rom ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// external program rom for 8051 core ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/10/17 18:56:13 simont
// initial CVS input
//
//
 
module oc8051_xrom (rst, clk, addr, data, stb_i, cyc_i, ack_o);
 
parameter DELAY=5;
 
 
input rst, clk, stb_i, cyc_i;
input [15:0] addr;
output ack_o;
output [31:0] data;
 
reg ack_o;
reg [31:0] data;
reg [7:0] buff [0:65535];
//reg [7:0] buff [8388607:0];
reg [2:0] cnt;
integer i;
 
 
initial
begin
// for (i=0; i<65536; i=i+1)
// buff [i] = 8'h00;
$readmemh("../../../bench/in/oc8051_xrom.in", buff);
end
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
data <= #1 31'h0;
ack_o <= #1 1'b0;
end else if (stb_i && ((DELAY==3'b000) || (cnt==3'b000))) begin
data <= #1 {buff [addr], buff[addr+1], buff[addr+2], buff[addr+3]};
ack_o <= #1 1'b1;
end else
ack_o <= #1 1'b0;
end
 
always @(posedge clk or posedge rst)
begin
if (rst)
cnt <= #1 DELAY;
else if (cnt == 3'b000)
cnt <= #1 DELAY;
else if (stb_i)
cnt <= #1 cnt - 3'b001;
else cnt <= #1 DELAY;
end
 
 
endmodule
 
 
trunk/bench/verilog/oc8051_xrom.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bench/verilog/oc8051_xram.v =================================================================== --- trunk/bench/verilog/oc8051_xram.v (nonexistent) +++ trunk/bench/verilog/oc8051_xram.v (revision 97) @@ -0,0 +1,130 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// 8051 external data ram //// +//// //// +//// This file is part of the 8051 cores project //// +//// http://www.opencores.org/cores/8051/ //// +//// //// +//// Description //// +//// external data ram //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Simon Teran, simont@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.4 2002/10/17 18:53:04 simont +// added parameter DELAY +// +// Revision 1.3 2002/09/30 17:34:01 simont +// prepared header +// +// + +// synopsys translate_off +`include "oc8051_timescale.v" +// synopsys translate_on + + +module oc8051_xram (clk, rst, wr, addr, data_in, data_out, ack, stb); +// +// external data ram for simulation. part of oc8051_tb +// it's tehnology dependent +// +// clk (in) clock +// addr (in) addres +// data_in (out) data input +// data_out (in) data output +// wr (in) write +// ack (out) acknowlage +// stb (in) strobe +// + +parameter DELAY=1; + + +input clk, wr, stb, rst; +input [7:0] data_in; +input [15:0] addr; +output [7:0] data_out; +output ack; + +reg ackw, ackr; +reg [7:0] data_out; +reg [2:0] cnt; + +// +// buffer +reg [7:0] buff [65535:0]; //64kb +//reg [7:0] buff [8388607:0]; //8Mb + +assign ack = ackw || ackr; + + +// +// writing to ram +always @(posedge clk or posedge rst) +begin + if (rst) + ackw <= #1 1'b0; + else if (wr && stb && ((DELAY==3'b000) || (cnt==3'b000))) begin + buff[addr] <= #1 data_in; + ackw <= #1 1'b1; + end else ackw <= #1 1'b0; +end + +always @(posedge clk or posedge rst) + if (rst) + ackr <= #1 1'b0; + else if (stb && !wr && ((DELAY==3'b000) || (cnt==3'b000))) begin + data_out <= #1 buff[addr]; + ackr <= #1 1'b1; + end else begin + ackr <= #1 1'b0; + data_out <= #1 8'h00; + end + +always @(posedge clk or posedge rst) +begin + if (rst) + cnt <= #1 DELAY; + else if (cnt==3'b000) + cnt <= #1 DELAY; + else if (stb) + cnt <= #1 cnt - 3'b001; + else cnt <= #1 DELAY; +end + + +endmodule Index: trunk/bench/verilog/oc8051_uart_test.v =================================================================== --- trunk/bench/verilog/oc8051_uart_test.v (nonexistent) +++ trunk/bench/verilog/oc8051_uart_test.v (revision 97) @@ -0,0 +1,106 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// 8051 uart test //// +//// //// +//// This file is part of the 8051 cores project //// +//// http://www.opencores.org/cores/8051/ //// +//// //// +//// Description //// +//// submodul of oc8051_tb, used to comunicate with 8051 //// +//// serial potr //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Simon Teran, simont@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.4 2002/09/30 17:34:01 simont +// prepared header +// +// + +// synopsys translate_off +`include "oc8051_timescale.v" +// synopsys translate_on + + +module oc8051_uart_test (clk, rst, addr, wr, wr_bit, data_in, data_out, bit_out, rxd, txd, ow, intr, ack, stb); +// +// serial interface simulation. part of oc8051_tb +// +// clk (in) clock +// rst (in) reset +// addr (in) addres [oc8051.ext_addr] +// wr (in) write [oc8051.write] +// wr_bit (in) write bit addresable [oc8051.p3_out.0] +// data_in (out) data input [oc8051.data_out] +// data_out (in) data output [oc8051.data_in] +// rxd (in) receive data [oc8051.txd] +// txd (out) transmit data [oc8051.rxd] +// ow (in) owerflov (used in mode 1 and 3) [oc8051.p3_out.1] +// intr (out) interrupt request [oc8051.p3_in.0] +// + +input clk, rst, wr, wr_bit, rxd, ow, stb; +input [7:0] addr, data_in; + +output txd, intr, bit_out, ack; +output [7:0] data_out; + +wire syn; +reg wr_r, ack; +reg [7:0] addr_r, data_in_r; + + +oc8051_uart oc8051_uart_test(.rst(rst), .clk(clk), .bit_in(data_in[0]), .rd_addr(addr), .data_in(data_in_r), + .wr(wr_r), .wr_bit(wr_bit), .wr_addr(addr_r), .data_out(data_out), .bit_out(bit_out), + .rxd(rxd), .txd(txd), .intr(intr), .t1_ow(ow)); + + +always @(posedge clk) +begin + if (ack) ack <= #1 1'b0; + else + ack <= #1 stb; +end + +always @(posedge clk) +begin + wr_r <= #1 wr; + addr_r <= #1 addr; + data_in_r <= #1 data_in; +end + + +endmodule Index: trunk/bench/vec/testall.vec~ =================================================================== --- trunk/bench/vec/testall.vec~ (nonexistent) +++ trunk/bench/vec/testall.vec~ (revision 97) @@ -0,0 +1,7 @@ +//// +//// +//// test vectors for testall +//// +//// +ffffff +7fxxxx
trunk/bench/vec/testall.vec~ Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bench/vec/serial_test.vec =================================================================== --- trunk/bench/vec/serial_test.vec (nonexistent) +++ trunk/bench/vec/serial_test.vec (revision 97) @@ -0,0 +1,10 @@ +//// +//// +//// test vectors for serial_test +//// +//// +ffffff +00xxxx +01xxxx +02xxxx +03xxxx Index: trunk/bench/vec/counter_test.vec =================================================================== --- trunk/bench/vec/counter_test.vec (nonexistent) +++ trunk/bench/vec/counter_test.vec (revision 97) @@ -0,0 +1,8 @@ +//// +//// +//// test vectors for counter_test +//// +//// +ffffff +01xxxx +02xxxx Index: trunk/bench/vec/timer_test.vec =================================================================== --- trunk/bench/vec/timer_test.vec (nonexistent) +++ trunk/bench/vec/timer_test.vec (revision 97) @@ -0,0 +1,8 @@ +//// +//// +//// test vectors for timer_test +//// +//// +ffffff +01xxxx +02xxxx Index: trunk/bench/vec/wdog1.vec =================================================================== --- trunk/bench/vec/wdog1.vec (nonexistent) +++ trunk/bench/vec/wdog1.vec (revision 97) @@ -0,0 +1,12 @@ +//// +//// +//// test vectors for wdog1 +//// +//// +ffffff +00xxxx +02xxxx +03xxxx +04xxxx +ffxxxx +00xxxx Index: trunk/bench/vec/xrom_test.vec~ =================================================================== --- trunk/bench/vec/xrom_test.vec~ (nonexistent) +++ trunk/bench/vec/xrom_test.vec~ (revision 97) @@ -0,0 +1,7 @@ +//// +//// +//// test vectors for test_xram +//// +//// +ffffff +11xxxx Index: trunk/bench/vec/wdog2.vec =================================================================== --- trunk/bench/vec/wdog2.vec (nonexistent) +++ trunk/bench/vec/wdog2.vec (revision 97) @@ -0,0 +1,10 @@ +//// +//// +//// test vectors for wdog2 +//// +//// +ffffff +00xxxx +01xxxx +ffxxxx +00xxxx Index: trunk/bench/vec/xram_m.vec =================================================================== --- trunk/bench/vec/xram_m.vec (nonexistent) +++ trunk/bench/vec/xram_m.vec (revision 97) @@ -0,0 +1,7 @@ +//// +//// +//// test vectors for xram_m +//// +//// +ffffff +01xxxx Index: trunk/bench/vec/wdog3.vec =================================================================== --- trunk/bench/vec/wdog3.vec (nonexistent) +++ trunk/bench/vec/wdog3.vec (revision 97) @@ -0,0 +1,11 @@ +//// +//// +//// test vectors for wdog1 +//// +//// +ffffff +00xxxx +01xxxx +02xxxx +ffxxxx +00xxxx Index: trunk/bench/vec/gcd.vec~ =================================================================== --- trunk/bench/vec/gcd.vec~ (nonexistent) +++ trunk/bench/vec/gcd.vec~ (revision 97) @@ -0,0 +1,11 @@ +//// +//// +//// test vectors for gcd +//// +//// +ffffff +24xxxx +19xxxx +0exxxx +03xxxx +01xxxx
trunk/bench/vec/gcd.vec~ Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bench/vec/gcd.vec =================================================================== --- trunk/bench/vec/gcd.vec (nonexistent) +++ trunk/bench/vec/gcd.vec (revision 97) @@ -0,0 +1,16 @@ +//// +//// +//// test vectors for gcd +//// +//// +ffffff +24xxxx +19xxxx +0exxxx +03xxxx +0308xx +0305xx +0302xx +0102xx +0101xx +010101
trunk/bench/vec/gcd.vec Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bench/vec/fib.vec =================================================================== --- trunk/bench/vec/fib.vec (nonexistent) +++ trunk/bench/vec/fib.vec (revision 97) @@ -0,0 +1,15 @@ +//// +//// +//// test vectors for fib +//// +//// +ffffff +01xxxx +02xxxx +03xxxx +05xxxx +08xxxx +0dxxxx +15xxxx +22xxxx +37xxxx
trunk/bench/vec/fib.vec Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bench/vec/timer2_test.vec =================================================================== --- trunk/bench/vec/timer2_test.vec (nonexistent) +++ trunk/bench/vec/timer2_test.vec (revision 97) @@ -0,0 +1,22 @@ +//// +//// +//// test vectors for timer2_test +//// +//// +ffffff +01xxxx +02xxxx +03xxxx +04xxxx +05xxxx +06xxxx +07xxxx +08xxxx +09xxxx +0axxxx +0bxxxx +0cxxxx +0dxxxx +0exxxx +0fxxxx +10xxxx Index: trunk/bench/vec/pca_test.vec =================================================================== --- trunk/bench/vec/pca_test.vec (nonexistent) +++ trunk/bench/vec/pca_test.vec (revision 97) @@ -0,0 +1,18 @@ +//// +//// +//// test vectors for pca_test +//// +//// +ffffff +00xxxx +01xxxx +02xxxx +03xxxx +04xxxx +05xxxx +06xxxx +07xxxx +08xxxx +09xxxx +0axxxx +00xxxx
trunk/bench/vec/pca_test.vec Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bench/vec/int2bin.vec =================================================================== --- trunk/bench/vec/int2bin.vec (nonexistent) +++ trunk/bench/vec/int2bin.vec (revision 97) @@ -0,0 +1,14 @@ +//// +//// +//// test vectors for int2bin +//// +//// +ffffff +00xxxx +01xxxx +00xxxx +01xxxx +00xxxx +01xxxx +00xxxx +01xxxx
trunk/bench/vec/int2bin.vec Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bench/vec/test_xram.vec =================================================================== --- trunk/bench/vec/test_xram.vec (nonexistent) +++ trunk/bench/vec/test_xram.vec (revision 97) @@ -0,0 +1,7 @@ +//// +//// +//// test vectors for test_xram +//// +//// +ffffff +11xxxx Index: trunk/bench/vec/testall.vec =================================================================== --- trunk/bench/vec/testall.vec (nonexistent) +++ trunk/bench/vec/testall.vec (revision 97) @@ -0,0 +1,7 @@ +//// +//// +//// test vectors for testall +//// +//// +ffffff +xx7fxx
trunk/bench/vec/testall.vec Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bench/vec/interrupt_test2.vec =================================================================== --- trunk/bench/vec/interrupt_test2.vec (nonexistent) +++ trunk/bench/vec/interrupt_test2.vec (revision 97) @@ -0,0 +1,17 @@ +//// +//// +//// test vectors for interrupt_test2 +//// +//// +ffffff +02xxxx +00xxxx +03xxxx +04xxxx +01xxxx +03xxxx +02xxxx +04xxxx +01xxxx +00xxxx +11xxxx Index: trunk/bench/vec/oc8051_test.vec =================================================================== --- trunk/bench/vec/oc8051_test.vec (nonexistent) +++ trunk/bench/vec/oc8051_test.vec (revision 97) @@ -0,0 +1,7 @@ +//// +//// +//// test vectors for testall +//// +//// +ffffff +xx7fxx
trunk/bench/vec/oc8051_test.vec Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bench/vec/negcnt.vec =================================================================== --- trunk/bench/vec/negcnt.vec (nonexistent) +++ trunk/bench/vec/negcnt.vec (revision 97) @@ -0,0 +1,16 @@ +//// +//// +//// test vectors for Negcnt +//// +//// +ffffff +40xxxx +41xxxx +42xxxx +43xxxx +44xxxx +45xxxx +46xxxx +47xxxx +48xxxx +49xxxx
trunk/bench/vec/negcnt.vec Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bench/vec/div16u.vec =================================================================== --- trunk/bench/vec/div16u.vec (nonexistent) +++ trunk/bench/vec/div16u.vec (revision 97) @@ -0,0 +1,18 @@ + +//// +//// +//// test vectors for div16u +//// +//// +ffffff +00xxxx +70xxxx +00xxxx +54xxxx +02xxxx +01xxxx +0cxxxx +00xxxx +e2xxxx +50xxxx +00xxxx
trunk/bench/vec/div16u.vec Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bench/vec/mx_test.vec~ =================================================================== --- trunk/bench/vec/mx_test.vec~ (nonexistent) +++ trunk/bench/vec/mx_test.vec~ (revision 97) @@ -0,0 +1,9 @@ +//// +//// +//// test vectors for mx_test +//// +//// +ffffff +01xxxx +02xxxx +03xxxx
trunk/bench/vec/mx_test.vec~ Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bench/vec/mx_test.vec =================================================================== --- trunk/bench/vec/mx_test.vec (nonexistent) +++ trunk/bench/vec/mx_test.vec (revision 97) @@ -0,0 +1,11 @@ +//// +//// +//// test vectors for mx_test +//// +//// +ffffff +01xxxx +02xxxx +03xxxx +04xxxx +05xxxx
trunk/bench/vec/mx_test.vec Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bench/vec/xrom_test.vec =================================================================== --- trunk/bench/vec/xrom_test.vec (nonexistent) +++ trunk/bench/vec/xrom_test.vec (revision 97) @@ -0,0 +1,11 @@ +//// +//// +//// test vectors for xrom_test +//// +//// +ffffff +90xxxx +00xxxx +01xxxx +02xxxx +eexxxx Index: trunk/bench/vec/stdout.log =================================================================== Index: trunk/bench/vec/lcall.vec =================================================================== --- trunk/bench/vec/lcall.vec (nonexistent) +++ trunk/bench/vec/lcall.vec (revision 97) @@ -0,0 +1,8 @@ +//// +//// +//// test vectors for lcall +//// +//// +ffffff +0axxxx +04xxxx
trunk/bench/vec/lcall.vec Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bench/vec/sort.vec =================================================================== --- trunk/bench/vec/sort.vec (nonexistent) +++ trunk/bench/vec/sort.vec (revision 97) @@ -0,0 +1,17 @@ +//// +//// +//// test vectors for sort +//// +//// +ffffff +00xxxx +0axxxx +0bxxxx +0cxxxx +0dxxxx +0exxxx +0fxxxx +10xxxx +11xxxx +12xxxx +13xxxx
trunk/bench/vec/sort.vec Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bench/vec/sqroot.vec =================================================================== --- trunk/bench/vec/sqroot.vec (nonexistent) +++ trunk/bench/vec/sqroot.vec (revision 97) @@ -0,0 +1,10 @@ +//// +//// +//// test vectors for sqroot +//// +//// +ffffff +09xxxx +xx10xx +xxxx19 +05xxxx
trunk/bench/vec/sqroot.vec Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bench/vec/cast.vec =================================================================== --- trunk/bench/vec/cast.vec (nonexistent) +++ trunk/bench/vec/cast.vec (revision 97) @@ -0,0 +1,10 @@ +//// +//// +//// test vectors for cast +//// +//// +ffffff +01xxxx +xx23xx +xxxx45 +67xxxx
trunk/bench/vec/cast.vec Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/bench/vec/interrupt_test.vec =================================================================== --- trunk/bench/vec/interrupt_test.vec (nonexistent) +++ trunk/bench/vec/interrupt_test.vec (revision 97) @@ -0,0 +1,8 @@ +//// +//// +//// test vectors for interrupt_test +//// +//// +ffffff +01xxxx +02xxxx Index: trunk/bench/vec/r_bank.vec =================================================================== --- trunk/bench/vec/r_bank.vec (nonexistent) +++ trunk/bench/vec/r_bank.vec (revision 97) @@ -0,0 +1,11 @@ +//// +//// +//// test vectors for r_bank +//// +//// +ffffff +00xxxx +01xxxx +02xxxx +03xxxx +04xxxx Index: trunk/bench/vec/divmul.vec =================================================================== --- trunk/bench/vec/divmul.vec (nonexistent) +++ trunk/bench/vec/divmul.vec (revision 97) @@ -0,0 +1,9 @@ +//// +//// +//// test vectors for divmul +//// +//// +ffffff +0axxxx +04xxxx +86xxxx
trunk/bench/vec/divmul.vec Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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