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Rev 96 → Rev 97

/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
1,3 → 1,5
versatile_library.v:
async_fifo_dw_simplex_actel.v:
svn export http://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk/rtl/verilog/async_fifo_dw_simplex_actel.v
 
11,9 → 13,12
excel2csv ref_counter.xls -S ,
./versatile_counter_generator.php ref_counter.csv > ref_counter.v
 
sdr_sdram_16_ctrl_actel.v: sdr_sdram_16_ctrl.v ref_counter.v sdr_16_defines.v async_fifo_dw_simplex_actel.v
sdr_sdram_16_ctrl_actel.v:
vppreproc --noline --noblank +define+RFR_LENGTH+10 +define+RFR_WRAP_VALUE+1001 +define+ACTEL sdr_sdram_16_ctrl.v > sdr_sdram_16_ctrl_actel.v
 
export:
svn export http://opencores.org/ocsvn/versatile_library/versatile_library/trunk/rtl/verilog/versatile_library.v
# the single all rule
all: sdr_sdram_16_ctrl_actel.v
 
/versatile_mem_ctrl/trunk/rtl/verilog/wbwb_bridge.v
1,4 → 1,5
module wbwb_bridge (
`timescale 1ns/1ns
module wbwb_bridge (
// wishbone slave side
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
// wishbone master side
37,97 → 38,151
parameter incburst = 3'b010;
parameter endofburst = 3'b111;
 
parameter adr = 1'b0;
parameter data = 1'b1;
parameter wbs_adr = 1'b0;
parameter wbs_data = 1'b1;
 
reg wbs_we_reg, wbs_bte_reg, wbs, wbm;
parameter wbm_adr0 = 2'b00;
parameter wbm_adr1 = 2'b01;
parameter wbm_data = 2'b10;
parameter wbm_wait = 2'b11;
 
reg wbs_we_reg;
reg [1:0] wbs_bte_reg;
reg wbs;
wire wbs_eoc_alert, wbm_eoc_alert;
reg wbs_eoc, wbm_eoc;
reg [1:0] wbm;
 
reg [1:16] wbs_count, wbm_count;
 
reg wbs_ack_o_rd;
wire wbs_ack_o_wr;
 
wire [35:0] a_d, a_q, b_d, b_q;
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
reg a_rd_reg;
wire b_rd_adr, b_rd_data;
reg b_rd_data_reg;
reg [35:0] temp;
 
reg [1:16] count;
reg count_zero;
`define WE 5
`define BTE 4:3
`define CTI 2:0
 
`define WBS_EOC (wbs_bte_i==linear | wbs_cti_i==endofburst) & wbs_cyc_i & wbs_stb_i
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
wbs <= adr;
wbs_eoc <= 1'b0;
else
if (wbs_cyc_i & wbs_stb_i & (wbs==adr) & !a_fifo_full)
wbs <= data;
else if ((`WBS_EOC & !a_fifo_full) & (a_rd | (wbs_stb_i & wbs_we_i)))
wbs <= adr;
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
wbs_eoc <= wbs_bte_i==linear;
else if (wbs_eoc_alert & (a_rd | a_wr))
wbs_eoc <= 1'b1;
 
cnt_shreg_ce_clear # ( .length(16))
cnt0 (
.cke(wbs_ack_o),
.clear(wbs_eoc),
.q(wbs_count),
.rst(wbs_rst),
.clk(wbs_clk));
 
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
wbs <= wbs_adr;
else
if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
wbs <= wbs_data;
else if (wbs_eoc & wbs_ack_o)
wbs <= wbs_adr;
 
// wbs FIFO
assign a_d = (wbs==adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
assign a_wr = ((wbs== adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full) ? 1'b1 :
((wbs==data) & wbs_cyc_i & wbs_stb_i & !a_fifo_full & wbs_we_i) ? 1'b1 :
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
assign a_wr = (wbs==wbs_adr) ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
(wbs==wbs_data) ? wbs_we_i & wbs_stb_i & !a_fifo_full :
1'b0;
assign wbs_dat_o = a_q[35:4];
assign a_rd = !a_fifo_empty;
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
wbs_ack_o_rd <= 1'b0;
a_rd_reg <= 1'b0;
else
wbs_ack_o_rd <= a_rd;
a_rd_reg <= a_rd;
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
 
assign wbs_dat_o = a_q[35:4];
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
{wbs_we_reg,wbs_bte_reg} <= 2'b00;
{wbs_we_reg,wbs_bte_reg} <= {1'b0,2'b00};
else
{wbs_we_reg,wbs_bte_reg} <= {wbs_we_i,|wbs_bte_i};
{wbs_we_reg,wbs_bte_reg} <= {wbs_we_i,wbs_bte_i};
 
assign wbs_ack_o_wr = wbs==data & wbs_we_reg & wbs_stb_i;
 
assign wbs_ack_o = wbs_ack_o_rd | wbs_ack_o_wr;
// wbm FIFO
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
wbm <= adr;
wbm_eoc <= 1'b0;
else
if (!b_fifo_empty)
wbm <= data;
else if (wbm_ack_i & ((b_q[4:3]==wrap4 & count[3]) | (b_q[4:3]==wrap8 & count[7]) | (b_q[4:3]==wrap16 & count[15])))
wbm <= adr;
assign b_d = {wbm_dat_i,4'b1111};
assign b_wr = !wbm_we_o & wbm_ack_i;
assign b_rd = (wbm==adr & !b_fifo_empty) ? 1'b1 :
(wbm==data & wbm_ack_i) ? 1'b1 :
1'b0;
if (wbm==wbm_adr0 & !b_fifo_empty)
wbm_eoc <= b_q[`BTE] == linear;
else if (wbm_eoc_alert & wbm_ack_i)
wbm_eoc <= 1'b1;
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
{count,count_zero} <= {16'h8000,1'b1};
wbm <= wbm_adr0;
else
casex ({b_fifo_empty,wbm_bte_o,count,count_zero,wbm_ack_i})
{1'b0,linear,16'b1xxxxxxxxxxxxxxx,1'bx,1'b1}: {count, count_zero} <= {16'h8000,1'b1};
{1'b0,wrap4 ,16'bxxx1xxxxxxxxxxxx,1'bx,1'b1}: {count, count_zero} <= {16'h8000,1'b1};
{1'b0,wrap8 ,16'bxxxxxxx1xxxxxxxx,1'bx,1'b1}: {count, count_zero} <= {16'h8000,1'b1};
{1'b0,wrap16,16'bxxxxxxxxxxxxxxx1,1'bx,1'b1}: {count, count_zero} <= {16'h8000,1'b1};
{1'b0,2'bxx,{16{1'bx}},1'b0,1'b1} : {count, count_zero} <= {count >> 1,1'b0};
default : ;
casex ({wbm,b_fifo_empty,wbm_we_o,wbm_ack_i,wbm_eoc}) // ,b_q[`WE]
{wbm_adr0,1'b0,1'bx,1'bx,1'bx} : wbm <= wbm_adr1; // if write wait for !fifo_empty
{wbm_adr1,1'b0,1'b1,1'bx,1'bx} : wbm <= wbm_data; // if write wait for !fifo_empty
{wbm_adr1,1'bx,1'b0,1'bx,1'bx} : wbm <= wbm_data; // if read go ahead
{wbm_data,1'bx,1'bx,1'b1,1'b1} : wbm <= wbm_adr0; //
{wbm_wait,1'bx,1'bx,1'bx,1'bx} : wbm <= wbm_adr0;
default : wbm <= wbm;
endcase
assign wbm_cyc_o = wbm;
assign wbm_stb_o = (wbm==adr) ? 1'b0 :
(wbm==data & wbm_we_o) ? !b_fifo_empty :
1'b1;
assign b_d = {wbm_dat_i,4'b1111};
assign b_wr = !wbm_we_o & wbm_ack_i;
assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty);
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1'b0;
assign b_rd = b_rd_adr | b_rd_data;
 
dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
 
cnt_shreg_ce_clear # ( .length(16))
cnt1 (
.cke(wbm_ack_i),
.clear(wbm_eoc),
.q(wbm_count),
.rst(wbm_rst),
.clk(wbm_clk));
 
assign wbm_cyc_o = wbm==wbm_data;
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
(wbm==wbm_data) ? 1'b1 :
1'b0;
 
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {32'h0,1'b0,linear,classic};
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
else begin
if (wbm==adr & !b_fifo_empty)
if (wbm==wbm_adr0 & !b_fifo_empty)
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
else if ((b_q[4:3]==wrap4 & count[3]) | (b_q[4:3]==wrap8 & count[7]) | (b_q[4:3]==wrap16 & count[15]))
else if (wbm_eoc_alert & wbm_ack_i)
wbm_cti_o <= endofburst;
end
assign {wbm_dat_o,wbm_sel_o} = b_q;
//assign {wbm_dat_o,wbm_sel_o} = b_q;
 
async_fifo_dw_simplex_top
//async_fifo_dw_simplex_top
vl_fifo_2r2w_async_simplex
# ( .data_width(36), .addr_width(addr_width))
fifo (
// a side
// a side
.a_d(a_d),
.a_wr(a_wr),
.a_fifo_full(a_fifo_full),
134,9 → 189,9
.a_q(a_q),
.a_rd(a_rd),
.a_fifo_empty(a_fifo_empty),
.a_clk(wbs_clk),
.a_rst(wbs_rst),
// b side
.a_clk(wbs_clk),
.a_rst(wbs_rst),
// b side
.b_d(b_d),
.b_wr(b_wr),
.b_fifo_full(b_fifo_full),
143,8 → 198,8
.b_q(b_q),
.b_rd(b_rd),
.b_fifo_empty(b_fifo_empty),
.b_clk(wbm_clk),
.b_rst(wbm_rst)
.b_clk(wbm_clk),
.b_rst(wbm_rst)
);
endmodule
/versatile_mem_ctrl/trunk/rtl/verilog/sdr_sdram_16_ctrl.v
14,14 → 14,13
// system
clk, rst);
 
/* Now these are defined
parameter ba_size = 2;
parameter row_size = 13;
parameter col_size = 9;
*/
parameter col_size = 9;
parameter cl = 2;
input [31:0] dat_i;
input [`BA_SIZE+`COL_SIZE+`ROW_SIZE-1:2] adr_i;
input [ba_size+col_size+row_size:1] adr_i;
input [3:0] sel_i;
input [2:0] cti_i;
input [1:0] bte_i;
29,33 → 28,36
output reg [31:0] dat_o;
output ack_o;
 
output reg [1:0] ba `SYN;
output reg [12:0] a `SYN;
output reg [2:0] cmd `SYN;
output reg [1:0] ba `SYN;
output reg [12:0] a `SYN;
output reg [2:0] cmd `SYN;
output cke, cs_n;
output reg [1:0] dqm `SYN;
output reg [1:0] dqm `SYN;
output reg [15:0] dq_o `SYN;
output reg dq_oe;
input [15:0] dq_i;
output reg dq_oe;
input [15:0] dq_i;
 
input clk, rst;
 
wire [`BA_SIZE-1:0] bank;
wire [`ROW_SIZE-1:0] row;
wire [`COL_SIZE-1:0] col;
wire [12:0] col_a10_fix;
reg [4:0] col_reg;
reg [0:31] shreg;
reg count0;
wire stall; // active if write burst need data
reg refresh_req, cmd_aref;
reg cmd_read;
reg wb_flag;
wire [ba_size-1:0] bank;
wire [row_size-1:0] row;
wire [col_size-1:0] col;
wire [12:0] col_a10_fix;
reg [4:0] col_reg;
wire [0:31] shreg;
reg count0;
wire stall; // active if write burst need data
reg ref_cnt_zero, refresh_req;
reg cmd_read;
reg wb_flag;
reg [1:6] ack_rd;
wire ack_wr;
 
// to keep track of open rows per bank
reg [`ROW_SIZE-1:0] open_row[0:3];
reg [0:3] open_ba;
reg current_bank_closed, current_row_open;
reg [row_size-1:0] open_row[0:3];
reg [0:3] open_ba;
reg current_bank_closed, current_row_open;
`ifndef RFR_WRAP_VALUE
parameter rfr_length = 10;
88,18 → 90,18
//`define FSM_W4D 3'b110
`define FSM_RW 3'b111
 
assign cke = 1'b1;
assign cs_n = 1'b0;
assign cke = 1'b1;
assign cs_n = 1'b0;
reg [2:0] state, next;
reg [2:0] state, next;
 
function [12:0] a10_fix;
input [`COL_SIZE-1:0] a;
integer i;
begin
for (i=0;i<13;i=i+1) begin
function [12:0] a10_fix;
input [col_size-1:0] a;
integer i;
begin
for (i=0;i<13;i=i+1) begin
if (i<10)
if (i<`COL_SIZE)
if (i<col_size)
a10_fix[i] = a[i];
else
a10_fix[i] = 1'b0;
106,216 → 108,231
else if (i==10)
a10_fix[i] = 1'b0;
else
if (i<`COL_SIZE)
if (i<col_size)
a10_fix[i] = a[i-1];
else
a10_fix[i] = 1'b0;
end
end
endfunction
end
end
endfunction
 
assign {bank,row,col} = adr_i;
 
assign {bank,row,col} = adr_i;
 
always @ (posedge clk or posedge rst) begin
if (rst)
always @ (posedge clk or posedge rst) begin
if (rst)
state <= `FSM_INIT;
else
state <= next; end
else
state <= next;
end
always @*
begin
next = 3'bx;
case (state)
`FSM_INIT:
if (shreg[31]) next = `FSM_IDLE;
else next = `FSM_INIT;
`FSM_IDLE:
if (refresh_req) next = `FSM_RFR;
else if (cyc_i & stb_i) next = `FSM_ADR;
always @*
begin
next = 3'bx;
case (state)
`FSM_INIT:
if (shreg[31]) next = `FSM_IDLE;
else next = `FSM_INIT;
`FSM_IDLE:
if (refresh_req) next = `FSM_RFR;
else if (cyc_i & stb_i & !(|ack_rd)) next = `FSM_ADR;
else next = `FSM_IDLE;
`FSM_RFR:
if (shreg[5]) next = `FSM_IDLE;
`FSM_RFR:
if (shreg[8]) next = `FSM_IDLE; // tRFC=60ns, AREF@2
else next = `FSM_RFR;
`FSM_ADR:
if (current_bank_closed) next = `FSM_ACT;
else if (current_row_open)
next = `FSM_RW;
else next = `FSM_PCH;
`FSM_PCH:
if (shreg[1]) next = `FSM_ACT;
else next = `FSM_PCH;
`FSM_ACT:
if (shreg[2]) next = `FSM_RW;
`FSM_ADR:
if (current_bank_closed) next = `FSM_ACT;
else if (current_row_open) next = `FSM_RW;
else next = `FSM_PCH;
`FSM_PCH:
if (shreg[1]) next = `FSM_ACT;
else next = `FSM_PCH;
`FSM_ACT:
if (shreg[2]) next = `FSM_RW;
else next = `FSM_ACT;
// `FSM_W4D:
// if (!fifo_empty) next = `FSM_RW;
// else next = `FSM_W4D;
`FSM_RW:
if (bte_i==linear & shreg[1])
next = `FSM_IDLE;
else if (bte_i==beat4 & shreg[7])
next = `FSM_IDLE;
// `FSM_W4D:
// if (!fifo_empty) next = `FSM_RW;
// else next = `FSM_W4D;
`FSM_RW:
if (bte_i==linear & shreg[1]) next = `FSM_IDLE;
else if (bte_i==beat4 & shreg[7]) next = `FSM_IDLE;
`ifdef BEAT8
else if (bte_i==beat8 & shreg[15])
next = `FSM_IDLE;
else if (bte_i==beat8 & shreg[15])
next = `FSM_IDLE;
`endif
`ifdef BEAT16
else if (bte_i==beat16 & shreg[31])
next = `FSM_IDLE;
else if (bte_i==beat16 & shreg[31]) next = `FSM_IDLE;
`endif
else
next = `FSM_RW;
endcase
end
else next = `FSM_RW;
endcase
end
 
// active if write burst need data
assign stall = state==`FSM_RW & next==`FSM_RW & ~stb_i & count0 & we_i;
// active if write burst need data
assign stall = state==`FSM_RW & next==`FSM_RW & ~stb_i & count0 & we_i;
// flag indicates active wb cycle
always @ (posedge clk or posedge rst)
if (rst)
wb_flag <= 1'b0;
else
if (state==`FSM_ADR)
wb_flag <= 1'b1;
else if ((cti_i==3'b000 | cti_i==3'b111) & ack_o)
wb_flag <= 1'b0;
 
// counter
always @ (posedge clk or posedge rst)
if (rst)
{shreg,count0} <= {32'h80000000,1'b0};
// flag indicates active wb cycle
always @ (posedge clk or posedge rst)
if (rst)
wb_flag <= 1'b0;
else
if (!stall)
if (state==next)
{shreg,count0} <= {shreg >> 1,!count0};
else
{shreg,count0} <= {32'h80000000,1'b0};
// else if (state!=next)
// {shreg,count0} <= {1'b1,{31{1'b0}},1'b0};
// else if (~stall)
// {shreg,count0} <= {shreg >> 1,!count0};
if (state==`FSM_ADR)
wb_flag <= 1'b1;
else if ((cti_i==3'b000 | cti_i==3'b111) & ack_o)
wb_flag <= 1'b0;
//// counter
//always @ (posedge clk or posedge rst)
//if (rst)
// {shreg,count0} <= {32'h80000000,1'b0};
//else
// if (!stall)
// if (state==next)
// {shreg,count0} <= {shreg >> 1,!count0};
// else
// {shreg,count0} <= {32'h80000000,1'b0};
// counter
cnt_shreg_ce_clear # ( .length(32))
cnt0 (
.cke(!stall),
.clear(!(state==next)),
.q(shreg),
.rst(rst),
.clk(clk));
dff_ce_clear
dff_count0 (
.d(!count0),
.ce(!stall),
.clear(!(state==next)),
.q(count0),
.rst(rst),
.clk(clk));
 
// ba, a, cmd
// col_reg_a10 has bit [10] set to zero to disable auto precharge
assign col_a10_fix = a10_fix({col[`COL_SIZE-1:5],col_reg});
// ba, a, cmd
// col_reg_a10 has bit [10] set to zero to disable auto precharge
assign col_a10_fix = a10_fix({col[col_size-1:5],col_reg});
 
// outputs dependent on state vector
always @ (posedge clk or posedge rst)
// outputs dependent on state vector
always @ (posedge clk or posedge rst)
begin
if (rst) begin
{ba,a,cmd} <= {2'b00,13'd0,cmd_nop};
dqm <= 2'b11;
cmd_aref <= 1'b0;
dq_oe <= 1'b0;
col_reg <= 5'b000;
{open_ba,open_row[0],open_row[1],open_row[2],open_row[3]} <=
{4'b0000,{`ROW_SIZE*4{1'b0}}};
{open_ba,open_row[0],open_row[1],open_row[2],open_row[3]} <= {4'b0000,{row_size*4{1'b0}}};
end else begin
{ba,a,cmd} <= {2'b00,13'd0,cmd_nop};
dqm <= 2'b11;
cmd_aref <= 1'b0;
dq_oe <= 1'b0;
case (state)
`FSM_INIT:
if (shreg[3]) begin
{ba,a,cmd} <= {2'b00, 13'b0010000000000, cmd_pch};
open_ba[bank] <= 1'b0;
end else if (shreg[7] | shreg[19])
{ba,a,cmd,cmd_aref} <= {2'b00, 13'd0, cmd_rfr,1'b1};
else if (shreg[31])
{ba,a,cmd} <=
{2'b00,3'b000,`INIT_WB,2'b00,`INIT_CL,`INIT_BT,`INIT_BL, cmd_lmr};
`FSM_RFR:
{ba,a,cmd} <= {2'b00,13'd0,cmd_nop};
dqm <= 2'b11;
dq_oe <= 1'b0;
case (state)
`FSM_INIT:
if (shreg[3]) begin
{ba,a,cmd} <= {2'b00, 13'b0010000000000, cmd_pch};
open_ba[bank] <= 1'b0;
end else if (shreg[7] | shreg[19])
{ba,a,cmd} <= {2'b00, 13'd0, cmd_rfr};
else if (shreg[31])
{ba,a,cmd} <= {2'b00,3'b000,`INIT_WB,2'b00,`INIT_CL,`INIT_BT,`INIT_BL, cmd_lmr};
`FSM_RFR:
if (shreg[0]) begin
{ba,a,cmd} <= {2'b00, 13'b0010000000000, cmd_pch};
open_ba <= 4'b0000;
end else if (shreg[2])
{ba,a,cmd,cmd_aref} <= {2'b00, 13'd0, cmd_rfr,1'b1};
`FSM_IDLE:
{ba,a,cmd} <= {2'b00, 13'd0, cmd_rfr};
`FSM_IDLE:
col_reg <= col[4:0];
`FSM_PCH:
`FSM_PCH:
if (shreg[0]) begin
{ba,a,cmd} <= {ba,13'd0,cmd_pch};
//open_ba <= 4'b0000;
open_ba[bank] <= 1'b0;
end
`FSM_ACT:
if (shreg[0]) begin
{ba,a,cmd} <= {bank,(13'd0 | row),cmd_act};
{open_ba[bank],open_row[bank]} <= {1'b1,row};
end
`FSM_RW:
begin
if (we_i & !count0)
cmd <= cmd_wr;
else if (!count0)
{cmd,cmd_read} <= {cmd_rd,1'b1};
else
cmd <= cmd_nop;
if (we_i & !count0)
dqm <= ~sel_i[3:2];
else if (we_i & count0)
dqm <= ~sel_i[1:0];
else
dqm <= 2'b00;
if (we_i)
dq_oe <= 1'b1;
if (~stall)
case (bte_i)
linear: {ba,a} <= {bank,col_a10_fix};
beat4: {ba,a,col_reg[2:0]} <= {bank,col_a10_fix, col_reg[2:0] + 3'd1};
`ifdef BEAT8
beat8: {ba,a,col_reg[3:0]} <= {bank,col_a10_fix, col_reg[3:0] + 4'd1};
{ba,a,cmd} <= {ba,13'd0,cmd_pch};
//open_ba <= 4'b0000;
open_ba[bank] <= 1'b0;
end
`FSM_ACT:
if (shreg[0]) begin
{ba,a,cmd} <= {bank,(13'd0 | row),cmd_act};
{open_ba[bank],open_row[bank]} <= {1'b1,row};
end
`FSM_RW:
begin
if (we_i & !count0)
cmd <= cmd_wr;
else if (!count0)
{cmd,cmd_read} <= {cmd_rd,1'b1};
else
cmd <= cmd_nop;
if (we_i & !count0)
dqm <= ~sel_i[3:2];
else if (we_i & count0)
dqm <= ~sel_i[1:0];
else
dqm <= 2'b00;
if (we_i)
dq_oe <= 1'b1;
if (~stall)
case (bte_i)
linear: {ba,a} <= {bank,col_a10_fix};
beat4: {ba,a,col_reg[2:0]} <= {bank,col_a10_fix, col_reg[2:0] + 3'd1};
`ifdef BEAT8
beat8: {ba,a,col_reg[3:0]} <= {bank,col_a10_fix, col_reg[3:0] + 4'd1};
`endif
`ifdef BEAT16
beat16: {ba,a,col_reg[4:0]} <= {bank,col_a10_fix, col_reg[4:0] + 5'd1};
`ifdef BEAT16
beat16: {ba,a,col_reg[4:0]} <= {bank,col_a10_fix, col_reg[4:0] + 5'd1};
`endif
endcase
end
endcase
end
end
endcase
end
endcase
end
end
 
// bank and row open ?
always @ (posedge clk or posedge rst)
if (rst)
// bank and row open ?
always @ (posedge clk or posedge rst)
if (rst)
{current_bank_closed, current_row_open} <= {1'b1, 1'b0};
else
else
//if (state==adr & counter[1:0]==2'b10)
{current_bank_closed, current_row_open} <=
{!(open_ba[bank]), open_row[bank]==row};
{current_bank_closed, current_row_open} <= {!(open_ba[bank]), open_row[bank]==row};
 
// refresch counter
ref_counter
# ( .length(rfr_length), .wrap_value (rfr_wrap_value))
ref_counter0( .zq(ref_cnt_zero), .rst(sdram_rst), .clk(sdram_clk));
always @ (posedge clk or posedge rst)
// refresh counter
cnt_lfsr_zq # ( .length(rfr_length), .wrap_value (rfr_wrap_value)) ref_counter0( .zq(ref_cnt_zero), .rst(rst), .clk(clk));
always @ (posedge clk or posedge rst)
if (rst)
refresh_req <= 1'b0;
else
if (ref_cnt_zero)
refresh_req <= 1'b1;
else if (cmd_aref)
refresh_req <= 1'b0;
refresh_req <= 1'b1;
else if (state==`FSM_RFR)
refresh_req <= 1'b0;
// data to WB
//always @ (posedge clk or posedge rst)
//if (rst)
// dat_o <= 32'h00000000;
//else
// dat_o <= {dat_o[15:0],dq_i};
dff # ( .width(32)) wb_dat_dff ( .d({dat_o[15:0],dq_i}), .q(dat_o), .clk(clk), .rst(rst));
assign ack_wr = (state==`FSM_RW & count0 & we_i);
always @ (posedge clk or posedge rst)
if (rst)
ack_rd <= {6{1'b0}};
else
ack_rd <= {state==`FSM_RW & count0 & !we_i,ack_rd[2:5]};
assign ack_o = (cl==2) ? ack_rd[5] | ack_wr :
(cl==3) ? ack_rd[6] | ack_wr :
1'b0;
 
// data to WB
always @ (posedge clk or posedge rst)
if (rst)
dat_o <= 32'h00000000;
else
dat_o <= {dat_o[15:0],dq_i};
 
assign ack_o = (state==`FSM_RW & count0);
 
// output dq_o mux and dffs
always @ (posedge clk or posedge rst)
if (rst)
// output dq_o mux and dffs
always @ (posedge clk or posedge rst)
if (rst)
dq_o <= 16'h0000;
else if (~count0)
dq_o <= dat_i[31:16];
else
dq_o <= dat_i[15:0];
if (~count0)
dq_o <= dat_i[31:16];
else
dq_o <= dat_i[15:0];
 
endmodule

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