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/trunk/orp/orp_soc/sw/support/int.h

/trunk/orp/orp_soc/sw/support/support.h

trunk/orp/orp_soc/sw/support/support.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/orp/orp_soc/sw/support/reset.S =================================================================== --- trunk/orp/orp_soc/sw/support/reset.S (nonexistent) +++ trunk/orp/orp_soc/sw/support/reset.S (revision 964) @@ -0,0 +1,194 @@ +/* Support file for c based tests */ +#include "spr_defs.h" +#include "board.h" +#include "mc.h" + + .section .stack + .space 0x1000 +_stack: + + .section .reset + + .org 0x100 +_reset_vector: + l.nop + l.nop + l.addi r2,r0,0x0 + l.addi r3,r0,0x0 + l.addi r4,r0,0x0 + l.addi r5,r0,0x0 + l.addi r6,r0,0x0 + l.addi r7,r0,0x0 + l.addi r8,r0,0x0 + l.addi r9,r0,0x0 + l.addi r10,r0,0x0 + l.addi r11,r0,0x0 + l.addi r12,r0,0x0 + l.addi r13,r0,0x0 + l.addi r14,r0,0x0 + l.addi r15,r0,0x0 + l.addi r16,r0,0x0 + l.addi r17,r0,0x0 + l.addi r18,r0,0x0 + l.addi r19,r0,0x0 + l.addi r20,r0,0x0 + l.addi r21,r0,0x0 + l.addi r22,r0,0x0 + l.addi r23,r0,0x0 + l.addi r24,r0,0x0 + l.addi r25,r0,0x0 + l.addi r26,r0,0x0 + l.addi r27,r0,0x0 + l.addi r28,r0,0x0 + l.addi r29,r0,0x0 + l.addi r30,r0,0x0 + l.addi r31,r0,0x0 + + l.movhi r3,hi(MC_BASE_ADDR) + l.ori r3,r3,MC_BA_MASK + l.addi r5,r0,0x00 + l.sw 0(r3),r5 + l.movhi r3,hi(_start) + l.ori r3,r3,lo(_start) + l.jr r3 + l.nop + + .section .text + +_start: + l.jal _init_mc + l.nop + +.if IC | DC + /* Flush IC and/or DC */ + l.addi r10,r0,0 + l.addi r11,r0,0 + l.addi r12,r0,0 +.if IC + l.addi r11,r0,IC_SIZE +.endif +.if DC + l.addi r12,r0,DC_SIZE +.endif + l.sfleu r12,r11 + l.bf loop + l.nop + l.add r11,r0,r12 +loop: +.if IC + l.mtspr r0,r10,SPR_ICBIR +.endif +.if DC + l.mtspr r0,r10,SPR_DCBIR +.endif + l.sfne r10,r11 + l.bf loop + l.addi r10,r10,16 + + /* Enable IC and/or DC */ + l.addi r10,r0,(SPR_SR_SM) +.if IC + l.ori r10,r10,(SPR_SR_ICE) +.endif +.if DC + l.ori r10,r10,(SPR_SR_DCE) +.endif + l.mtspr r0,r10,SPR_SR + l.nop + l.nop + l.nop + l.nop + l.nop +.endif + + /* Wait for SDRAM */ + l.addi r3,r0,0x1 /* 0x1000 */ +1: l.sfeqi r3,0 + l.bnf 1b + l.addi r3,r3,-1 + + /* Copy from flash to sram */ + l.movhi r3,hi(_src_beg) + l.ori r3,r3,lo(_src_beg) + l.movhi r4,hi(_vec_start) + l.ori r4,r4,lo(_vec_start) + l.movhi r5,hi(_vec_end) + l.ori r5,r5,lo(_vec_end) + l.sub r5,r5,r4 + l.sfeqi r5,0 + l.bf 2f + l.nop +1: l.lwz r6,0(r3) + l.sw 0(r4),r6 + l.addi r3,r3,4 + l.addi r4,r4,4 + l.addi r5,r5,-4 + l.sfgtsi r5,0 + l.bf 1b + l.nop +2: + l.movhi r4,hi(_dst_beg) + l.ori r4,r4,lo(_dst_beg) + l.movhi r5,hi(_dst_end) + l.ori r5,r5,lo(_dst_end) +1: l.sfgeu r4,r5 + l.bf 1f + l.nop + l.lwz r8,0(r3) + l.sw 0(r4),r8 + l.addi r3,r3,4 + l.bnf 1b + l.addi r4,r4,4 +1: + l.addi r3,r0,0 + l.addi r4,r0,0 +3: + /* Set stack pointer */ + l.movhi r1,hi(_stack) + l.ori r1,r1,lo(_stack) + + /* Jump to main */ + l.movhi r2,hi(_reset) + l.ori r2,r2,lo(_reset) + l.jr r2 + l.nop + +_init_mc: + + l.movhi r3,hi(MC_BASE_ADDR) + l.ori r3,r3,lo(MC_BASE_ADDR) + + l.addi r4,r3,MC_CSC(0) + l.movhi r5,hi(FLASH_BASE_ADDR) + l.srai r5,r5,5 + l.ori r5,r5,0x0025 + l.sw 0(r4),r5 + + l.addi r4,r3,MC_TMS(0) + l.movhi r5,hi(FLASH_TMS_VAL) + l.ori r5,r5,lo(FLASH_TMS_VAL) + l.sw 0(r4),r5 + + l.addi r4,r3,MC_BA_MASK + l.addi r5,r0,MC_MASK_VAL + l.sw 0(r4),r5 + + l.addi r4,r3,MC_CSR + l.movhi r5,hi(MC_CSR_VAL) + l.ori r5,r5,lo(MC_CSR_VAL) + l.sw 0(r4),r5 + + l.addi r4,r3,MC_TMS(1) + l.movhi r5,hi(SDRAM_TMS_VAL) + l.ori r5,r5,lo(SDRAM_TMS_VAL) + l.sw 0(r4),r5 + + l.addi r4,r3,MC_CSC(1) + l.movhi r5,hi(SDRAM_BASE_ADDR) + l.srai r5,r5,5 + l.ori r5,r5,0x0411 + l.sw 0(r4),r5 + + l.jr r9 + l.nop +

trunk/orp/orp_soc/sw/support/reset.S Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/orp/orp_soc/sw/support/mc.h =================================================================== --- trunk/orp/orp_soc/sw/support/mc.h (nonexistent) +++ trunk/orp/orp_soc/sw/support/mc.h (revision 964) @@ -0,0 +1,111 @@ +/* mc.h -- Simulation of Memory Controller + Copyright (C) 2001 by Marko Mlinar, markom@opencores.org + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +/* Prototypes */ +#ifndef __MC_H +#define __MC_H + +#define N_CE (8) + +#define MC_CSR (0x00) +#define MC_POC (0x04) +#define MC_BA_MASK (0x08) +#define MC_CSC(i) (0x10 + (i) * 8) +#define MC_TMS(i) (0x14 + (i) * 8) + +#define MC_ADDR_SPACE (MC_CSC(N_CE)) + +/* POC register field definition */ +#define MC_POC_EN_BW_OFFSET 0 +#define MC_POC_EN_BW_WIDTH 2 +#define MC_POC_EN_MEMTYPE_OFFSET 2 +#define MC_POC_EN_MEMTYPE_WIDTH 2 + +/* CSC register field definition */ +#define MC_CSC_EN_OFFSET 0 +#define MC_CSC_MEMTYPE_OFFSET 1 +#define MC_CSC_MEMTYPE_WIDTH 2 +#define MC_CSC_BW_OFFSET 4 +#define MC_CSC_BW_WIDTH 2 +#define MC_CSC_MS_OFFSET 6 +#define MC_CSC_MS_WIDTH 2 +#define MC_CSC_WP_OFFSET 8 +#define MC_CSC_BAS_OFFSET 9 +#define MC_CSC_KRO_OFFSET 10 +#define MC_CSC_PEN_OFFSET 11 +#define MC_CSC_SEL_OFFSET 16 +#define MC_CSC_SEL_WIDTH 8 + +#define MC_CSC_MEMTYPE_SDRAM 0 +#define MC_CSC_MEMTYPE_SSRAM 1 +#define MC_CSC_MEMTYPE_ASYNC 2 +#define MC_CSC_MEMTYPE_SYNC 3 + +#define MC_CSR_VALID 0xFF000703LU +#define MC_POC_VALID 0x0000000FLU +#define MC_BA_MASK_VALID 0x000000FFLU +#define MC_CSC_VALID 0x00FF0FFFLU +#define MC_TMS_SDRAM_VALID 0x0FFF83FFLU +#define MC_TMS_SSRAM_VALID 0x00000000LU +#define MC_TMS_ASYNC_VALID 0x03FFFFFFLU +#define MC_TMS_SYNC_VALID 0x01FFFFFFLU +#define MC_TMS_VALID 0xFFFFFFFFLU /* reg test compat. */ + +/* TMS register field definition SDRAM */ +#define MC_TMS_SDRAM_TRFC_OFFSET 24 +#define MC_TMS_SDRAM_TRFC_WIDTH 4 +#define MC_TMS_SDRAM_TRP_OFFSET 20 +#define MC_TMS_SDRAM_TRP_WIDTH 4 +#define MC_TMS_SDRAM_TRCD_OFFSET 17 +#define MC_TMS_SDRAM_TRCD_WIDTH 4 +#define MC_TMS_SDRAM_TWR_OFFSET 15 +#define MC_TMS_SDRAM_TWR_WIDTH 2 +#define MC_TMS_SDRAM_WBL_OFFSET 9 +#define MC_TMS_SDRAM_OM_OFFSET 7 +#define MC_TMS_SDRAM_OM_WIDTH 2 +#define MC_TMS_SDRAM_CL_OFFSET 4 +#define MC_TMS_SDRAM_CL_WIDTH 3 +#define MC_TMS_SDRAM_BT_OFFSET 3 +#define MC_TMS_SDRAM_BL_OFFSET 0 +#define MC_TMS_SDRAM_BL_WIDTH 3 + +/* TMS register field definition ASYNC */ +#define MC_TMS_ASYNC_TWWD_OFFSET 20 +#define MC_TMS_ASYNC_TWWD_WIDTH 6 +#define MC_TMS_ASYNC_TWD_OFFSET 16 +#define MC_TMS_ASYNC_TWD_WIDTH 4 +#define MC_TMS_ASYNC_TWPW_OFFSET 12 +#define MC_TMS_ASYNC_TWPW_WIDTH 4 +#define MC_TMS_ASYNC_TRDZ_OFFSET 8 +#define MC_TMS_ASYNC_TRDZ_WIDTH 4 +#define MC_TMS_ASYNC_TRDV_OFFSET 0 +#define MC_TMS_ASYNC_TRDV_WIDTH 8 + +/* TMS register field definition SYNC */ +#define MC_TMS_SYNC_TTO_OFFSET 16 +#define MC_TMS_SYNC_TTO_WIDTH 9 +#define MC_TMS_SYNC_TWR_OFFSET 12 +#define MC_TMS_SYNC_TWR_WIDTH 4 +#define MC_TMS_SYNC_TRDZ_OFFSET 8 +#define MC_TMS_SYNC_TRDZ_WIDTH 4 +#define MC_TMS_SYNC_TRDV_OFFSET 0 +#define MC_TMS_SYNC_TRDV_WIDTH 8 + +#endif Index: trunk/orp/orp_soc/sw/support/except.S =================================================================== --- trunk/orp/orp_soc/sw/support/except.S (nonexistent) +++ trunk/orp/orp_soc/sw/support/except.S (revision 964) @@ -0,0 +1,109 @@ +#include "spr_defs.h" + +.section .text + +.org 0x100 + +_reset: + l.nop + l.j _reset_except + l.nop + +.org 0x200 + +_except_200: + l.nop + l.j _buserr_except + l.nop + +.org 0x300 + +_except_300: + l.nop + l.j _dpf_except + l.nop + +.org 0x400 + +_except_400: + l.nop + l.j _ipf_except + l.nop + +.org 0x500 + +_except_500: + l.nop + l.j _lpint_except + l.nop + +.org 0x600 + +_except_600: + l.nop + l.j _align_except + l.nop + +.org 0x700 + +_except_700: + l.nop + l.j _illegal_except + l.nop + +.org 0x800 + +_except_800: + l.nop + l.j _hpint_except + l.nop + +.org 0x900 + +_except_900: + l.nop + l.j _dtlbmiss_except + l.nop + +.org 0xa00 + +_except_a00: + l.nop + l.j _itlbmiss_except + l.nop + +.org 0xb00 + +_except_b00: + l.nop + l.j _range_except + l.nop + +.org 0xc00 + +_except_c00: + l.nop + l.j _syscall_except + l.nop + +.org 0xd00 + +_except_d00: + l.nop + l.j _res1_except + l.nop + +.org 0xe00 + +_except_e00: + l.nop + l.j _trap_except + l.nop + +.org 0xf00 + +_except_f00: + l.nop + l.j _res2_except + l.nop +

trunk/orp/orp_soc/sw/support/except.S Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/orp/orp_soc/sw/support/int.c =================================================================== --- trunk/orp/orp_soc/sw/support/int.c (nonexistent) +++ trunk/orp/orp_soc/sw/support/int.c (revision 964) @@ -0,0 +1,79 @@ +/* This file is part of test microkernel for OpenRISC 1000. */ +/* (C) 2001 Simon Srot, srot@opencores.org */ + +#include "support.h" +#include "spr_defs.h" +#include "int.h" + +#ifdef OR1K + +/* Interrupt handlers table */ +struct ihnd int_handlers[MAX_INT_HANDLERS]; + +/* Initialize routine */ +int int_init() +{ + int i; + + for(i = 0; i < MAX_INT_HANDLERS; i++) { + int_handlers[i].handler = 0; + int_handlers[i].arg = 0; + } + + return 0; +} + +/* Add interrupt handler */ +int int_add(unsigned long vect, void (* handler)(void *), void *arg) +{ + if(vect >= MAX_INT_HANDLERS) + return -1; + + int_handlers[vect].handler = handler; + int_handlers[vect].arg = arg; + + mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect)); + + return 0; +} + +/* Disable interrupt */ +int int_disable(unsigned long vect) +{ + if(vect >= MAX_INT_HANDLERS) + return -1; + + mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << vect)); + + return 0; +} + +/* Enable interrupt */ +int int_enable(unsigned long vect) +{ + if(vect >= MAX_INT_HANDLERS) + return -1; + + mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect)); + + return 0; +} + +/* Main interrupt handler */ +void int_main() +{ + unsigned long picsr = mfspr(SPR_PICSR); + unsigned long i = 0; + + mtspr(SPR_PICSR, 0); + + while(i < 32) { + if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) { + (*int_handlers[i].handler)(int_handlers[i].arg); + mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(0x00000001L << i)); + } + i++; + } +} + +#endif Index: trunk/orp/orp_soc/sw/support/spr_defs.h =================================================================== --- trunk/orp/orp_soc/sw/support/spr_defs.h (nonexistent) +++ trunk/orp/orp_soc/sw/support/spr_defs.h (revision 964) @@ -0,0 +1,449 @@ +/* spr_defs.h -- Defines OR1K architecture specific special-purpose registers + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* This file is also used by microkernel test bench. Among +others it is also used in assembly file(s). */ + +/* Definition of special-purpose registers (SPRs) */ + +#define MAX_GRPS (32) +#define MAX_SPRS_PER_GRP_BITS (11) +#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS) +#define MAX_SPRS (0x10000) + +/* Base addresses for the groups */ +#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_DMMU (1<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_IMMU (2<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_DC (3<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_IC (4<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_MAC (5<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS) + +/* System control and status group */ +#define SPR_VR (SPRGROUP_SYS + 0) +#define SPR_UPR (SPRGROUP_SYS + 1) +#define SPR_CPUCFGR (SPRGROUP_SYS + 2) +#define SPR_DMMUCFGR (SPRGROUP_SYS + 3) +#define SPR_IMMUCFGR (SPRGROUP_SYS + 4) +#define SPR_DCCFGR (SPRGROUP_SYS + 5) +#define SPR_ICCFGR (SPRGROUP_SYS + 6) +#define SPR_DCFGR (SPRGROUP_SYS + 7) +#define SPR_PCCFGR (SPRGROUP_SYS + 8) +#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */ +#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */ +#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */ +#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */ +#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */ +#define SPR_EEAR_BASE (SPRGROUP_SYS + 48) +#define SPR_EEAR_LAST (SPRGROUP_SYS + 63) +#define SPR_ESR_BASE (SPRGROUP_SYS + 64) +#define SPR_ESR_LAST (SPRGROUP_SYS + 79) + +#if 0 +/* Data MMU group */ +#define SPR_DMMUCR (SPRGROUP_DMMU + 0) +#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x200) +#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x200) +#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x300 + (WAY) * 0x200) +#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x3ff + (WAY) * 0x200) + +/* Instruction MMU group */ +#define SPR_IMMUCR (SPRGROUP_IMMU + 0) +#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x200) +#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x200) +#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x300 + (WAY) * 0x200) +#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x3ff + (WAY) * 0x200) +#else +/* Data MMU group */ +#define SPR_DMMUCR (SPRGROUP_DMMU + 0) +#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) +#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) +#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) +#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) + +/* Instruction MMU group */ +#define SPR_IMMUCR (SPRGROUP_IMMU + 0) +#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) +#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100) +#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100) +#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100) +#endif +/* Data cache group */ +#define SPR_DCCR (SPRGROUP_DC + 0) +#define SPR_DCBPR (SPRGROUP_DC + 1) +#define SPR_DCBFR (SPRGROUP_DC + 2) +#define SPR_DCBIR (SPRGROUP_DC + 3) +#define SPR_DCBWR (SPRGROUP_DC + 4) +#define SPR_DCBLR (SPRGROUP_DC + 5) +#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200) +#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200) + +/* Instruction cache group */ +#define SPR_ICCR (SPRGROUP_IC + 0) +#define SPR_ICBPR (SPRGROUP_IC + 1) +#define SPR_ICBIR (SPRGROUP_IC + 2) +#define SPR_ICBLR (SPRGROUP_IC + 3) +#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200) +#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200) + +/* MAC group */ +#define SPR_MACLO (SPRGROUP_MAC + 1) +#define SPR_MACHI (SPRGROUP_MAC + 2) + +/* Debug group */ +#define SPR_DVR(N) (SPRGROUP_D + (N)) +#define SPR_DCR(N) (SPRGROUP_D + 8 + (N)) +#define SPR_DMR1 (SPRGROUP_D + 16) +#define SPR_DMR2 (SPRGROUP_D + 17) +#define SPR_DWCR0 (SPRGROUP_D + 18) +#define SPR_DWCR1 (SPRGROUP_D + 19) +#define SPR_DSR (SPRGROUP_D + 20) +#define SPR_DRR (SPRGROUP_D + 21) + +/* Performance counters group */ +#define SPR_PCCR(N) (SPRGROUP_PC + (N)) +#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N)) + +/* Power management group */ +#define SPR_PMR (SPRGROUP_PM + 0) + +/* PIC group */ +#define SPR_PICMR (SPRGROUP_PIC + 0) +#define SPR_PICPR (SPRGROUP_PIC + 1) +#define SPR_PICSR (SPRGROUP_PIC + 2) + +/* Tick Timer group */ +#define SPR_TTMR (SPRGROUP_TT + 0) +#define SPR_TTCR (SPRGROUP_TT + 1) + +/* + * Bit definitions for the Version Register + * + */ +#define SPR_VR_VER 0xffff0000 /* Processor version */ +#define SPR_VR_REV 0x0000003f /* Processor revision */ + +/* + * Bit definitions for the Unit Present Register + * + */ +#define SPR_UPR_UP 0x00000001 /* UPR present */ +#define SPR_UPR_DCP 0x00000002 /* Data cache present */ +#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */ +#define SPR_UPR_DMP 0x00000008 /* Data MMU present */ +#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */ +#define SPR_UPR_OB32P 0x00000020 /* ORBIS32 present */ +#define SPR_UPR_OB64P 0x00000040 /* ORBIS64 present */ +#define SPR_UPR_OF32P 0x00000080 /* ORFPX32 present */ +#define SPR_UPR_OF64P 0x00000100 /* ORFPX64 present */ +#define SPR_UPR_OV32P 0x00000200 /* ORVDX32 present */ +#define SPR_UPR_OV64P 0x00000400 /* ORVDX64 present */ +#define SPR_UPR_DUP 0x00000800 /* Debug unit present */ +#define SPR_UPR_PCUP 0x00001000 /* Performance counters unit present */ +#define SPR_UPR_PMP 0x00002000 /* Power management present */ +#define SPR_UPR_PICP 0x00004000 /* PIC present */ +#define SPR_UPR_TTP 0x00008000 /* Tick timer present */ +#define SPR_UPR_SRP 0x00010000 /* Shadow registers present */ +#define SPR_UPR_RES 0x00fe0000 /* ORVDX32 present */ +#define SPR_UPR_CUST 0xff000000 /* Custom units */ + +/* + * Bit definitions for the Supervision Register + * + */ +#define SPR_SR_CID 0xf0000000 /* Context ID */ +#define SPR_SR_FO 0x00008000 /* Fixed one */ +#define SPR_SR_EPH 0x00004000 /* Exception Prefixi High */ +#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */ +#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */ +#define SPR_SR_OV 0x00000800 /* Overflow flag */ +#define SPR_SR_CY 0x00000400 /* Carry flag */ +#define SPR_SR_F 0x00000200 /* Condition Flag */ +#define SPR_SR_CE 0x00000100 /* CID Enable */ +#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */ +#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */ +#define SPR_SR_DME 0x00000020 /* Data MMU Enable */ +#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */ +#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */ +#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */ +#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */ +#define SPR_SR_SM 0x00000001 /* Supervisor Mode */ + +/* + * Bit definitions for the Data MMU Control Register + * + */ +#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */ +#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ +#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ +#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ + +/* + * Bit definitions for the Instruction MMU Control Register + * + */ +#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */ +#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ +#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ +#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ + +/* + * Bit definitions for the Data TLB Match Register + * + */ +#define SPR_DTLBMR_V 0x00000001 /* Valid */ +#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ +#define SPR_DTLBMR_CID 0x0000003c /* Context ID */ +#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */ +#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */ + +/* + * Bit definitions for the Data TLB Translate Register + * + */ +#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */ +#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */ +#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */ +#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ +#define SPR_DTLBTR_A 0x00000010 /* Accessed */ +#define SPR_DTLBTR_D 0x00000020 /* Dirty */ +#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */ +#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */ +#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */ +#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */ +#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */ +#define DTLB_PR_NOLIMIT (SPR_DTLBTR_URE | \ + SPR_DTLBTR_UWE | \ + SPR_DTLBTR_SRE | \ + SPR_DTLBTR_SWE ) +/* + * Bit definitions for the Instruction TLB Match Register + * + */ +#define SPR_ITLBMR_V 0x00000001 /* Valid */ +#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ +#define SPR_ITLBMR_CID 0x0000003c /* Context ID */ +#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */ +#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */ + +/* + * Bit definitions for the Instruction TLB Translate Register + * + */ +#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */ +#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */ +#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */ +#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ +#define SPR_ITLBTR_A 0x00000010 /* Accessed */ +#define SPR_ITLBTR_D 0x00000020 /* Dirty */ +#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */ +#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */ +#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */ +#define ITLB_PR_NOLIMIT (SPR_ITLBTR_SXE | \ + SPR_ITLBTR_UXE ) + + +/* + * Bit definitions for Data Cache Control register + * + */ +#define SPR_DCCR_EW 0x000000ff /* Enable ways */ + +/* + * Bit definitions for Insn Cache Control register + * + */ +#define SPR_ICCR_EW 0x000000ff /* Enable ways */ + +/* + * Bit definitions for Debug Control registers + * + */ +#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */ +#define SPR_DCR_CC 0x0000000e /* Compare condition */ +#define SPR_DCR_SC 0x00000010 /* Signed compare */ +#define SPR_DCR_CT 0x000000e0 /* Compare to */ + +/* Bit results with SPR_DCR_CC mask */ +#define SPR_DCR_CC_MASKED 0x00000000 +#define SPR_DCR_CC_EQUAL 0x00000001 +#define SPR_DCR_CC_LESS 0x00000002 +#define SPR_DCR_CC_LESSE 0x00000003 +#define SPR_DCR_CC_GREAT 0x00000004 +#define SPR_DCR_CC_GREATE 0x00000005 +#define SPR_DCR_CC_NEQUAL 0x00000006 + +/* Bit results with SPR_DCR_CT mask */ +#define SPR_DCR_CT_DISABLED 0x00000000 +#define SPR_DCR_CT_IFEA 0x00000020 +#define SPR_DCR_CT_LEA 0x00000040 +#define SPR_DCR_CT_SEA 0x00000060 +#define SPR_DCR_CT_LD 0x00000080 +#define SPR_DCR_CT_SD 0x000000a0 +#define SPR_DCR_CT_LSEA 0x000000c0 + +/* + * Bit definitions for Debug Mode 1 register + * + */ +#define SPR_DMR1_CW0 0x00000003 /* Chain watchpoint 0 */ +#define SPR_DMR1_CW1 0x0000000c /* Chain watchpoint 1 */ +#define SPR_DMR1_CW2 0x00000030 /* Chain watchpoint 2 */ +#define SPR_DMR1_CW3 0x000000c0 /* Chain watchpoint 3 */ +#define SPR_DMR1_CW4 0x00000300 /* Chain watchpoint 4 */ +#define SPR_DMR1_CW5 0x00000c00 /* Chain watchpoint 5 */ +#define SPR_DMR1_CW6 0x00003000 /* Chain watchpoint 6 */ +#define SPR_DMR1_CW7 0x0000c000 /* Chain watchpoint 7 */ +#define SPR_DMR1_CW8 0x00030000 /* Chain watchpoint 8 */ +#define SPR_DMR1_CW9 0x000c0000 /* Chain watchpoint 9 */ +#define SPR_DMR1_CW10 0x00300000 /* Chain watchpoint 10 */ +#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/ +#define SPR_DMR1_BT 0x00800000 /* Branch trace */ +#define SPR_DMR1_DXFW 0x01000000 /* Disable external force watchpoint */ + +/* + * Bit definitions for Debug Mode 2 register + * + */ +#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */ +#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */ +#define SPR_DMR2_AWTC 0x00001ffc /* Assign watchpoints to counters */ +#define SPR_DMR2_WGB 0x00ffe000 /* Watchpoints generating breakpoint */ + +/* + * Bit definitions for Debug watchpoint counter registers + * + */ +#define SPR_DWCR_COUNT 0x0000ffff /* Count */ +#define SPR_DWCR_MATCH 0xffff0000 /* Match */ + +/* + * Bit definitions for Debug stop register + * + */ +#define SPR_DSR_RSTE 0x00000001 /* Reset exception */ +#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */ +#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */ +#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */ +#define SPR_DSR_TTE 0x00000010 /* iTick Timer exception */ +#define SPR_DSR_AE 0x00000020 /* Alignment exception */ +#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */ +#define SPR_DSR_IE 0x00000080 /* Interrupt exception */ +#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */ +#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */ +#define SPR_DSR_RE 0x00000400 /* Range exception */ +#define SPR_DSR_SCE 0x00000800 /* System call exception */ +#define SPR_DSR_SSE 0x00001000 /* Single Step Exception */ +#define SPR_DSR_TE 0x00002000 /* Trap exception */ + +/* + * Bit definitions for Debug reason register + * + */ +#define SPR_DRR_RSTE 0x00000001 /* Reset exception */ +#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */ +#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */ +#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */ +#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */ +#define SPR_DRR_AE 0x00000020 /* Alignment exception */ +#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */ +#define SPR_DRR_IE 0x00000080 /* Interrupt exception */ +#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */ +#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */ +#define SPR_DRR_RE 0x00000400 /* Range exception */ +#define SPR_DRR_SCE 0x00000800 /* System call exception */ +#define SPR_DRR_TE 0x00001000 /* Trap exception */ + +/* + * Bit definitions for Performance counters mode registers + * + */ +#define SPR_PCMR_CP 0x00000001 /* Counter present */ +#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */ +#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */ +#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */ +#define SPR_PCMR_LA 0x00000010 /* Load access event */ +#define SPR_PCMR_SA 0x00000020 /* Store access event */ +#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/ +#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */ +#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */ +#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */ +#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */ +#define SPR_PCMR_BS 0x00000800 /* Branch stall event */ +#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */ +#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */ +#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */ +#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */ + +/* + * Bit definitions for the Power management register + * + */ +#define SPR_PMR_SDF 0x0000000f /* Slow down factor */ +#define SPR_PMR_DME 0x00000010 /* Doze mode enable */ +#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */ +#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */ +#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */ + +/* + * Bit definitions for PICMR + * + */ +#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */ + +/* + * Bit definitions for PICPR + * + */ +#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */ + +/* + * Bit definitions for PICSR + * + */ +#define SPR_PICSR_IS 0xffffffff /* Interrupt status */ + +/* + * Bit definitions for Tick Timer Control Register + * + */ +#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */ +#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD +#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */ +#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */ +#define SPR_TTMR_RT 0x40000000 /* Restart tick */ +#define SPR_TTMR_SR 0x80000000 /* Single run */ +#define SPR_TTMR_CR 0xc0000000 /* Continuous run */ +#define SPR_TTMR_M 0xc0000000 /* Tick mode */ + +/* + * l.nop constants + * + */ +#define NOP_NOP 0x0000 /* Normal nop instruction */ +#define NOP_EXIT 0x0001 /* End of simulation */ +#define NOP_REPORT 0x0002 /* Simple report */ +#define NOP_PRINTF 0x0003 /* Simprintf instruction */ +#define NOP_REPORT_FIRST 0x0400 /* Report with number */ +#define NOP_REPORT_LAST 0x03ff /* Report with number */

trunk/orp/orp_soc/sw/support/spr_defs.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/orp/orp_soc/sw/support/Makefile =================================================================== --- trunk/orp/orp_soc/sw/support/Makefile (nonexistent) +++ trunk/orp/orp_soc/sw/support/Makefile (revision 964) @@ -0,0 +1,29 @@ +all: libsupport.a reset-nocache.o reset-ic.o reset-dc.o reset-icdc.o + +libsupport.a: support.o int.o except.o + or32-rtems-ar cru libsupport.a support.o except.o int.o + or32-rtems-ranlib libsupport.a + +support.o: support.c + or32-rtems-gcc -O2 -c -o $@ $? + +reset-nocache.o: reset.S + or32-rtems-gcc -O2 -c -DIC=0 -DDC=0 -o $@ $? + +reset-dc.o: reset.S + or32-rtems-gcc -O2 -c -DIC=0 -DDC=1 -o $@ $? + +reset-ic.o: reset.S + or32-rtems-gcc -O2 -c -DIC=1 -DDC=0 -o $@ $? + +reset-icdc.o: reset.S + or32-rtems-gcc -O2 -c -DIC=1 -DDC=1 -o $@ $? + +except.o: except.S + or32-rtems-gcc -O2 -c -o $@ $? + +int.o: int.c + or32-rtems-gcc -O2 -c -o $@ $? + +clean: + rm -rf *.o *.a Index: trunk/orp/orp_soc/sw/support/board.h =================================================================== --- trunk/orp/orp_soc/sw/support/board.h (nonexistent) +++ trunk/orp/orp_soc/sw/support/board.h (revision 964) @@ -0,0 +1,92 @@ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifdef XESS +#define MC_ENABLED 0 +#else +#define MC_ENABLED 1 +#endif + +#define IC_ENABLE 0 +#define IC_SIZE 8192 +#define DC_ENABLE 0 +#define DC_SIZE 8192 + +#define MC_CSR_VAL 0x0B000300 +#define MC_MASK_VAL 0x000000e0 +#define FLASH_BASE_ADDR 0x04000000 +#define FLASH_SIZE 0x02000000 +#define FLASH_BLOCK_SIZE 0x20000 +#define FLASH_TMS_VAL 0x00102102 +#define SDRAM_BASE_ADDR 0x00000000 +#define SDRAM_TMS_VAL 0x07248230 + +#ifdef XESS +#define IN_CLK 10000000 +#else +#define IN_CLK 25000000 +#endif + +#define TICKS_PER_SEC 100 + +#define STACK_SIZE 0x10000 + +#ifdef XESS +#define UART_BAUD_RATE 19200 +#else +#define UART_BAUD_RATE 9600 /* 115200 */ +#endif + +#define UART_BASE 0x90000000 +#define UART_IRQ 19 +#ifdef XESS +#define ETH_BASE 0x92000000 +#else +#define ETH_BASE 0xD0000000 +#endif +#define ETH_IRQ 15 +#define MC_BASE_ADDR 0x60000000 +#define SPI_BASE 0xa0000000 + +#ifdef XESS + #define ETH_DATA_BASE 0x00100000 /* Address for ETH_DATA */ +#else + #define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ +#endif + +#define BOARD_DEF_IP 0x0a010185 +#define BOARD_DEF_MASK 0xff000000 +#define BOARD_DEF_GW 0x0a010101 + +#define ETH_MACADDR0 0x00 +#define ETH_MACADDR1 0x12 +#define ETH_MACADDR2 0x34 +#define ETH_MACADDR3 0x56 +#define ETH_MACADDR4 0x78 +#define ETH_MACADDR5 0x9a + +#define CRT_ENABLED 1 +#define CRT_BASE_ADDR 0xc0000000 +#define FB_BASE_ADDR 0xa8000000 + +/* Whether online help is available -- saves space */ +#define HELP_ENABLED 1 + +/* Whether self check is enabled */ +#define SELF_CHECK 1 + +/* Whether we have keyboard suppport */ +#define KBD_ENABLED 1 + +/* Keyboard base address */ +#define KBD_BASE_ADD 0x98000000 + +#define KBD_IRQ 12 + +/* Keyboard buffer size */ +#define KBDBUF_SIZE 256 + +/* Which console is used (CT_NONE, CT_SIM, CT_UART, CT_CRT) */ +#define CONSOLE_TYPE CT_UART + +#endif Index: trunk/orp/orp_soc/sw/support/support.c =================================================================== --- trunk/orp/orp_soc/sw/support/support.c (nonexistent) +++ trunk/orp/orp_soc/sw/support/support.c (revision 964) @@ -0,0 +1,131 @@ +/* Support */ + +#include +#include "spr_defs.h" +#include "support.h" +#include "int.h" + +#if OR1K +void excpt_dummy(); +void int_main(); + +unsigned long excpt_buserr = (unsigned long) excpt_dummy; +unsigned long excpt_dpfault = (unsigned long) excpt_dummy; +unsigned long excpt_ipfault = (unsigned long) excpt_dummy; +unsigned long excpt_tick = (unsigned long) excpt_dummy; +unsigned long excpt_align = (unsigned long) excpt_dummy; +unsigned long excpt_illinsn = (unsigned long) excpt_dummy; +unsigned long excpt_int = (unsigned long) int_main; +unsigned long excpt_dtlbmiss = (unsigned long) excpt_dummy; +unsigned long excpt_itlbmiss = (unsigned long) excpt_dummy; +unsigned long excpt_range = (unsigned long) excpt_dummy; +unsigned long excpt_syscall = (unsigned long) excpt_dummy; +unsigned long excpt_break = (unsigned long) excpt_dummy; +unsigned long excpt_trap = (unsigned long) excpt_dummy; + + +/* Start function, called by reset exception handler. */ +void reset () +{ + int i = main(); + exit (i); +} + +/* return value by making a syscall */ +void exit (int i) +{ + asm("l.add r3,r0,%0": : "r" (i)); + asm("l.nop %0": :"K" (NOP_EXIT)); + while (1); +} + +/* activate printf support in simulator */ +void printf(const char *fmt, ...) +{ + va_list args; + va_start(args, fmt); + __asm__ __volatile__ (" l.addi\tr3,%1,0\n \ + l.addi\tr4,%2,0\n \ + l.nop %0": :"K" (NOP_PRINTF), "r" (fmt), "r" (args)); +} + +/* print long */ +void report(unsigned long value) +{ + asm("l.addi\tr3,%0,0": :"r" (value)); + asm("l.nop %0": :"K" (NOP_REPORT)); +} + +/* just to satisfy linker */ +void __main() +{ +} + +/* start_TIMER */ +void start_timer(int x) +{ +} + +/* read_TIMER */ +/* Returns a value since started in uS */ +unsigned int read_timer(int x) +{ + unsigned long count = 0; + + /* Read the Time Stamp Counter */ +/* asm("simrdtsc %0" :"=r" (count)); */ + /*asm("l.sys 201"); */ + return count; +} + +/* For writing into SPR. */ +void mtspr(unsigned long spr, unsigned long value) +{ + asm("l.mtspr\t\t%0,%1,0": : "r" (spr), "r" (value)); +} + +/* For reading SPR. */ +unsigned long mfspr(unsigned long spr) +{ + unsigned long value; + asm("l.mfspr\t\t%0,%1,0" : "=r" (value) : "r" (spr)); + return value; +} + +#else +void report(unsigned long value) +{ + printf("report(0x%x);\n", (unsigned) value); +} + +/* start_TIMER */ +void start_timer(int tmrnum) +{ +} + +/* read_TIMER */ +/* Returns a value since started in uS */ +unsigned int read_timer(int tmrnum) +{ + struct timeval tv; + struct timezone tz; + + gettimeofday(&tv, &tz); + + return(tv.tv_sec*1000000+tv.tv_usec); +} + +#endif + +void *memcpy (void *__restrict dstvoid, + __const void *__restrict srcvoid, size_t length) +{ + char *dst = dstvoid; + const char *src = (const char *) srcvoid; + + while (length--) + *dst++ = *src++; + return dst; +} + +void excpt_dummy() {}

trunk/orp/orp_soc/sw/support/support.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/orp/orp_soc/sw/support/orp.cfg =================================================================== --- trunk/orp/orp_soc/sw/support/orp.cfg (nonexistent) +++ trunk/orp/orp_soc/sw/support/orp.cfg (revision 964) @@ -0,0 +1,465 @@ +/* sim.cfg -- Simulator configuration script file + Copyright (C) 2001, Marko Mlinar, markom@opencores.org + +This file includes a lot of help about configurations and default one + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* INTRODUCTION + + The or1ksim have various parameters, which can be set in configuration + files. Multiple configurations may be used and switched between at + or1ksim startup. + By default, or1ksim loads condfiguration file from './sim.cfg' and if not + found it checks '~/.or1k/sim.cfg'. If even this file is not found or + all parameters are not defined, default configuration is used. + Users should not rely on default configuration, but rather redefine all + critical settings, since default configuration may differ in newer + versions of the or1ksim. + If multiple configurations are used, user can switch between them by + supplying -f option when starting simulator. + + This file may contain (standard C) only comments - no // support. + + Like normal configuration file, this file is divided in sections, + where each section is described in detail also. + + Some section also have subsections. One example of such subsection is + block: + + device + instance specific parameters... + enddevice + + which creates a device instance. +*/ + + +/* MEMORY SECTION + + This section specifies how is initial memory generated and which blocks + it consist of. + + type = random/unknown/pattern + specifies the initial memory values. 'random' parameter generate + random memory using seed 'random_seed' parameter. 'pattern' parameter + fills memory with 'pattern' parameter and 'unknown' does not specify + how memory should be generated - the fastest option. + + random_seed = + random seed for randomizer, used if type = random + + pattern = + pattern to fill memory, used if type = pattern + + nmemories = + number of memory instances connected + + instance specific: + baseaddr = + memory start address + + size = + memory size + + name = "" + memory block name + + ce = + chip enable index of the memory instance + + delayr = + cycles, required for read access, -1 if instance does not support reading + + delayw = + cycles, required for write access, -1 if instance does not support writing + + 16550 = 0/1 + 0, if this device is uart 16450 and 1, if it is 16550 + + log = "" + filename, where to log memory accesses to, no log, if log command is not specified +*/ + +section memory + /*random_seed = 12345 + type = random*/ + pattern = 0x00 + type = unknown /* Fastest */ + + nmemories = 2 + device 0 + name = "RAM" + ce = 1 + baseaddr = 0x00000000 + size = 0x00200000 + delayr = 1 + delayw = 1 + enddevice + + device 1 + name = "FLASH" + ce = 0 + baseaddr = 0x04000000 + size = 0x00200000 + delayr = 1 + delayw = -1 + enddevice +end + +/* IMMU SECTION + + This section configures Instruction Memory Menangement Unit + + enabled = 0/1 + whether IMMU is enabled + (NOTE: UPR bit is set) + + nsets = + number of ITLB sets; must be power of two + + nways = + number of ITLB ways + + pagesize = + instruction page size; must be power of two + + entrysize = + instruction entry size in bytes + + ustates = + number of ITLB usage states (2, 3, 4 etc., max is 4) +*/ + +section immu + enabled = 1 + nsets = 32 + nways = 1 + pagesize = 8192 +end + +/* DMMU SECTION + + This section configures Data Memory Menangement Unit + + enabled = 0/1 + whether DMMU is enabled + (NOTE: UPR bit is set) + + nsets = + number of DTLB sets; must be power of two + + nways = + number of DTLB ways + + pagesize = + data page size; must be power of two + + entrysize = + data entry size in bytes + + ustates = + number of DTLB usage states (2, 3, 4 etc., max is 4) +*/ + +section dmmu + enabled = 1 + nsets = 32 + nways = 1 + pagesize = 8192 +end + + +/* IC SECTION + + This section configures Instruction Cache + + enabled = 0/1 + whether IC is enabled + (NOTE: UPR bit is set) + + nsets = + number of IC sets; must be power of two + + nways = + number of IC ways + + blocksize = + IC block size in bytes; must be power of two + + ustates = + number of IC usage states (2, 3, 4 etc., max is 4) +*/ + +section ic + enabled = 1 + nsets = 512 + nways = 1 + blocksize = 16 +end + +/* DC SECTION + + This section configures Data Cache + + enabled = 0/1 + whether DC is enabled + (NOTE: UPR bit is set) + + nsets = + number of DC sets; must be power of two + + nways = + number of DC ways + + blocksize = + DC block size in bytes; must be power of two + + ustates = + number of DC usage states (2, 3, 4 etc., max is 4) +*/ + +section dc + enabled = 1 + nsets = 512 + nways = 1 + blocksize = 16 +end + +/* SIM SECTION + + This section specifies how should sim behave. + + verbose = 0/1 + whether to print out extra messages + + debug = 0-9 + = 0 disabled debug messages + 1-9 level of sim debug information, greater the number more verbose is + the output + + profile = 0/1 + whether to generate profiling file 'sim.profile' + + prof_fn = "" + filename, where to generate profiling info, used + only if 'profile' is set + + history = 0/1 + whether instruction execution flow is tracked for + display by simulator hist command. Useful for + back-trace debugging. + + iprompt = 0/1 + whether we strart in interactive prompt + + exe_log = 0/1 + whether execution log should be generated + + exe_log_fn = "" + where to put execution log in, used only if 'exe_log' + is set + + clkcycle = [ps|ns|us|ms] + specifies time measurement for one cycle +*/ + +section sim + /* verbose = 1 */ + debug = 0 + profile = 0 + prof_fn = "sim.profile" + mprofile = 0 + mprof_fn = "sim.mprofile" + + history = 1 + /* iprompt = 0 */ + exe_log = 1 + exe_log_type = hardware + exe_log_fn = "executed.log" + spr_log = 0 + spr_log_fn = "sprs.log" +end + + +/* SECTION VAPI + + This section configures Verification API, used for Advanced + Core Verification. + + enabled = 0/1 + whether to start VAPI server + + server_port = + TCP/IP port to start VAPI server on + + log_enabled = 0/1 + whether logging of VAPI requests is enabled + + vapi_fn = + specifies filename where to log into, if log_enabled is selected +*/ + +section VAPI + enabled = 0 + server_port = 9998 + log_enabled = 0 + vapi_log_fn = "vapi.log" +end + + +/* CPU SECTION + + This section specifies various CPU parameters. + + ver = + rev = + specifies version and revision of the CPU used + + upr = + changes the upr register + + superscalar = 0/1 + whether CPU is scalar or superscalar + (modify cpu/or32/execute.c to tune superscalar model) + + hazards = 0/1 + whether data hazards are tracked in superscalar CPU + and displayed by the simulator r command + + dependstats = 0/1 + whether inter-instruction dependencies are calculated + and displayed by simulator stats command. +*/ + +section cpu + ver = 0x1200 + rev = 0x0001 + /* upr = */ + superscalar = 0 + hazards = 1 + dependstats = 1 +end + +section bpb + enabled = 1 + btic = 1 +end + + +/* DEBUG SECTION + + This sections specifies how debug unit should behave. + + enabled = 0/1 + whether debug unit is enabled + + gdb_enabled = 0/1 + whether to start gdb server at 'server_port' port + + server_port = + TCP/IP port to start gdb server on, used only if gdb_enabled + is set + +section debug + enabled = 0 + gdb_enabled = 0 + server_port = 9999 +end + + +/* MC SECTION + + This section configures the memory controller + + enabled = 0/1 + whether memory controller is enabled + + baseaddr = + address of first MC register + + POC = + Power On Configuration register +*/ + +section mc + enabled = 1 + baseaddr = 0x60000000 + POC = 0x00000008 /* Power on configuration register */ +end + + +/* TICK TIMER SECTION + + This section configures tick timer + + enabled = 0/1 + whether tick timer is enabled + + irq = + irq number +*/ + +section tick + enabled = 1 + irq = 3 +end + +section uart + nuarts = 1 + + device 0 + baseaddr = 0x90000000 + irq = 2 + rxfile = "uart0.rx" + txfile = "uart0.tx" + jitter = -1 /* async behaviour */ + enddevice +end + +/* CUC SECTION + + This section configures the OpenRISC Custom Unit Compiler + + memory_order = none/weak/strong/exact + none different memory ordering, even if there are dependencies, + burst can be made, width can change + weak different memory ordering, if there cannot be dependencies + burst can be made, width can change + strong same memory ordering, burst can be made, width can change + exact exacltly the same memory ordering and widths + + calling_convention = 0/1 + whether programs follow OpenRISC calling conventions + + enable_bursts = 0/1 + whether burst are detected + + no_multicycle = 0/1 + if selected no multicycle logic paths will be generated + + timings_fn = "" +*/ + +section cuc + memory_order = weak + calling_convention = 1 + enable_bursts = 1 + no_multicycle = 1 + timings_fn = "../support/virtex.tim" +end Index: trunk/orp/orp_soc/sw/support/orp.ld =================================================================== --- trunk/orp/orp_soc/sw/support/orp.ld (nonexistent) +++ trunk/orp/orp_soc/sw/support/orp.ld (revision 964) @@ -0,0 +1,56 @@ +MEMORY + { + vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000 + flash : ORIGIN = 0x04000000, LENGTH = 0x00200000 + ram : ORIGIN = 0x00002000, LENGTH = 0x001fe000 + } + +SECTIONS +{ + .reset : + { + *(.reset) + } > flash + + .text ALIGN(0x04): + { + *(.text) + } > flash + + .rodata : + { + *(.rodata) + } > flash + + .dummy ALIGN(0x04): + { + _src_beg = .; + } > flash + + .vectors : + AT ( ADDR (.dummy) ) + { + _vec_start = .; + *(.vectors) + _vec_end = .; + } > vectors + + .data : + AT ( ADDR (.dummy) + SIZEOF (.vectors) ) + { + _dst_beg = .; + *(.data) + _dst_end = .; + } > ram + + .bss : + { + *(.bss) + } > ram + + .stack (NOLOAD) : + { + *(.stack) + _src_addr = .; + } > ram +}

trunk/orp/orp_soc/sw/support/orp.ld Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property