URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
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- This comparison shows the changes necessary to convert path
/
- from Rev 97 to Rev 98
- ↔ Reverse comparison
Rev 97 → Rev 98
/trunk/or1ksim/cpu/or32/execute.c
314,7 → 314,7
memset(reg, 0, sizeof(reg)); |
memset(iqueue, 0, sizeof(iqueue)); |
memset(icomplet, 0, sizeof(icomplet)); |
mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_EXR); |
mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_EXR | SPR_SR_SUPV); |
pcnext = eval_label("_main"); |
pc = pcnext; |
pc_phy = pc; |
383,7 → 383,7
cur->func_unit = store; |
set_operand(cur->op1, (eval_operand(cur->op2) << 16) + (eval_operand(cur->op1) & 0xffff)); |
} else |
if (CURINSN("l.lw")) { |
if (CURINSN("l.lw") || CURINSN("l.lwz")) { |
cur->func_unit = load; |
set_operand(cur->op1, eval_operand(cur->op2)); |
} else |
715,19 → 715,19
(unsigned)eval_operand(cur->op2); |
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_CF | flag); |
} else |
if (CURINSN("l.mtsr")) { |
if (CURINSN("l.mtspr")) { |
cur->func_unit = move; |
if (mfspr(SPR_SR) & SPR_SR_SUPV) |
mtspr(eval_operand(cur->op1), eval_operand(cur->op2)); |
mtspr(eval_operand(cur->op1) + eval_operand(cur->op3), eval_operand(cur->op2)); |
else { |
printf("WARNING: trying to write SPR while SR[SUPV] is cleared.\n"); |
cont_run = 0; |
} |
} else |
if (CURINSN("l.mfsr")) { |
if (CURINSN("l.mfspr")) { |
cur->func_unit = move; |
if (mfspr(SPR_SR) & SPR_SR_SUPV) |
set_operand(cur->op1, mfspr(eval_operand(cur->op2))); |
set_operand(cur->op1, mfspr(eval_operand(cur->op2) + eval_operand(cur->op3))); |
else { |
set_operand(cur->op1, 0); |
printf("WARNING: trying to read SPR while SR[SUPV] is cleared.\n"); |
749,7 → 749,7
unsigned long stackaddr, fmtaddr, args; |
switch (eval_operand(cur->op1)) { |
case 201: |
set_operand("r3", cycles + loadcycles + storecycles); |
set_operand("r9", cycles + loadcycles + storecycles); |
break; |
case 202: |
simprintf(stackaddr, eval_reg("r3")); |
769,7 → 769,7
printf("sys 204: startaddr=%x virtphy=%x\n", startaddr, eval_reg("r5")); |
fflush(stdout); |
endaddr = loadcode(simgetstr(stackaddr, eval_reg("r3")), startaddr, eval_reg("r5")); |
set_reg32("r3", endaddr); |
set_reg32("r9", endaddr); |
/* setsim_mem32(eval_reg("r4"), startaddr); |
setsim_mem32(eval_reg("r5"), endaddr);*/ |
break; |