URL
https://opencores.org/ocsvn/pci/pci/trunk
Subversion Repositories pci
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/trunk/apps/test/bench/verilog/test_bench.v~
File deleted
trunk/apps/test/bench/verilog/test_bench.v~
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/apps/test/rtl/verilog/pci_test_top.v~
===================================================================
--- trunk/apps/test/rtl/verilog/pci_test_top.v~ (revision 97)
+++ trunk/apps/test/rtl/verilog/pci_test_top.v~ (nonexistent)
@@ -1,478 +0,0 @@
-module pci_test_top
-(
- pci_clk_pad_i,
- pci_rst_pad_i,
- clk_pad_i,
-
- pci_req_pad_o,
- pci_gnt_pad_i,
- pci_idsel_pad_i,
-
- pci_ad0_pad_io,
- pci_ad1_pad_io,
- pci_ad2_pad_io,
- pci_ad3_pad_io,
- pci_ad4_pad_io,
- pci_ad5_pad_io,
- pci_ad6_pad_io,
- pci_ad7_pad_io,
- pci_ad8_pad_io,
- pci_ad9_pad_io,
- pci_ad10_pad_io,
- pci_ad11_pad_io,
- pci_ad12_pad_io,
- pci_ad13_pad_io,
- pci_ad14_pad_io,
- pci_ad15_pad_io,
- pci_ad16_pad_io,
- pci_ad17_pad_io,
- pci_ad18_pad_io,
- pci_ad19_pad_io,
- pci_ad20_pad_io,
- pci_ad21_pad_io,
- pci_ad22_pad_io,
- pci_ad23_pad_io,
- pci_ad24_pad_io,
- pci_ad25_pad_io,
- pci_ad26_pad_io,
- pci_ad27_pad_io,
- pci_ad28_pad_io,
- pci_ad29_pad_io,
- pci_ad30_pad_io,
- pci_ad31_pad_io,
-
- pci_cbe0_pad_io,
- pci_cbe1_pad_io,
- pci_cbe2_pad_io,
- pci_cbe3_pad_io,
-
- pci_frame_pad_io,
- pci_irdy_pad_io,
- pci_devsel_pad_io,
- pci_trdy_pad_io,
- pci_stop_pad_io,
- pci_par_pad_io,
- pci_perr_pad_io,
- pci_serr_pad_o
-);
-
-// input/output inout declarations
-input pci_clk_pad_i,
- pci_rst_pad_i,
- clk_pad_i ;
-
-output pci_req_pad_o, pci_serr_pad_o ;
-input pci_gnt_pad_i,
- pci_idsel_pad_i ;
-
-inout pci_frame_pad_io,
- pci_irdy_pad_io,
- pci_devsel_pad_io,
- pci_trdy_pad_io,
- pci_stop_pad_io,
- pci_par_pad_io,
- pci_perr_pad_io,
- pci_ad0_pad_io,
- pci_ad1_pad_io,
- pci_ad2_pad_io,
- pci_ad3_pad_io,
- pci_ad4_pad_io,
- pci_ad5_pad_io,
- pci_ad6_pad_io,
- pci_ad7_pad_io,
- pci_ad8_pad_io,
- pci_ad9_pad_io,
- pci_ad10_pad_io,
- pci_ad11_pad_io,
- pci_ad12_pad_io,
- pci_ad13_pad_io,
- pci_ad14_pad_io,
- pci_ad15_pad_io,
- pci_ad16_pad_io,
- pci_ad17_pad_io,
- pci_ad18_pad_io,
- pci_ad19_pad_io,
- pci_ad20_pad_io,
- pci_ad21_pad_io,
- pci_ad22_pad_io,
- pci_ad23_pad_io,
- pci_ad24_pad_io,
- pci_ad25_pad_io,
- pci_ad26_pad_io,
- pci_ad27_pad_io,
- pci_ad28_pad_io,
- pci_ad29_pad_io,
- pci_ad30_pad_io,
- pci_ad31_pad_io,
- pci_cbe0_pad_io,
- pci_cbe1_pad_io,
- pci_cbe2_pad_io,
- pci_cbe3_pad_io ;
-
-// wires for test master to pci slave connections
-wire wbm_test_wbs_pci_cyc,
- wbm_test_wbs_pci_stb,
- wbm_test_wbs_pci_cab,
- wbm_test_wbs_pci_we,
- wbs_pci_wbm_test_ack ;
-
-wire [31:0] wbm_test_wbs_pci_adr,
- wbm_test_wbs_pci_dat,
- wbs_pci_wbm_test_dat ;
-
-wire [3:0] wbm_test_wbs_pci_sel ;
-
-// wires for test slave to pci master connections
-wire wbm_pci_wbs_test_cyc,
- wbm_pci_wbs_test_stb,
- wbm_pci_wbs_test_cab,
- wbm_pci_wbs_test_we,
- wbs_test_wbm_pci_ack ;
-
-wire [31:0] wbm_pci_wbs_test_adr,
- wbm_pci_wbs_test_dat,
- wbs_test_wbm_pci_dat ;
-
-wire [3:0] wbm_pci_wbs_test_sel ;
-
-wire wb_rst ;
-
-wire wb_clk ;
-wire wb_clk_unbuf ;
-
-wire clk0 ;
-wire clk0_buf ;
-wire clk_i_buf ;
-
-CLKDLL i_clkdll
-(
- .CLKIN ( clk_i_buf ),
- .CLKFB ( clk0_buf ),
- .RST ( 1'b0 ),
- .CLK2X ( ),
- .CLK0 ( clk0 ),
- .CLK90 ( ),
- .CLK180 ( ),
- .CLK270 ( ),
- .CLKDV ( wb_clk_unbuf ),
- .LOCKED ( )
-);
-
-BUFG i_bufg_clk0
-(
- .I( clk0 ),
- .O( clk0_buf )
-) ;
-
-BUFG i_bufg_wb_clk
-(
- .I( wb_clk_unbuf ),
- .O( wb_clk )
-) ;
-
-IBUFG i_ibufg_clk_pad_i
-(
- .I( clk_pad_i ),
- .O( clk_i_buf )
-) ;
-
-// prevent concurent accesses through pci bridge master and slave interfaces
-reg test_wbs_cyc ;
-reg pci_wbs_cyc ;
-
-always@(posedge wb_clk or posedge wb_rst)
-begin
- if (wb_rst)
- begin
- test_wbs_cyc <= 1'b0 ;
- pci_wbs_cyc <= 1'b0 ;
- end
- else
- begin
- if (~pci_wbs_cyc & ~test_wbs_cyc)
- begin
- // currently no cyc signal is asserted - the pci bridge wb master will have the priority here, so check if it has cycle asserted!
- if (wbm_pci_wbs_test_cyc)
- test_wbs_cyc <= 1'b1 ;
- else // no cycle is asserted and pci wb master is not starting the transaction - test wb master can start
- pci_wbs_cyc <= wbm_test_wbs_pci_cyc ;
- end
- else
- begin
- // at least one of the cycles is asserted - wait for transaction to finish
- if (test_wbs_cyc)
- test_wbs_cyc <= wbm_pci_wbs_test_cyc ;
-
- if (pci_wbs_cyc)
- pci_wbs_cyc <= wbm_test_wbs_pci_cyc ;
- end
- end
-end
-
-test i_test
-(
- .clk_i (wb_clk),
- .rst_i (wb_rst),
-
- .wbm_cyc_o (wbm_test_wbs_pci_cyc),
- .wbm_stb_o (wbm_test_wbs_pci_stb),
- .wbm_cab_o (wbm_test_wbs_pci_cab),
- .wbm_we_o (wbm_test_wbs_pci_we),
- .wbm_adr_o (wbm_test_wbs_pci_adr),
- .wbm_sel_o (wbm_test_wbs_pci_sel),
- .wbm_dat_o (wbm_test_wbs_pci_dat),
- .wbm_dat_i (wbs_pci_wbm_test_dat),
- .wbm_ack_i (wbs_pci_wbm_test_ack),
- .wbm_rty_i (1'b0),
- .wbm_err_i (1'b0),
-
- .wbs_cyc_i (wbm_pci_wbs_test_cyc),
- .wbs_stb_i (wbm_pci_wbs_test_stb),
- .wbs_cab_i (wbm_pci_wbs_test_cab),
- .wbs_we_i (wbm_pci_wbs_test_we),
- .wbs_adr_i (wbm_pci_wbs_test_adr),
- .wbs_sel_i (wbm_pci_wbs_test_sel),
- .wbs_dat_i (wbm_pci_wbs_test_dat),
- .wbs_dat_o (wbs_test_wbm_pci_dat),
- .wbs_ack_o (wbs_test_wbm_pci_ack),
- .wbs_rty_o (),
- .wbs_err_o ()
-);
-
-wire pci_req_o,
- pci_req_oe,
- pci_frame_i,
- pci_frame_o,
- pci_frame_oe,
- pci_irdy_oe,
- pci_devsel_oe,
- pci_trdy_oe,
- pci_stop_oe,
- pci_irdy_i,
- pci_irdy_o,
- pci_devsel_i,
- pci_devsel_o,
- pci_trdy_i,
- pci_trdy_o,
- pci_stop_i,
- pci_stop_o,
- pci_par_i,
- pci_par_o,
- pci_par_oe,
- pci_perr_i,
- pci_perr_o,
- pci_perr_oe,
- pci_serr_o,
- pci_serr_oe
-;
-
-wire [31:0] pci_ad_oe,
- pci_ad_i,
- pci_ad_o ;
-
-wire [3:0] pci_cbe_oe,
- pci_cbe_i,
- pci_cbe_o ;
-
-bufif0 ad_buffer00 (pci_ad0_pad_io , pci_ad_o[0] , pci_ad_oe[0] ) ;
-bufif0 ad_buffer01 (pci_ad1_pad_io , pci_ad_o[1] , pci_ad_oe[1] ) ;
-bufif0 ad_buffer02 (pci_ad2_pad_io , pci_ad_o[2] , pci_ad_oe[2] ) ;
-bufif0 ad_buffer03 (pci_ad3_pad_io , pci_ad_o[3] , pci_ad_oe[3] ) ;
-bufif0 ad_buffer04 (pci_ad4_pad_io , pci_ad_o[4] , pci_ad_oe[4] ) ;
-bufif0 ad_buffer05 (pci_ad5_pad_io , pci_ad_o[5] , pci_ad_oe[5] ) ;
-bufif0 ad_buffer06 (pci_ad6_pad_io , pci_ad_o[6] , pci_ad_oe[6] ) ;
-bufif0 ad_buffer07 (pci_ad7_pad_io , pci_ad_o[7] , pci_ad_oe[7] ) ;
-bufif0 ad_buffer08 (pci_ad8_pad_io , pci_ad_o[8] , pci_ad_oe[8] ) ;
-bufif0 ad_buffer09 (pci_ad9_pad_io , pci_ad_o[9] , pci_ad_oe[9] ) ;
-bufif0 ad_buffer10 (pci_ad10_pad_io, pci_ad_o[10], pci_ad_oe[10]) ;
-bufif0 ad_buffer11 (pci_ad11_pad_io, pci_ad_o[11], pci_ad_oe[11]) ;
-bufif0 ad_buffer12 (pci_ad12_pad_io, pci_ad_o[12], pci_ad_oe[12]) ;
-bufif0 ad_buffer13 (pci_ad13_pad_io, pci_ad_o[13], pci_ad_oe[13]) ;
-bufif0 ad_buffer14 (pci_ad14_pad_io, pci_ad_o[14], pci_ad_oe[14]) ;
-bufif0 ad_buffer15 (pci_ad15_pad_io, pci_ad_o[15], pci_ad_oe[15]) ;
-bufif0 ad_buffer16 (pci_ad16_pad_io, pci_ad_o[16], pci_ad_oe[16]) ;
-bufif0 ad_buffer17 (pci_ad17_pad_io, pci_ad_o[17], pci_ad_oe[17]) ;
-bufif0 ad_buffer18 (pci_ad18_pad_io, pci_ad_o[18], pci_ad_oe[18]) ;
-bufif0 ad_buffer19 (pci_ad19_pad_io, pci_ad_o[19], pci_ad_oe[19]) ;
-bufif0 ad_buffer20 (pci_ad20_pad_io, pci_ad_o[20], pci_ad_oe[20]) ;
-bufif0 ad_buffer21 (pci_ad21_pad_io, pci_ad_o[21], pci_ad_oe[21]) ;
-bufif0 ad_buffer22 (pci_ad22_pad_io, pci_ad_o[22], pci_ad_oe[22]) ;
-bufif0 ad_buffer23 (pci_ad23_pad_io, pci_ad_o[23], pci_ad_oe[23]) ;
-bufif0 ad_buffer24 (pci_ad24_pad_io, pci_ad_o[24], pci_ad_oe[24]) ;
-bufif0 ad_buffer25 (pci_ad25_pad_io, pci_ad_o[25], pci_ad_oe[25]) ;
-bufif0 ad_buffer26 (pci_ad26_pad_io, pci_ad_o[26], pci_ad_oe[26]) ;
-bufif0 ad_buffer27 (pci_ad27_pad_io, pci_ad_o[27], pci_ad_oe[27]) ;
-bufif0 ad_buffer28 (pci_ad28_pad_io, pci_ad_o[28], pci_ad_oe[28]) ;
-bufif0 ad_buffer29 (pci_ad29_pad_io, pci_ad_o[29], pci_ad_oe[29]) ;
-bufif0 ad_buffer30 (pci_ad30_pad_io, pci_ad_o[30], pci_ad_oe[30]) ;
-bufif0 ad_buffer31 (pci_ad31_pad_io, pci_ad_o[31], pci_ad_oe[31]) ;
-
-bufif0 cbe_buffer0 (pci_cbe0_pad_io, pci_cbe_o[0], pci_cbe_oe[0]) ;
-bufif0 cbe_buffer1 (pci_cbe1_pad_io, pci_cbe_o[1], pci_cbe_oe[1]) ;
-bufif0 cbe_buffer2 (pci_cbe2_pad_io, pci_cbe_o[2], pci_cbe_oe[2]) ;
-bufif0 cbe_buffer3 (pci_cbe3_pad_io, pci_cbe_o[3], pci_cbe_oe[3]) ;
-
-assign pci_ad_i = {
- pci_ad31_pad_io,
- pci_ad30_pad_io,
- pci_ad29_pad_io,
- pci_ad28_pad_io,
- pci_ad27_pad_io,
- pci_ad26_pad_io,
- pci_ad25_pad_io,
- pci_ad24_pad_io,
- pci_ad23_pad_io,
- pci_ad22_pad_io,
- pci_ad21_pad_io,
- pci_ad20_pad_io,
- pci_ad19_pad_io,
- pci_ad18_pad_io,
- pci_ad17_pad_io,
- pci_ad16_pad_io,
- pci_ad15_pad_io,
- pci_ad14_pad_io,
- pci_ad13_pad_io,
- pci_ad12_pad_io,
- pci_ad11_pad_io,
- pci_ad10_pad_io,
- pci_ad9_pad_io,
- pci_ad8_pad_io,
- pci_ad7_pad_io,
- pci_ad6_pad_io,
- pci_ad5_pad_io,
- pci_ad4_pad_io,
- pci_ad3_pad_io,
- pci_ad2_pad_io,
- pci_ad1_pad_io,
- pci_ad0_pad_io
-} ;
-
-assign pci_cbe_i = {
- pci_cbe3_pad_io,
- pci_cbe2_pad_io,
- pci_cbe1_pad_io,
- pci_cbe0_pad_io
-} ;
-
-bufif0 req_buf (pci_req_pad_o, pci_req_o, pci_req_oe) ;
-
-bufif0 frame_buf (pci_frame_pad_io, pci_frame_o, pci_frame_oe) ;
-assign pci_frame_i = pci_frame_pad_io ;
-
-bufif0 irdy_buf (pci_irdy_pad_io, pci_irdy_o, pci_irdy_oe) ;
-assign pci_irdy_i = pci_irdy_pad_io ;
-
-bufif0 devsel_buf (pci_devsel_pad_io, pci_devsel_o, pci_devsel_oe) ;
-assign pci_devsel_i = pci_devsel_pad_io ;
-
-bufif0 trdy_buf (pci_trdy_pad_io, pci_trdy_o, pci_trdy_oe) ;
-assign pci_trdy_i = pci_trdy_pad_io ;
-
-bufif0 stop_buf (pci_stop_pad_io, pci_stop_o, pci_stop_oe) ;
-assign pci_stop_i = pci_stop_pad_io ;
-
-bufif0 par_buf (pci_par_pad_io, pci_par_o, pci_par_oe) ;
-assign pci_par_i = pci_par_pad_io ;
-
-bufif0 perr_buf (pci_perr_pad_io, pci_perr_o, pci_perr_oe) ;
-assign pci_perr_i = pci_perr_pad_io ;
-
-bufif0 serr_buf (pci_serr_pad_o, pci_serr_o, pci_serr_oe) ;
-
-pci_bridge32 i_pci_bridge32
-(
- // WISHBONE system signals
- .wb_clk_i(wb_clk),
- .wb_rst_i(1'b0),
- .wb_rst_o(wb_rst),
- .wb_int_i(1'b0),
- .wb_int_o(),
-
- // WISHBONE slave interface
- .wbs_adr_i(wbm_test_wbs_pci_adr),
- .wbs_dat_i(wbm_test_wbs_pci_dat),
- .wbs_dat_o(wbs_pci_wbm_test_dat),
- .wbs_sel_i(wbm_test_wbs_pci_sel),
- .wbs_cyc_i(wbm_test_wbs_pci_cyc),
- .wbs_stb_i(wbm_test_wbs_pci_stb),
- .wbs_we_i (wbm_test_wbs_pci_we),
- .wbs_cab_i(wbm_test_wbs_pci_cab),
- .wbs_ack_o(wbs_pci_wbm_test_ack),
- .wbs_rty_o(),
- .wbs_err_o(),
-
- // WISHBONE master interface
- .wbm_adr_o(wbm_pci_wbs_test_adr),
- .wbm_dat_i(wbs_test_wbm_pci_dat),
- .wbm_dat_o(wbm_pci_wbs_test_dat),
- .wbm_sel_o(wbm_pci_wbs_test_sel),
- .wbm_cyc_o(wbm_pci_wbs_test_cyc),
- .wbm_stb_o(wbm_pci_wbs_test_stb),
- .wbm_we_o (wbm_pci_wbs_test_we),
- .wbm_cab_o(wbm_pci_wbs_test_cab),
- .wbm_ack_i(wbs_test_wbm_pci_ack),
- .wbm_rty_i(1'b0),
- .wbm_err_i(1'b0),
-
- // pci interface - system pins
- .pci_clk_i (pci_clk_pad_i),
- .pci_rst_i (pci_rst_pad_i),
- .pci_rst_o (),
- .pci_inta_i (1'b1),
- .pci_inta_o (),
- .pci_rst_oe_o (),
- .pci_inta_oe_o (),
-
- // arbitration pins
- .pci_req_o (pci_req_o),
- .pci_req_oe_o (pci_req_oe),
-
- .pci_gnt_i (pci_gnt_pad_i),
-
- // protocol pins
- .pci_frame_i (pci_frame_i),
- .pci_frame_o (pci_frame_o),
-
- .pci_frame_oe_o (pci_frame_oe),
- .pci_irdy_oe_o (pci_irdy_oe),
- .pci_devsel_oe_o(pci_devsel_oe),
- .pci_trdy_oe_o (pci_trdy_oe),
- .pci_stop_oe_o (pci_stop_oe),
- .pci_ad_oe_o (pci_ad_oe),
- .pci_cbe_oe_o (pci_cbe_oe),
-
- .pci_irdy_i (pci_irdy_i),
- .pci_irdy_o (pci_irdy_o),
-
- .pci_idsel_i (pci_idsel_pad_i),
-
- .pci_devsel_i (pci_devsel_i),
- .pci_devsel_o (pci_devsel_o),
-
- .pci_trdy_i (pci_trdy_i),
- .pci_trdy_o (pci_trdy_o),
-
- .pci_stop_i (pci_stop_i),
- .pci_stop_o (pci_stop_o),
-
- // data transfer pins
- .pci_ad_i (pci_ad_i),
- .pci_ad_o (pci_ad_o),
-
- .pci_cbe_i (pci_cbe_i),
- .pci_cbe_o (pci_cbe_o),
-
- // parity generation and checking pins
- .pci_par_i (pci_par_i),
- .pci_par_o (pci_par_o),
- .pci_par_oe_o (pci_par_oe),
-
- .pci_perr_i (pci_perr_i),
- .pci_perr_o (pci_perr_o),
- .pci_perr_oe_o (pci_perr_oe),
-
- // system error pin
- .pci_serr_o (pci_serr_o),
- .pci_serr_oe_o (pci_serr_oe)
-);
-endmodule // pci_test_top
trunk/apps/test/rtl/verilog/pci_test_top.v~
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/apps/test/rtl/verilog/pci_user_constants.v~
===================================================================
--- trunk/apps/test/rtl/verilog/pci_user_constants.v~ (revision 97)
+++ trunk/apps/test/rtl/verilog/pci_user_constants.v~ (nonexistent)
@@ -1,238 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// File name "pci_user_constants.v" ////
-//// ////
-//// This file is part of the "PCI bridge" project ////
-//// http://www.opencores.org/cores/pci/ ////
-//// ////
-//// Author(s): ////
-//// - Miha Dolenc (mihad@opencores.org) ////
-//// - Tadej Markovic (tadej@opencores.org) ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.8 2003/03/14 15:31:57 mihad
-// Entered the option to disable no response counter in wb master.
-//
-// Revision 1.7 2003/01/27 17:05:50 mihad
-// Updated.
-//
-// Revision 1.6 2003/01/27 16:51:19 mihad
-// Old files with wrong names removed.
-//
-// Revision 1.5 2003/01/21 16:06:56 mihad
-// Bug fixes, testcases added.
-//
-// Revision 1.4 2002/09/30 17:22:45 mihad
-// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
-//
-// Revision 1.3 2002/08/13 11:03:53 mihad
-// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
-//
-// Revision 1.2 2002/03/05 11:53:47 mihad
-// Added some testcases, removed un-needed fifo signals
-//
-// Revision 1.1 2002/02/01 14:43:31 mihad
-// *** empty log message ***
-//
-//
-
-// Fifo implementation defines:
-// If FPGA and XILINX are defined, Xilinx's BlockSelectRAM+ is instantiated for Fifo storage.
-// 16 bit width is used, so 8 bits of address ( 256 ) locations are available. If RAM_DONT_SHARE is not defined (commented out),
-// then one block RAM is shared between two FIFOs. That means each Fifo can have a maximum address length of 7 - depth of 128 and only 6 block rams are used
-// If RAM_DONT_SHARE is defined ( not commented out ), then 12 block RAMs are used and each Fifo can have a maximum address length of 8 ( 256 locations )
-// If FPGA is not defined, then ASIC RAMs are used. Currently there is only one version of ARTISAN RAM supported. User should generate synchronous RAM with
-// width of 40 and instantiate it in pci_tpram.v. If RAM_DONT_SHARE is defined, then these can be dual port rams ( write port
-// in one clock domain, read in other ), otherwise it must be two port RAM ( read and write ports in both clock domains ).
-// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
-// WB_FIFO_RAM_ADDR_LENGTH.
-
-`define WBW_ADDR_LENGTH 4
-`define WBR_ADDR_LENGTH 4
-`define PCIW_ADDR_LENGTH 4
-`define PCIR_ADDR_LENGTH 4
-
-`define FPGA
-`define XILINX
-
-`define WB_RAM_DONT_SHARE
-//`define PCI_RAM_DONT_SHARE
-
-`ifdef FPGA
- `ifdef XILINX
- `define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition
- `define WB_FIFO_RAM_ADDR_LENGTH 4 // WB slave unit fifo storage definition
- `define PCI_XILINX_RAMB4
- //`define WB_XILINX_RAMB4
- //`define PCI_XILINX_DIST_RAM
- `define WB_XILINX_DIST_RAM
- `endif
-`else
- `define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
- `define WB_FIFO_RAM_ADDR_LENGTH 7 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
-// `define WB_ARTISAN_SDP
-// `define PCI_ARTISAN_SDP
-// `define PCI_VS_STP
-// `define WB_VS_STP
-`endif
-
-// these two defines allow user to select active high or low output enables on PCI bus signals, depending on
-// output buffers instantiated. Xilinx FPGAs use active low output enables.
-`define ACTIVE_LOW_OE
-//`define ACTIVE_HIGH_OE
-
-// HOST/GUEST implementation selection - see design document and specification for description of each implementation
-// only one can be defined at same time
-//`define HOST
-`define GUEST
-
-// if NO_CNF_IMAGE is commented out, then READ-ONLY access to configuration space is ENABLED:
-// - ENABLED Read-Only access from WISHBONE for GUEST bridges
-// - ENABLED Read-Only access from PCI for HOST bridges
-// with defining NO_CNF_IMAGE, one decoder and one multiplexer are saved
-`define NO_CNF_IMAGE
-
-// number defined here specifies how many MS bits in PCI address are compared with base address, to decode
-// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
-// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,
-// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
-// smaller the number here, faster the decoder operation
-`define PCI_NUM_OF_DEC_ADDR_LINES 12
-
-// no. of PCI Target IMAGES
-// - PCI provides 6 base address registers for image implementation.
-// PCI_IMAGE1 definition is not required and has no effect, since PCI image 1 is always implemented
-// If GUEST is defined, PCI Image 0 is also always implemented and is used for configuration space
-// access.
-// If HOST is defined and NO_CNF_IMAGE is not, then PCI Image 0 is used for Read Only access to configuration
-// space. If HOST is defined and NO_CNF_IMAGE is defined, then user can define PCI_IMAGE0 as normal image, and there
-// is no access to Configuration space possible from PCI bus.
-// Implementation of all other PCI images is selected by defining PCI_IMAGE2 through PCI_IMAGE5 regardles of HOST
-// or GUEST implementation.
-`ifdef HOST
- `ifdef NO_CNF_IMAGE
- `define PCI_IMAGE0
- `endif
-`endif
-
-`define PCI_IMAGE2
-//`define PCI_IMAGE3
-//`define PCI_IMAGE4
-//`define PCI_IMAGE5
-
-// initial value for PCI image address masks. Address masks can be defined in enabled state,
-// to allow device independent software to detect size of image and map base addresses to
-// memory space. If initial mask for an image is defined as 0, then device independent software
-// won't detect base address implemented and device dependent software will have to configure
-// address masks as well as base addresses!
-`define PCI_AM0 20'hffff_f
-`define PCI_AM1 20'hffff_f
-`define PCI_AM2 20'hffff_8
-`define PCI_AM3 20'hffff_0
-`define PCI_AM4 20'hfffe_0
-`define PCI_AM5 20'h0000_0
-
-// initial value for PCI image maping to MEMORY or IO spaces. If initial define is set to 0,
-// then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. D
-// Device independent software sets the base addresses acording to MEMORY or IO maping!
-`define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
-`define PCI_BA1_MEM_IO 1'b0
-`define PCI_BA2_MEM_IO 1'b0
-`define PCI_BA3_MEM_IO 1'b1
-`define PCI_BA4_MEM_IO 1'b0
-`define PCI_BA5_MEM_IO 1'b1
-
-// number defined here specifies how many MS bits in WB address are compared with base address, to decode
-// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
-// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
-// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
-// smaller the number here, faster the decoder operation
-`define WB_NUM_OF_DEC_ADDR_LINES 1
-
-// no. of WISHBONE Slave IMAGES
-// WB image 0 is always used for access to configuration space. In case configuration space access is not implemented,
-// ( both GUEST and NO_CNF_IMAGE defined ), then WB image 0 is not implemented. User doesn't need to define image 0.
-// WB Image 1 is always implemented and user doesnt need to specify its definition
-// WB images' 2 through 5 implementation by defining each one.
-`define WB_IMAGE2
-//`define WB_IMAGE3
-//`define WB_IMAGE4
-//`define WB_IMAGE5
-
-// If this define is commented out, then address translation will not be implemented.
-// addresses will pass through bridge unchanged, regardles of address translation enable bits.
-// Address translation also slows down the decoding
-`define ADDR_TRAN_IMPL
-
-// decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
-// slower decode speed can be used, to provide enough time for address to be decoded.
-`define WB_DECODE_FAST
-//`define WB_DECODE_MEDIUM
-//`define WB_DECODE_SLOW
-
-// Base address for Configuration space access from WB bus. This value cannot be changed during runtime
-`define WB_CONFIGURATION_BASE 20'hF300_0
-
-// Turn registered WISHBONE slave outputs on or off
-// all outputs from WB Slave state machine are registered, if this is defined - WB bus outputs as well as
-// outputs to internals of the core.
-//`define REGISTER_WBS_OUTPUTS
-
-/*-----------------------------------------------------------------------------------------------------------
-Core speed definition - used for simulation and 66MHz Capable bit value in status register indicating 66MHz
-capable device
------------------------------------------------------------------------------------------------------------*/
-`define PCI33
-//`define PCI66
-
-/*-----------------------------------------------------------------------------------------------------------
-[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !
- Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g.
- Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
- together by application.
------------------------------------------------------------------------------------------------------------*/
-`define HEADER_VENDOR_ID 16'h1895
-`define HEADER_DEVICE_ID 16'h0001
-`define HEADER_REVISION_ID 8'h01
-
-// Turn registered WISHBONE master outputs on or off
-// all outputs from WB Master state machine are registered, if this is defined - WB bus outputs as well as
-// outputs to internals of the core.
-`define REGISTER_WBM_OUTPUTS
-
-// MAX Retry counter value for WISHBONE Master state-machine
-// This value is 8-bit because of 8-bit retry counter !!!
-`define WB_RTY_CNT_MAX 8'hff
-
-// define the macro below to disable internal retry generation in the wishbone master interface
-// used when wb master accesses extremly slow devices.
-//`define PCI_WBM_NO_RESPONSE_CNT_DISABLE
trunk/apps/test/rtl/verilog/pci_user_constants.v~
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/apps/test/rtl/verilog/test.v~
===================================================================
--- trunk/apps/test/rtl/verilog/test.v~ (revision 97)
+++ trunk/apps/test/rtl/verilog/test.v~ (nonexistent)
@@ -1,751 +0,0 @@
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-
-module test
-(
- pci_clk_i,
- clk_i,
- rst_i,
-
- wbm_cyc_o,
- wbm_stb_o,
- wbm_cab_o,
- wbm_we_o,
- wbm_adr_o,
- wbm_sel_o,
- wbm_dat_o,
- wbm_dat_i,
- wbm_ack_i,
- wbm_rty_i,
- wbm_err_i,
-
- wbs_cyc_i,
- wbs_stb_i,
- wbs_cab_i,
- wbs_we_i,
- wbs_adr_i,
- wbs_sel_i,
- wbs_dat_i,
- wbs_dat_o,
- wbs_ack_o,
- wbs_rty_o,
- wbs_err_o,
-
- // pci trdy, irdy and irdy enable inputs used to count number of transfers on pci bus
- pci_irdy_reg_i,
- pci_irdy_en_reg_i,
- pci_trdy_reg_i,
- pci_ad_reg_i
-);
-
-input pci_clk_i,
- clk_i,
- rst_i ;
-
-output wbm_cyc_o,
- wbm_stb_o,
- wbm_cab_o,
- wbm_we_o ;
-
-output [31:0] wbm_adr_o ;
-output [3:0] wbm_sel_o ;
-assign wbm_sel_o = 4'hF ;
-output [31:0] wbm_dat_o ;
-input [31:0] wbm_dat_i ;
-input wbm_ack_i,
- wbm_rty_i,
- wbm_err_i ;
-
-input wbs_cyc_i,
- wbs_stb_i,
- wbs_cab_i,
- wbs_we_i ;
-
-input [31:0] wbs_adr_i ;
-input [3:0] wbs_sel_i ;
-input [31:0] wbs_dat_i ;
-output [31:0] wbs_dat_o ;
-output wbs_ack_o,
- wbs_rty_o,
- wbs_err_o ;
-
-input pci_irdy_reg_i,
- pci_irdy_en_reg_i,
- pci_trdy_reg_i ;
-
-input [31:0] pci_ad_reg_i ;
-
-wire sel_registers = wbs_adr_i[12] ;
-wire sel_rams = ~wbs_adr_i[12] ;
-
-wire wbs_write = wbs_cyc_i & wbs_stb_i & wbs_we_i ;
-
-wire wbs_ram0_255_we = wbs_write & sel_rams & (wbs_adr_i[11:10] == 2'b00) ;
-wire wbs_ram256_511_we = wbs_write & sel_rams & (wbs_adr_i[11:10] == 2'b01) ;
-wire wbs_ram512_767_we = wbs_write & sel_rams & (wbs_adr_i[11:10] == 3'b10) ;
-wire wbs_ram768_1023_we = wbs_write & sel_rams & (wbs_adr_i[11:10] == 3'b11) ;
-
-reg sel_master_transaction_size,
- sel_master_transaction_count,
- sel_master_opcode,
- sel_master_base,
- sel_target_burst_transaction_count,
- sel_target_test_size,
- sel_target_test_start_adr,
- sel_target_test_start_dat,
- sel_target_test_error_detected,
- sel_master_num_of_wb_transfers,
- sel_master_num_of_pci_transfers,
- sel_master_test_start_dat,
- sel_master_test_size,
- sel_master_dat_err_detected ;
-
-wire [31:0] wbs_ram0_255_o ;
-wire [31:0] wbs_ram256_511_o ;
-wire [31:0] wbs_ram512_767_o ;
-wire [31:0] wbs_ram768_1023_o ;
-
-wire wbm_write = wbm_cyc_o & wbm_stb_o & wbm_we_o ;
-wire wbm_read = wbm_cyc_o & wbm_stb_o & ~wbm_we_o ;
-
-wire wbm_ram0_255_we = wbm_ack_i & wbm_read & (wbm_adr_o[11:10] == 2'b00) ;
-wire wbm_ram256_511_we = wbm_ack_i & wbm_read & (wbm_adr_o[11:10] == 2'b01) ;
-wire wbm_ram512_767_we = wbm_ack_i & wbm_read & (wbm_adr_o[11:10] == 2'b10) ;
-wire wbm_ram768_1023_we = wbm_ack_i & wbm_read & (wbm_adr_o[11:10] == 2'b11) ;
-
-wire [31:0] wbm_ram0_255_o ;
-wire [31:0] wbm_ram256_511_o ;
-wire [31:0] wbm_ram512_767_o ;
-wire [31:0] wbm_ram768_1023_o ;
-
-reg [31:0] wbm_dat_o ;
-
-always@(wbm_adr_o or wbm_ram0_255_o or wbm_ram256_511_o or wbm_ram512_767_o or wbm_ram768_1023_o)
-begin
- case (wbm_adr_o[11:10])
- 2'b00:
- begin
- wbm_dat_o = wbm_ram0_255_o ;
- end
- 2'b01:
- begin
- wbm_dat_o = wbm_ram256_511_o ;
- end
- 2'b10:
- begin
- wbm_dat_o = wbm_ram512_767_o ;
- end
- 2'b11:
- begin
- wbm_dat_o = wbm_ram768_1023_o ;
- end
- endcase
-end
-
-reg [10:0] master_transaction_size ;
-reg [10:0] master_transaction_count ;
-reg master_opcode ;
-reg [31:0] master_base ;
-reg [31:0] master_base_next ;
-reg [10:0] target_test_size ;
-reg [31:0] target_test_start_adr ;
-reg [31:0] target_test_expect_adr ;
-reg [31:0] target_test_start_dat ;
-reg [31:0] target_test_expect_dat ;
-reg target_test_adr_error_detected,
- target_test_dat_error_detected ;
-reg [31:0] master_num_of_wb_transfers,
- master_num_of_pci_transfers ;
-reg [31:0] master_test_start_dat ;
-reg [31:0] pci_clk_master_test_expect_dat ;
-reg [20:0] master_test_size ;
-reg [20:0] pci_clk_master_test_size ;
-reg pci_clk_master_test_done,
- wb_clk_master_test_done_sync,
- wb_clk_master_test_done,
- wb_clk_master_test_start,
- pci_clk_master_test_start_sync,
- pci_clk_master_test_start,
- pci_clk_master_test_started,
- wb_clk_master_test_started_sync,
- wb_clk_master_test_started,
- master_dat_err_detected ;
-
-always@(posedge pci_clk_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- pci_clk_master_test_expect_dat <= 0 ;
- pci_clk_master_test_size <= 0 ;
- pci_clk_master_test_done <= 1 ;
- pci_clk_master_test_start_sync <= 0 ;
- pci_clk_master_test_start <= 0 ;
- pci_clk_master_test_started <= 0 ;
- master_dat_err_detected <= 0 ;
- end
- else
- begin
- // sync flop always samples the data
- pci_clk_master_test_start_sync <= wb_clk_master_test_start ;
- if (pci_clk_master_test_size == 0)
- begin
- // load test start_flop only when test size is zero
- pci_clk_master_test_start <= pci_clk_master_test_start_sync ;
- pci_clk_master_test_started <= 0 ;
- pci_clk_master_test_done <= 1 ;
- if (pci_clk_master_test_start)
- begin
- pci_clk_master_test_size <= master_test_size ;
- pci_clk_master_test_expect_dat <= master_test_start_dat ;
-
- // error detected bit is cleared when new test starts
- master_dat_err_detected <= 0 ;
- end
- end
- else
- begin
- pci_clk_master_test_done <= 0 ;
- pci_clk_master_test_start <= 0 ;
- pci_clk_master_test_started <= 1 ;
- if (~(pci_irdy_reg_i | ~pci_irdy_en_reg_i | pci_trdy_reg_i))
- begin
- pci_clk_master_test_size <= pci_clk_master_test_size - 1'b1 ;
-
- if (pci_ad_reg_i != pci_clk_master_test_expect_dat)
- master_dat_err_detected <= 1'b1 ;
-
- pci_clk_master_test_expect_dat <= {pci_clk_master_test_expect_dat[30:0], pci_clk_master_test_expect_dat[31]} ;
- end
- end
- end
-end
-
-always@(posedge clk_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- wb_clk_master_test_done_sync <= 1'b1 ;
- wb_clk_master_test_done <= 1'b1 ;
- wb_clk_master_test_started_sync <= 1'b0 ;
- wb_clk_master_test_started <= 1'b0 ;
- end
- else
- begin
- wb_clk_master_test_done_sync <= pci_clk_master_test_done ;
- if (wb_clk_master_test_start)
- wb_clk_master_test_done <= 1'b0 ;
- else
- wb_clk_master_test_done <= wb_clk_master_test_done_sync ;
-
- wb_clk_master_test_started_sync <= pci_clk_master_test_started ;
- wb_clk_master_test_started <= wb_clk_master_test_started_sync ;
- end
-end
-
-assign wbm_we_o = master_opcode ;
-
-reg [10:0] master_current_transaction_size ;
-
-reg [10:0] target_burst_transaction_count ;
-reg wbs_cyc_i_previous ;
-
-reg clr_master_num_of_pci_transfers ;
-reg clr_master_num_of_pci_transfers_sync ;
-reg wb_clk_clr_master_num_of_pci_transfers ;
-
-always@(posedge pci_clk_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- master_num_of_pci_transfers <= 0 ;
- end
- else if (clr_master_num_of_pci_transfers)
- begin
- master_num_of_pci_transfers <= 0 ;
- end
- else if (~(pci_irdy_reg_i | ~pci_irdy_en_reg_i | pci_trdy_reg_i))
- begin
- master_num_of_pci_transfers <= master_num_of_pci_transfers + 1'b1 ;
- end
-
- if (rst_i)
- begin
- clr_master_num_of_pci_transfers <= 1'b1 ;
- clr_master_num_of_pci_transfers_sync <= 1'b1 ;
- end
- else
- begin
- clr_master_num_of_pci_transfers <= clr_master_num_of_pci_transfers_sync ;
- clr_master_num_of_pci_transfers_sync <= wb_clk_clr_master_num_of_pci_transfers ;
- end
-end
-
-always@(posedge clk_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- master_transaction_size <= 0 ;
- master_transaction_count <= 0 ;
- master_opcode <= 0 ;
- master_base <= 0 ;
- master_base_next <= 4 ;
- target_burst_transaction_count <= 0 ;
- wbs_cyc_i_previous <= 0 ;
- target_test_size <= 0 ;
- target_test_start_adr <= 0 ;
- target_test_start_dat <= 0 ;
- target_test_adr_error_detected <= 0 ;
- target_test_dat_error_detected <= 0 ;
- target_test_expect_adr <= 0 ;
- target_test_expect_dat <= 0 ;
- master_num_of_wb_transfers <= 0 ;
- wb_clk_clr_master_num_of_pci_transfers <= 1'b1 ;
- master_test_size <= 0 ;
- master_test_start_dat <= 0 ;
- wb_clk_master_test_start <= 0 ;
- end
- else
- begin
- if (sel_master_transaction_size & wbs_write & sel_registers)
- // write new value to transaction size register
- master_transaction_size <= wbs_dat_i[10:0] ;
-
- if (sel_master_transaction_count & wbs_write & sel_registers)
- // write new value to transaction count register
- master_transaction_count <= wbs_dat_i[10:0] ;
- else if (wbm_cyc_o & wbm_stb_o & wbm_ack_i & (master_current_transaction_size == 11'h1))
- // decrement the transaction count when ack is received and transaction size is 1
- master_transaction_count <= master_transaction_count - 1'b1 ;
-
- if (sel_master_opcode & wbs_write & sel_registers)
- // master opcode write
- master_opcode <= wbs_dat_i[0] ;
-
- if (sel_master_base & wbs_write & sel_registers)
- // master base address write
- master_base <= {wbs_dat_i[31:2], 2'b00} ;
-
- if (sel_target_burst_transaction_count & wbs_write & sel_registers)
- target_burst_transaction_count <= 0 ;
- else if (wbs_cyc_i & ~wbs_cyc_i_previous & wbs_cab_i)
- target_burst_transaction_count <= target_burst_transaction_count + 1 ;
-
- if (sel_target_test_size & wbs_write & sel_registers)
- target_test_size <= wbs_dat_i[10:0] ;
- else if ((target_test_size != 0) & wbs_cyc_i & wbs_stb_i & wbs_we_i & wbs_ack_o & ~sel_registers)
- begin
- target_test_size <= target_test_size - 1'b1 ;
- end
-
- if (sel_target_test_start_adr & wbs_write & sel_registers)
- target_test_start_adr <= wbs_dat_i ;
-
- if (sel_target_test_start_dat & wbs_write & sel_registers)
- target_test_start_dat <= wbs_dat_i ;
-
- if (sel_target_test_error_detected & wbs_write & sel_registers)
- begin
- target_test_adr_error_detected <= 1'b0 ;
- target_test_dat_error_detected <= 1'b0 ;
- end
- else if ((target_test_size != 0) & wbs_cyc_i & wbs_stb_i & wbs_we_i & wbs_ack_o & ~sel_registers)
- begin
- target_test_adr_error_detected <= (target_test_expect_adr != wbs_adr_i) | target_test_adr_error_detected ;
- target_test_dat_error_detected <= (target_test_expect_dat != wbs_dat_i) | target_test_dat_error_detected ;
- end
-
- if (target_test_size == 0)
- begin
- target_test_expect_adr <= target_test_start_adr ;
- target_test_expect_dat <= target_test_start_dat ;
- end
- else if (wbs_cyc_i & wbs_stb_i & wbs_we_i & wbs_ack_o & ~sel_registers)
- begin
- target_test_expect_adr <= target_test_expect_adr + 'd4 ;
- target_test_expect_dat <= {target_test_expect_dat[30:0], target_test_expect_dat[31]} ;
- end
-
- if (sel_master_num_of_wb_transfers & wbs_write & sel_registers)
- begin
- master_num_of_wb_transfers <= 0 ;
- wb_clk_clr_master_num_of_pci_transfers <= 1'b1 ;
- end
- else if (wbm_cyc_o & wbm_stb_o & wbm_ack_i)
- begin
- wb_clk_clr_master_num_of_pci_transfers <= 1'b0 ;
- master_num_of_wb_transfers <= master_num_of_wb_transfers + 1'b1 ;
- end
-
- if (wb_clk_master_test_done & wbs_write & sel_master_test_size & sel_registers & ~wb_clk_master_test_start)
- begin
- master_test_size <= wbs_dat_i[20:0] ;
- wb_clk_master_test_start <= 1'b1 ;
- end
- else
- begin
- if (wb_clk_master_test_started & !wb_clk_master_test_done)
- wb_clk_master_test_start <= 1'b0 ;
- end
-
- if (sel_master_test_start_dat & wbs_write & sel_registers)
- master_test_start_dat <= wbs_dat_i ;
-
- master_base_next <= master_base + 4 ;
-
- wbs_cyc_i_previous <= wbs_cyc_i ;
- end
-end
-
-reg [31:0] register_output ;
-reg [31:0] ram_output ;
-
-always@
-(
- wbs_adr_i or
- master_transaction_size or
- master_transaction_count or
- master_opcode or
- master_base or
- target_burst_transaction_count or
- target_test_size or
- target_test_start_adr or
- target_test_start_dat or
- target_test_adr_error_detected or
- target_test_dat_error_detected or
- master_num_of_wb_transfers or
- master_num_of_pci_transfers or
- master_test_size or
- master_test_start_dat or
- master_dat_err_detected
-)
-begin
- sel_master_transaction_size = 1'b0 ;
- sel_master_transaction_count = 1'b0 ;
- sel_master_opcode = 1'b0 ;
- sel_master_base = 1'b0 ;
- sel_target_burst_transaction_count = 1'b0 ;
- sel_target_test_size = 1'b0 ;
- sel_target_test_start_adr = 1'b0 ;
- sel_target_test_start_dat = 1'b0 ;
- sel_target_test_error_detected = 1'b0 ;
- sel_master_num_of_wb_transfers = 1'b0 ;
- sel_master_test_size = 1'b0 ;
- sel_master_dat_err_detected = 1'b0 ;
- register_output = 0 ;
-
- case (wbs_adr_i[5:2])
- 4'b0000:
- begin
- sel_master_transaction_size = 1'b1 ;
- register_output = {21'h0, master_transaction_size} ;
- end
- 4'b0001:
- begin
- sel_master_transaction_count = 1'b1 ;
- register_output = {21'h0, master_transaction_count} ;
- end
- 4'b0010:
- begin
- sel_master_opcode = 1'b1 ;
- register_output = {31'h0, master_opcode} ;
- end
- 4'b0011:
- begin
- sel_master_base = 1'b1 ;
- register_output = master_base ;
- end
- 4'b0100:
- begin
- sel_target_burst_transaction_count = 1'b1 ;
- register_output = target_burst_transaction_count ;
- end
- 4'b0101:
- begin
- sel_target_test_size = 1'b1 ;
- register_output = {20'h0, target_test_size} ;
- end
- 4'b0110:
- begin
- sel_target_test_start_adr = 1'b1 ;
- register_output = target_test_start_adr ;
- end
- 4'b0111:
- begin
- sel_target_test_start_dat = 1'b1 ;
- register_output = target_test_start_dat ;
- end
- 4'b1000:
- begin
- sel_target_test_error_detected = 1'b1 ;
- register_output = {30'h0, target_test_adr_error_detected, target_test_dat_error_detected} ;
- end
- 4'b1001:
- begin
- sel_master_num_of_wb_transfers = 1'b1 ;
- register_output = master_num_of_wb_transfers ;
- end
- 4'b1010:
- begin
- sel_master_num_of_pci_transfers = 1'b1 ;
- register_output = master_num_of_pci_transfers ;
- end
- 4'b1011:
- begin
- sel_master_test_size = 1'b1 ;
- register_output = {11'h0, master_test_size} ;
- end
- 4'b1100:
- begin
- sel_master_test_start_dat = 1'b1 ;
- register_output = master_test_start_dat ;
- end
- 4'b1101:
- begin
- sel_master_dat_err_detected = 1'b1 ;
- register_output = {31'h0, master_dat_err_detected} ;
- end
- endcase
-end
-
-always@(wbs_adr_i or wbs_ram0_255_o or wbs_ram256_511_o or wbs_ram512_767_o or wbs_ram768_1023_o)
-begin
- case (wbs_adr_i[11:10])
- 2'b00:ram_output = wbs_ram0_255_o ;
- 2'b01:ram_output = wbs_ram256_511_o ;
- 2'b10:ram_output = wbs_ram512_767_o ;
- 2'b11:ram_output = wbs_ram768_1023_o ;
- endcase
-end
-
-assign wbs_dat_o = sel_registers ? register_output : ram_output ;
-
-reg delayed_ack_for_reads ;
-
-always@(posedge clk_i or posedge rst_i)
-begin
- if (rst_i)
- delayed_ack_for_reads <= 1'b0 ;
- else if (delayed_ack_for_reads)
- delayed_ack_for_reads <= 1'b0 ;
- else
- delayed_ack_for_reads <= wbs_cyc_i & wbs_stb_i & (~wbs_we_i) ;
-end
-
-assign wbs_ack_o = wbs_we_i ? (wbs_cyc_i & wbs_stb_i) : delayed_ack_for_reads ;
-
-assign wbs_err_o = 1'b0 ;
-assign wbs_rty_o = 1'b0 ;
-
-reg wbm_cyc_o, wbm_cab_o, wbm_stb_o;
-reg [31:0] wbm_adr_o ;
-reg [31:0] wbm_next_adr_o ;
-
-wire wbm_end_cycle = wbm_cyc_o & wbm_stb_o & wbm_ack_i & (master_current_transaction_size == 11'h1) ;
-wire wbm_start_cycle = (master_transaction_size != 11'h0) & (master_transaction_count != 11'h0) & ~wbm_cyc_o ;
-
-always@(posedge clk_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- wbm_cyc_o <= 1'b0 ;
- wbm_cab_o <= 1'b0 ;
- wbm_stb_o <= 1'b0 ;
- wbm_adr_o <= 32'h0 ;
- master_current_transaction_size <= 11'h0 ;
- wbm_next_adr_o <= 32'h4 ;
- end
- else
- begin
- if (master_transaction_count == 11'h0)
- begin
- wbm_adr_o <= master_base ;
- wbm_next_adr_o <= master_base_next ;
- end
- else if (wbm_cyc_o & wbm_stb_o & wbm_ack_i)
- begin
- wbm_adr_o <= wbm_next_adr_o ;
- wbm_next_adr_o[31:2] <= wbm_next_adr_o[31:2] + 1'b1 ;
- end
-
- if (wbm_start_cycle)
- begin
- wbm_cyc_o <= 1'b1 ;
- wbm_cab_o <= (master_transaction_size != 11'h1) ;
- wbm_stb_o <= 1'b1 ;
- master_current_transaction_size <= master_transaction_size ;
- end
- else if (wbm_cyc_o)
- begin
- if (wbm_end_cycle)
- begin
- wbm_cyc_o <= 1'b0 ;
- wbm_stb_o <= 1'b0 ;
- wbm_cab_o <= 1'b0 ;
- end
- else
- begin
- if (wbm_stb_o & wbm_ack_i)
- begin
- master_current_transaction_size <= master_current_transaction_size - 1'b1 ;
- end
- end
- end
- end
-end
-
-wire [7:0] master_ram_adr = (wbm_we_o & wbm_ack_i) ? wbm_next_adr_o[9:2] : wbm_adr_o[9:2] ;
-
-RAMB4_S16_S16 ramb4_s16_s16_00
-(
- .CLKA(clk_i),
- .RSTA(rst_i),
- .ADDRA(wbs_adr_i[9:2]),
- .DIA(wbs_dat_i[31:16]),
- .ENA(1'b1),
- .WEA(wbs_ram0_255_we),
- .DOA(wbs_ram0_255_o[31:16]),
-
- .CLKB(clk_i),
- .RSTB(rst_i),
- .ADDRB(master_ram_adr),
- .DIB(wbm_dat_i[31:16]),
- .ENB(1'b1),
- .WEB(wbm_ram0_255_we),
- .DOB(wbm_ram0_255_o[31:16])
-);
-
-RAMB4_S16_S16 ramb4_s16_s16_01
-(
- .CLKA(clk_i),
- .RSTA(rst_i),
- .ADDRA(wbs_adr_i[9:2]),
- .DIA(wbs_dat_i[15:0]),
- .ENA(1'b1),
- .WEA(wbs_ram0_255_we),
- .DOA(wbs_ram0_255_o[15:0]),
-
- .CLKB(clk_i),
- .RSTB(rst_i),
- .ADDRB(master_ram_adr),
- .DIB(wbm_dat_i[15:0]),
- .ENB(1'b1),
- .WEB(wbm_ram0_255_we),
- .DOB(wbm_ram0_255_o[15:0])
-);
-
-RAMB4_S16_S16 ramb4_s16_s16_10
-(
- .CLKA(clk_i),
- .RSTA(rst_i),
- .ADDRA(wbs_adr_i[9:2]),
- .DIA(wbs_dat_i[31:16]),
- .ENA(1'b1),
- .WEA(wbs_ram256_511_we),
- .DOA(wbs_ram256_511_o[31:16]),
-
- .CLKB(clk_i),
- .RSTB(rst_i),
- .ADDRB(master_ram_adr),
- .DIB(wbm_dat_i[31:16]),
- .ENB(1'b1),
- .WEB(wbm_ram256_511_we),
- .DOB(wbm_ram256_511_o[31:16])
-);
-
-RAMB4_S16_S16 ramb4_s16_s16_11
-(
- .CLKA(clk_i),
- .RSTA(rst_i),
- .ADDRA(wbs_adr_i[9:2]),
- .DIA(wbs_dat_i[15:0]),
- .ENA(1'b1),
- .WEA(wbs_ram256_511_we),
- .DOA(wbs_ram256_511_o[15:0]),
-
- .CLKB(clk_i),
- .RSTB(rst_i),
- .ADDRB(master_ram_adr),
- .DIB(wbm_dat_i[15:0]),
- .ENB(1'b1),
- .WEB(wbm_ram256_511_we),
- .DOB(wbm_ram256_511_o[15:0])
-);
-
-RAMB4_S16_S16 ramb4_s16_s16_20
-(
- .CLKA(clk_i),
- .RSTA(rst_i),
- .ADDRA(wbs_adr_i[9:2]),
- .DIA(wbs_dat_i[31:16]),
- .ENA(1'b1),
- .WEA(wbs_ram512_767_we),
- .DOA(wbs_ram512_767_o[31:16]),
-
- .CLKB(clk_i),
- .RSTB(rst_i),
- .ADDRB(master_ram_adr),
- .DIB(wbm_dat_i[31:16]),
- .ENB(1'b1),
- .WEB(wbm_ram512_767_we),
- .DOB(wbm_ram512_767_o[31:16])
-);
-
-RAMB4_S16_S16 ramb4_s16_s16_21
-(
- .CLKA(clk_i),
- .RSTA(rst_i),
- .ADDRA(wbs_adr_i[9:2]),
- .DIA(wbs_dat_i[15:0]),
- .ENA(1'b1),
- .WEA(wbs_ram512_767_we),
- .DOA(wbs_ram512_767_o[15:0]),
-
- .CLKB(clk_i),
- .RSTB(rst_i),
- .ADDRB(master_ram_adr),
- .DIB(wbm_dat_i[15:0]),
- .ENB(1'b1),
- .WEB(wbm_ram512_767_we),
- .DOB(wbm_ram512_767_o[15:0])
-);
-
-RAMB4_S16_S16 ramb4_s16_s16_30
-(
- .CLKA(clk_i),
- .RSTA(rst_i),
- .ADDRA(wbs_adr_i[9:2]),
- .DIA(wbs_dat_i[31:16]),
- .ENA(1'b1),
- .WEA(wbs_ram768_1023_we),
- .DOA(wbs_ram768_1023_o[31:16]),
-
- .CLKB(clk_i),
- .RSTB(rst_i),
- .ADDRB(master_ram_adr),
- .DIB(wbm_dat_i[31:16]),
- .ENB(1'b1),
- .WEB(wbm_ram768_1023_we),
- .DOB(wbm_ram768_1023_o[31:16])
-);
-
-RAMB4_S16_S16 ramb4_s16_s16_31
-(
- .CLKA(clk_i),
- .RSTA(rst_i),
- .ADDRA(wbs_adr_i[9:2]),
- .DIA(wbs_dat_i[15:0]),
- .ENA(1'b1),
- .WEA(wbs_ram768_1023_we),
- .DOA(wbs_ram768_1023_o[15:0]),
-
- .CLKB(clk_i),
- .RSTB(rst_i),
- .ADDRB(master_ram_adr),
- .DIB(wbm_dat_i[15:0]),
- .ENB(1'b1),
- .WEB(wbm_ram768_1023_we),
- .DOB(wbm_ram768_1023_o[15:0])
-);
-
-endmodule // test
Index: trunk/apps/test/rtl/verilog/pci_test_top_2clks.v~
===================================================================
--- trunk/apps/test/rtl/verilog/pci_test_top_2clks.v~ (revision 97)
+++ trunk/apps/test/rtl/verilog/pci_test_top_2clks.v~ (nonexistent)
@@ -1,507 +0,0 @@
-module pci_test_top
-(
- pci_clk_pad_i,
- pci_rst_pad_i,
- clk_pad_i,
-
- pci_req_pad_o,
- pci_gnt_pad_i,
- pci_idsel_pad_i,
-
- pci_ad0_pad_io,
- pci_ad1_pad_io,
- pci_ad2_pad_io,
- pci_ad3_pad_io,
- pci_ad4_pad_io,
- pci_ad5_pad_io,
- pci_ad6_pad_io,
- pci_ad7_pad_io,
- pci_ad8_pad_io,
- pci_ad9_pad_io,
- pci_ad10_pad_io,
- pci_ad11_pad_io,
- pci_ad12_pad_io,
- pci_ad13_pad_io,
- pci_ad14_pad_io,
- pci_ad15_pad_io,
- pci_ad16_pad_io,
- pci_ad17_pad_io,
- pci_ad18_pad_io,
- pci_ad19_pad_io,
- pci_ad20_pad_io,
- pci_ad21_pad_io,
- pci_ad22_pad_io,
- pci_ad23_pad_io,
- pci_ad24_pad_io,
- pci_ad25_pad_io,
- pci_ad26_pad_io,
- pci_ad27_pad_io,
- pci_ad28_pad_io,
- pci_ad29_pad_io,
- pci_ad30_pad_io,
- pci_ad31_pad_io,
-
- pci_cbe0_pad_io,
- pci_cbe1_pad_io,
- pci_cbe2_pad_io,
- pci_cbe3_pad_io,
-
- pci_frame_pad_io,
- pci_irdy_pad_io,
- pci_devsel_pad_io,
- pci_trdy_pad_io,
- pci_stop_pad_io,
- pci_par_pad_io,
- pci_perr_pad_io,
- pci_serr_pad_o
-);
-
-// input/output inout declarations
-input pci_clk_pad_i,
- pci_rst_pad_i,
- clk_pad_i ;
-
-output pci_req_pad_o, pci_serr_pad_o ;
-input pci_gnt_pad_i,
- pci_idsel_pad_i ;
-
-inout pci_frame_pad_io,
- pci_irdy_pad_io,
- pci_devsel_pad_io,
- pci_trdy_pad_io,
- pci_stop_pad_io,
- pci_par_pad_io,
- pci_perr_pad_io,
- pci_ad0_pad_io,
- pci_ad1_pad_io,
- pci_ad2_pad_io,
- pci_ad3_pad_io,
- pci_ad4_pad_io,
- pci_ad5_pad_io,
- pci_ad6_pad_io,
- pci_ad7_pad_io,
- pci_ad8_pad_io,
- pci_ad9_pad_io,
- pci_ad10_pad_io,
- pci_ad11_pad_io,
- pci_ad12_pad_io,
- pci_ad13_pad_io,
- pci_ad14_pad_io,
- pci_ad15_pad_io,
- pci_ad16_pad_io,
- pci_ad17_pad_io,
- pci_ad18_pad_io,
- pci_ad19_pad_io,
- pci_ad20_pad_io,
- pci_ad21_pad_io,
- pci_ad22_pad_io,
- pci_ad23_pad_io,
- pci_ad24_pad_io,
- pci_ad25_pad_io,
- pci_ad26_pad_io,
- pci_ad27_pad_io,
- pci_ad28_pad_io,
- pci_ad29_pad_io,
- pci_ad30_pad_io,
- pci_ad31_pad_io,
- pci_cbe0_pad_io,
- pci_cbe1_pad_io,
- pci_cbe2_pad_io,
- pci_cbe3_pad_io ;
-
-// wires for test master to pci slave connections
-wire wbm_test_wbs_pci_cyc,
- wbm_test_wbs_pci_stb,
- wbm_test_wbs_pci_cab,
- wbm_test_wbs_pci_we,
- wbs_pci_wbm_test_ack ;
-
-wire [31:0] wbm_test_wbs_pci_adr,
- wbm_test_wbs_pci_dat,
- wbs_pci_wbm_test_dat ;
-
-wire [3:0] wbm_test_wbs_pci_sel ;
-
-// wires for test slave to pci master connections
-wire wbm_pci_wbs_test_cyc,
- wbm_pci_wbs_test_stb,
- wbm_pci_wbs_test_cab,
- wbm_pci_wbs_test_we,
- wbs_test_wbm_pci_ack ;
-
-wire [31:0] wbm_pci_wbs_test_adr,
- wbm_pci_wbs_test_dat,
- wbs_test_wbm_pci_dat ;
-
-wire [3:0] wbm_pci_wbs_test_sel ;
-
-wire wb_rst ;
-
-wire wb_clk ;
-wire wb_clk_unbuf ;
-
-wire clk0 ;
-wire clk0_buf ;
-wire clk_i_buf ;
-
-CLKDLL i_clkdll
-(
- .CLKIN ( clk_i_buf ),
- .CLKFB ( clk0_buf ),
- .RST ( 1'b0 ),
- .CLK2X ( ),
- .CLK0 ( clk0 ),
- .CLK90 ( ),
- .CLK180 ( ),
- .CLK270 ( ),
- .CLKDV ( wb_clk_unbuf ),
- .LOCKED ( )
-);
-
-BUFG i_bufg_clk0
-(
- .I( clk0 ),
- .O( clk0_buf )
-) ;
-
-BUFG i_bufg_wb_clk
-(
- .I( wb_clk_unbuf ),
- .O( wb_clk )
-) ;
-
-IBUFG i_ibufg_clk_pad_i
-(
- .I( clk_pad_i ),
- .O( clk_i_buf )
-) ;
-
-// prevent concurent accesses through pci bridge master and slave interfaces
-reg test_wbs_cyc ;
-reg pci_wbs_cyc ;
-
-always@(posedge wb_clk or posedge wb_rst)
-begin
- if (wb_rst)
- begin
- test_wbs_cyc <= 1'b0 ;
- pci_wbs_cyc <= 1'b0 ;
- end
- else
- begin
- if (~pci_wbs_cyc & ~test_wbs_cyc)
- begin
- // currently no cyc signal is asserted - the pci bridge wb master will have the priority here, so check if it has cycle asserted!
- if (wbm_pci_wbs_test_cyc)
- test_wbs_cyc <= 1'b1 ;
- else // no cycle is asserted and pci wb master is not starting the transaction - test wb master can start
- pci_wbs_cyc <= wbm_test_wbs_pci_cyc ;
- end
- else
- begin
- // at least one of the cycles is asserted - wait for transaction to finish
- if (test_wbs_cyc)
- test_wbs_cyc <= wbm_pci_wbs_test_cyc ;
-
- if (pci_wbs_cyc)
- pci_wbs_cyc <= wbm_test_wbs_pci_cyc ;
- end
- end
-end
-
-wire pci_irdy_out,
- pci_irdy_en,
- pci_trdy_reg ;
-
-reg pci_irdy_reg ;
-reg pci_irdy_en_reg ;
-always@(posedge pci_clk_pad_i or negedge pci_rst_pad_i)
-begin
- if (~pci_rst_pad_i)
- begin
- pci_irdy_reg <= 1'b1 ;
- pci_irdy_en_reg <= 1'b0 ;
- end
- else
- begin
- pci_irdy_reg <= pci_irdy_out ;
- pci_irdy_en_reg <= pci_irdy_en ;
- end
-end
-
-test i_test
-(
- .clk_i (wb_clk),
- .rst_i (wb_rst),
-
- .wbm_cyc_o (wbm_test_wbs_pci_cyc),
- .wbm_stb_o (wbm_test_wbs_pci_stb),
- .wbm_cab_o (wbm_test_wbs_pci_cab),
- .wbm_we_o (wbm_test_wbs_pci_we),
- .wbm_adr_o (wbm_test_wbs_pci_adr),
- .wbm_sel_o (wbm_test_wbs_pci_sel),
- .wbm_dat_o (wbm_test_wbs_pci_dat),
- .wbm_dat_i (wbs_pci_wbm_test_dat),
- .wbm_ack_i (wbs_pci_wbm_test_ack),
- .wbm_rty_i (1'b0),
- .wbm_err_i (1'b0),
-
- .wbs_cyc_i (test_wbs_cyc),
- .wbs_stb_i (wbm_pci_wbs_test_stb),
- .wbs_cab_i (wbm_pci_wbs_test_cab),
- .wbs_we_i (wbm_pci_wbs_test_we),
- .wbs_adr_i (wbm_pci_wbs_test_adr),
- .wbs_sel_i (wbm_pci_wbs_test_sel),
- .wbs_dat_i (wbm_pci_wbs_test_dat),
- .wbs_dat_o (wbs_test_wbm_pci_dat),
- .wbs_ack_o (wbs_test_wbm_pci_ack),
- .wbs_rty_o (),
- .wbs_err_o (),
-
- .pci_irdy_reg_i (pci_irdy_reg),
- .pci_irdy_en_reg_i (pci_irdy_en_reg),
- .pci_trdy_reg_i (pci_trdy_reg)
-);
-
-wire pci_req_o,
- pci_req_oe,
- pci_frame_i,
- pci_frame_o,
- pci_frame_oe,
- pci_irdy_oe,
- pci_devsel_oe,
- pci_trdy_oe,
- pci_stop_oe,
- pci_irdy_i,
- pci_irdy_o,
- pci_devsel_i,
- pci_devsel_o,
- pci_trdy_i,
- pci_trdy_o,
- pci_stop_i,
- pci_stop_o,
- pci_par_i,
- pci_par_o,
- pci_par_oe,
- pci_perr_i,
- pci_perr_o,
- pci_perr_oe,
- pci_serr_o,
- pci_serr_oe
-;
-
-wire [31:0] pci_ad_oe,
- pci_ad_i,
- pci_ad_o ;
-
-wire [3:0] pci_cbe_oe,
- pci_cbe_i,
- pci_cbe_o ;
-
-bufif0 ad_buffer00 (pci_ad0_pad_io , pci_ad_o[0] , pci_ad_oe[0] ) ;
-bufif0 ad_buffer01 (pci_ad1_pad_io , pci_ad_o[1] , pci_ad_oe[1] ) ;
-bufif0 ad_buffer02 (pci_ad2_pad_io , pci_ad_o[2] , pci_ad_oe[2] ) ;
-bufif0 ad_buffer03 (pci_ad3_pad_io , pci_ad_o[3] , pci_ad_oe[3] ) ;
-bufif0 ad_buffer04 (pci_ad4_pad_io , pci_ad_o[4] , pci_ad_oe[4] ) ;
-bufif0 ad_buffer05 (pci_ad5_pad_io , pci_ad_o[5] , pci_ad_oe[5] ) ;
-bufif0 ad_buffer06 (pci_ad6_pad_io , pci_ad_o[6] , pci_ad_oe[6] ) ;
-bufif0 ad_buffer07 (pci_ad7_pad_io , pci_ad_o[7] , pci_ad_oe[7] ) ;
-bufif0 ad_buffer08 (pci_ad8_pad_io , pci_ad_o[8] , pci_ad_oe[8] ) ;
-bufif0 ad_buffer09 (pci_ad9_pad_io , pci_ad_o[9] , pci_ad_oe[9] ) ;
-bufif0 ad_buffer10 (pci_ad10_pad_io, pci_ad_o[10], pci_ad_oe[10]) ;
-bufif0 ad_buffer11 (pci_ad11_pad_io, pci_ad_o[11], pci_ad_oe[11]) ;
-bufif0 ad_buffer12 (pci_ad12_pad_io, pci_ad_o[12], pci_ad_oe[12]) ;
-bufif0 ad_buffer13 (pci_ad13_pad_io, pci_ad_o[13], pci_ad_oe[13]) ;
-bufif0 ad_buffer14 (pci_ad14_pad_io, pci_ad_o[14], pci_ad_oe[14]) ;
-bufif0 ad_buffer15 (pci_ad15_pad_io, pci_ad_o[15], pci_ad_oe[15]) ;
-bufif0 ad_buffer16 (pci_ad16_pad_io, pci_ad_o[16], pci_ad_oe[16]) ;
-bufif0 ad_buffer17 (pci_ad17_pad_io, pci_ad_o[17], pci_ad_oe[17]) ;
-bufif0 ad_buffer18 (pci_ad18_pad_io, pci_ad_o[18], pci_ad_oe[18]) ;
-bufif0 ad_buffer19 (pci_ad19_pad_io, pci_ad_o[19], pci_ad_oe[19]) ;
-bufif0 ad_buffer20 (pci_ad20_pad_io, pci_ad_o[20], pci_ad_oe[20]) ;
-bufif0 ad_buffer21 (pci_ad21_pad_io, pci_ad_o[21], pci_ad_oe[21]) ;
-bufif0 ad_buffer22 (pci_ad22_pad_io, pci_ad_o[22], pci_ad_oe[22]) ;
-bufif0 ad_buffer23 (pci_ad23_pad_io, pci_ad_o[23], pci_ad_oe[23]) ;
-bufif0 ad_buffer24 (pci_ad24_pad_io, pci_ad_o[24], pci_ad_oe[24]) ;
-bufif0 ad_buffer25 (pci_ad25_pad_io, pci_ad_o[25], pci_ad_oe[25]) ;
-bufif0 ad_buffer26 (pci_ad26_pad_io, pci_ad_o[26], pci_ad_oe[26]) ;
-bufif0 ad_buffer27 (pci_ad27_pad_io, pci_ad_o[27], pci_ad_oe[27]) ;
-bufif0 ad_buffer28 (pci_ad28_pad_io, pci_ad_o[28], pci_ad_oe[28]) ;
-bufif0 ad_buffer29 (pci_ad29_pad_io, pci_ad_o[29], pci_ad_oe[29]) ;
-bufif0 ad_buffer30 (pci_ad30_pad_io, pci_ad_o[30], pci_ad_oe[30]) ;
-bufif0 ad_buffer31 (pci_ad31_pad_io, pci_ad_o[31], pci_ad_oe[31]) ;
-
-bufif0 cbe_buffer0 (pci_cbe0_pad_io, pci_cbe_o[0], pci_cbe_oe[0]) ;
-bufif0 cbe_buffer1 (pci_cbe1_pad_io, pci_cbe_o[1], pci_cbe_oe[1]) ;
-bufif0 cbe_buffer2 (pci_cbe2_pad_io, pci_cbe_o[2], pci_cbe_oe[2]) ;
-bufif0 cbe_buffer3 (pci_cbe3_pad_io, pci_cbe_o[3], pci_cbe_oe[3]) ;
-
-assign pci_ad_i = {
- pci_ad31_pad_io,
- pci_ad30_pad_io,
- pci_ad29_pad_io,
- pci_ad28_pad_io,
- pci_ad27_pad_io,
- pci_ad26_pad_io,
- pci_ad25_pad_io,
- pci_ad24_pad_io,
- pci_ad23_pad_io,
- pci_ad22_pad_io,
- pci_ad21_pad_io,
- pci_ad20_pad_io,
- pci_ad19_pad_io,
- pci_ad18_pad_io,
- pci_ad17_pad_io,
- pci_ad16_pad_io,
- pci_ad15_pad_io,
- pci_ad14_pad_io,
- pci_ad13_pad_io,
- pci_ad12_pad_io,
- pci_ad11_pad_io,
- pci_ad10_pad_io,
- pci_ad9_pad_io,
- pci_ad8_pad_io,
- pci_ad7_pad_io,
- pci_ad6_pad_io,
- pci_ad5_pad_io,
- pci_ad4_pad_io,
- pci_ad3_pad_io,
- pci_ad2_pad_io,
- pci_ad1_pad_io,
- pci_ad0_pad_io
-} ;
-
-assign pci_cbe_i = {
- pci_cbe3_pad_io,
- pci_cbe2_pad_io,
- pci_cbe1_pad_io,
- pci_cbe0_pad_io
-} ;
-
-bufif0 req_buf (pci_req_pad_o, pci_req_o, pci_req_oe) ;
-
-bufif0 frame_buf (pci_frame_pad_io, pci_frame_o, pci_frame_oe) ;
-assign pci_frame_i = pci_frame_pad_io ;
-
-bufif0 irdy_buf (pci_irdy_pad_io, pci_irdy_o, pci_irdy_oe) ;
-assign pci_irdy_i = pci_irdy_pad_io ;
-
-bufif0 devsel_buf (pci_devsel_pad_io, pci_devsel_o, pci_devsel_oe) ;
-assign pci_devsel_i = pci_devsel_pad_io ;
-
-bufif0 trdy_buf (pci_trdy_pad_io, pci_trdy_o, pci_trdy_oe) ;
-assign pci_trdy_i = pci_trdy_pad_io ;
-
-bufif0 stop_buf (pci_stop_pad_io, pci_stop_o, pci_stop_oe) ;
-assign pci_stop_i = pci_stop_pad_io ;
-
-bufif0 par_buf (pci_par_pad_io, pci_par_o, pci_par_oe) ;
-assign pci_par_i = pci_par_pad_io ;
-
-bufif0 perr_buf (pci_perr_pad_io, pci_perr_o, pci_perr_oe) ;
-assign pci_perr_i = pci_perr_pad_io ;
-
-bufif0 serr_buf (pci_serr_pad_o, pci_serr_o, pci_serr_oe) ;
-
-pci_bridge32 i_pci_bridge32
-(
- // WISHBONE system signals
- .wb_clk_i(wb_clk),
- .wb_rst_i(1'b0),
- .wb_rst_o(wb_rst),
- .wb_int_i(1'b0),
- .wb_int_o(),
-
- // WISHBONE slave interface
- .wbs_adr_i(wbm_test_wbs_pci_adr),
- .wbs_dat_i(wbm_test_wbs_pci_dat),
- .wbs_dat_o(wbs_pci_wbm_test_dat),
- .wbs_sel_i(wbm_test_wbs_pci_sel),
- .wbs_cyc_i(pci_wbs_cyc),
- .wbs_stb_i(wbm_test_wbs_pci_stb),
- .wbs_we_i (wbm_test_wbs_pci_we),
- .wbs_cab_i(wbm_test_wbs_pci_cab),
- .wbs_ack_o(wbs_pci_wbm_test_ack),
- .wbs_rty_o(),
- .wbs_err_o(),
-
- // WISHBONE master interface
- .wbm_adr_o(wbm_pci_wbs_test_adr),
- .wbm_dat_i(wbs_test_wbm_pci_dat),
- .wbm_dat_o(wbm_pci_wbs_test_dat),
- .wbm_sel_o(wbm_pci_wbs_test_sel),
- .wbm_cyc_o(wbm_pci_wbs_test_cyc),
- .wbm_stb_o(wbm_pci_wbs_test_stb),
- .wbm_we_o (wbm_pci_wbs_test_we),
- .wbm_cab_o(wbm_pci_wbs_test_cab),
- .wbm_ack_i(wbs_test_wbm_pci_ack),
- .wbm_rty_i(1'b0),
- .wbm_err_i(1'b0),
-
- // pci interface - system pins
- .pci_clk_i (pci_clk_pad_i),
- .pci_rst_i (pci_rst_pad_i),
- .pci_rst_o (),
- .pci_inta_i (1'b1),
- .pci_inta_o (),
- .pci_rst_oe_o (),
- .pci_inta_oe_o (),
-
- // arbitration pins
- .pci_req_o (pci_req_o),
- .pci_req_oe_o (pci_req_oe),
-
- .pci_gnt_i (pci_gnt_pad_i),
-
- // protocol pins
- .pci_frame_i (pci_frame_i),
- .pci_frame_o (pci_frame_o),
-
- .pci_frame_oe_o (pci_frame_oe),
- .pci_irdy_oe_o (pci_irdy_oe),
- .pci_devsel_oe_o(pci_devsel_oe),
- .pci_trdy_oe_o (pci_trdy_oe),
- .pci_stop_oe_o (pci_stop_oe),
- .pci_ad_oe_o (pci_ad_oe),
- .pci_cbe_oe_o (pci_cbe_oe),
-
- .pci_irdy_i (pci_irdy_i),
- .pci_irdy_o (pci_irdy_o),
-
- .pci_idsel_i (pci_idsel_pad_i),
-
- .pci_devsel_i (pci_devsel_i),
- .pci_devsel_o (pci_devsel_o),
-
- .pci_trdy_i (pci_trdy_i),
- .pci_trdy_o (pci_trdy_o),
-
- .pci_stop_i (pci_stop_i),
- .pci_stop_o (pci_stop_o),
-
- // data transfer pins
- .pci_ad_i (pci_ad_i),
- .pci_ad_o (pci_ad_o),
-
- .pci_cbe_i (pci_cbe_i),
- .pci_cbe_o (pci_cbe_o),
-
- // parity generation and checking pins
- .pci_par_i (pci_par_i),
- .pci_par_o (pci_par_o),
- .pci_par_oe_o (pci_par_oe),
-
- .pci_perr_i (pci_perr_i),
- .pci_perr_o (pci_perr_o),
- .pci_perr_oe_o (pci_perr_oe),
-
- // system error pin
- .pci_serr_o (pci_serr_o),
- .pci_serr_oe_o (pci_serr_oe),
-
- // debug
- .trdy_reg_o (pci_trdy_reg),
- .irdy_o (pci_irdy_out),
- .irdy_en_o (pci_irdy_en)
-);
-endmodule // pci_test_top
trunk/apps/test/rtl/verilog/pci_test_top_2clks.v~
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/apps/test/rtl/verilog/pci_test_top_1clk.v~
===================================================================
--- trunk/apps/test/rtl/verilog/pci_test_top_1clk.v~ (revision 97)
+++ trunk/apps/test/rtl/verilog/pci_test_top_1clk.v~ (nonexistent)
@@ -1,461 +0,0 @@
-module pci_test_top
-(
- pci_clk_pad_i,
- pci_rst_pad_i,
-
- pci_req_pad_o,
- pci_gnt_pad_i,
- pci_idsel_pad_i,
-
- pci_ad0_pad_io,
- pci_ad1_pad_io,
- pci_ad2_pad_io,
- pci_ad3_pad_io,
- pci_ad4_pad_io,
- pci_ad5_pad_io,
- pci_ad6_pad_io,
- pci_ad7_pad_io,
- pci_ad8_pad_io,
- pci_ad9_pad_io,
- pci_ad10_pad_io,
- pci_ad11_pad_io,
- pci_ad12_pad_io,
- pci_ad13_pad_io,
- pci_ad14_pad_io,
- pci_ad15_pad_io,
- pci_ad16_pad_io,
- pci_ad17_pad_io,
- pci_ad18_pad_io,
- pci_ad19_pad_io,
- pci_ad20_pad_io,
- pci_ad21_pad_io,
- pci_ad22_pad_io,
- pci_ad23_pad_io,
- pci_ad24_pad_io,
- pci_ad25_pad_io,
- pci_ad26_pad_io,
- pci_ad27_pad_io,
- pci_ad28_pad_io,
- pci_ad29_pad_io,
- pci_ad30_pad_io,
- pci_ad31_pad_io,
-
- pci_cbe0_pad_io,
- pci_cbe1_pad_io,
- pci_cbe2_pad_io,
- pci_cbe3_pad_io,
-
- pci_frame_pad_io,
- pci_irdy_pad_io,
- pci_devsel_pad_io,
- pci_trdy_pad_io,
- pci_stop_pad_io,
- pci_par_pad_io,
- pci_perr_pad_io,
- pci_serr_pad_o
-);
-
-// input/output inout declarations
-input pci_clk_pad_i,
- pci_rst_pad_i ;
-
-output pci_req_pad_o, pci_serr_pad_o ;
-input pci_gnt_pad_i,
- pci_idsel_pad_i ;
-
-inout pci_frame_pad_io,
- pci_irdy_pad_io,
- pci_devsel_pad_io,
- pci_trdy_pad_io,
- pci_stop_pad_io,
- pci_par_pad_io,
- pci_perr_pad_io,
- pci_ad0_pad_io,
- pci_ad1_pad_io,
- pci_ad2_pad_io,
- pci_ad3_pad_io,
- pci_ad4_pad_io,
- pci_ad5_pad_io,
- pci_ad6_pad_io,
- pci_ad7_pad_io,
- pci_ad8_pad_io,
- pci_ad9_pad_io,
- pci_ad10_pad_io,
- pci_ad11_pad_io,
- pci_ad12_pad_io,
- pci_ad13_pad_io,
- pci_ad14_pad_io,
- pci_ad15_pad_io,
- pci_ad16_pad_io,
- pci_ad17_pad_io,
- pci_ad18_pad_io,
- pci_ad19_pad_io,
- pci_ad20_pad_io,
- pci_ad21_pad_io,
- pci_ad22_pad_io,
- pci_ad23_pad_io,
- pci_ad24_pad_io,
- pci_ad25_pad_io,
- pci_ad26_pad_io,
- pci_ad27_pad_io,
- pci_ad28_pad_io,
- pci_ad29_pad_io,
- pci_ad30_pad_io,
- pci_ad31_pad_io,
- pci_cbe0_pad_io,
- pci_cbe1_pad_io,
- pci_cbe2_pad_io,
- pci_cbe3_pad_io ;
-
-// wires for test master to pci slave connections
-wire wbm_test_wbs_pci_cyc,
- wbm_test_wbs_pci_stb,
- wbm_test_wbs_pci_cab,
- wbm_test_wbs_pci_we,
- wbs_pci_wbm_test_ack ;
-
-wire [31:0] wbm_test_wbs_pci_adr,
- wbm_test_wbs_pci_dat,
- wbs_pci_wbm_test_dat ;
-
-wire [3:0] wbm_test_wbs_pci_sel ;
-
-// wires for test slave to pci master connections
-wire wbm_pci_wbs_test_cyc,
- wbm_pci_wbs_test_stb,
- wbm_pci_wbs_test_cab,
- wbm_pci_wbs_test_we,
- wbs_test_wbm_pci_ack ;
-
-wire [31:0] wbm_pci_wbs_test_adr,
- wbm_pci_wbs_test_dat,
- wbs_test_wbm_pci_dat ;
-
-wire [3:0] wbm_pci_wbs_test_sel ;
-
-wire wb_rst ;
-
-wire wb_clk = pci_clk_pad_i;
-
-// prevent concurent accesses through pci bridge master and slave interfaces
-reg test_wbs_cyc ;
-reg pci_wbs_cyc ;
-
-always@(posedge wb_clk or posedge wb_rst)
-begin
- if (wb_rst)
- begin
- test_wbs_cyc <= 1'b0 ;
- pci_wbs_cyc <= 1'b0 ;
- end
- else
- begin
- if (~pci_wbs_cyc & ~test_wbs_cyc)
- begin
- // currently no cyc signal is asserted - the pci bridge wb master will have the priority here, so check if it has cycle asserted!
- if (wbm_pci_wbs_test_cyc)
- test_wbs_cyc <= 1'b1 ;
- else // no cycle is asserted and pci wb master is not starting the transaction - test wb master can start
- pci_wbs_cyc <= wbm_test_wbs_pci_cyc ;
- end
- else
- begin
- // at least one of the cycles is asserted - wait for transaction to finish
- if (test_wbs_cyc)
- test_wbs_cyc <= wbm_pci_wbs_test_cyc ;
-
- if (pci_wbs_cyc)
- pci_wbs_cyc <= wbm_test_wbs_pci_cyc ;
- end
- end
-end
-
-reg pci_irdy_reg,
- pci_irdy_en_reg ;
-
-wire pci_trdy_reg = i_pci_bridge32.input_register.pci_trdy_reg_out ;
-
-always@(posedge pci_clk_pad_i or negedge pci_rst_pad_i)
-begin
- if (~pci_rst_pad_i)
- begin
- pci_irdy_reg <= 1'b1 ;
- pci_irdy_en_reg <= 1'b0 ;
- end
- else
- pci_irdy_reg <= i_pci_bridge32.output_backup.irdy_out ;
- pci_irdy_en_reg <= i_pci_bridge32.output_backup.irdy_en_out ;
- end
-end
-
-test i_test
-(
- .clk_i (wb_clk),
- .rst_i (wb_rst),
-
- .wbm_cyc_o (wbm_test_wbs_pci_cyc),
- .wbm_stb_o (wbm_test_wbs_pci_stb),
- .wbm_cab_o (wbm_test_wbs_pci_cab),
- .wbm_we_o (wbm_test_wbs_pci_we),
- .wbm_adr_o (wbm_test_wbs_pci_adr),
- .wbm_sel_o (wbm_test_wbs_pci_sel),
- .wbm_dat_o (wbm_test_wbs_pci_dat),
- .wbm_dat_i (wbs_pci_wbm_test_dat),
- .wbm_ack_i (wbs_pci_wbm_test_ack),
- .wbm_rty_i (1'b0),
- .wbm_err_i (1'b0),
-
- .wbs_cyc_i (test_wbs_cyc),
- .wbs_stb_i (wbm_pci_wbs_test_stb),
- .wbs_cab_i (wbm_pci_wbs_test_cab),
- .wbs_we_i (wbm_pci_wbs_test_we),
- .wbs_adr_i (wbm_pci_wbs_test_adr),
- .wbs_sel_i (wbm_pci_wbs_test_sel),
- .wbs_dat_i (wbm_pci_wbs_test_dat),
- .wbs_dat_o (wbs_test_wbm_pci_dat),
- .wbs_ack_o (wbs_test_wbm_pci_ack),
- .wbs_rty_o (),
- .wbs_err_o (),
-
- .pci_irdy_reg_i (i_pci_bridge32.output_backup.),
- .pci_irdy_en_reg_i (),
- .pci_trdy_reg_i ()
-);
-
-wire pci_req_o,
- pci_req_oe,
- pci_frame_i,
- pci_frame_o,
- pci_frame_oe,
- pci_irdy_oe,
- pci_devsel_oe,
- pci_trdy_oe,
- pci_stop_oe,
- pci_irdy_i,
- pci_irdy_o,
- pci_devsel_i,
- pci_devsel_o,
- pci_trdy_i,
- pci_trdy_o,
- pci_stop_i,
- pci_stop_o,
- pci_par_i,
- pci_par_o,
- pci_par_oe,
- pci_perr_i,
- pci_perr_o,
- pci_perr_oe,
- pci_serr_o,
- pci_serr_oe
-;
-
-wire [31:0] pci_ad_oe,
- pci_ad_i,
- pci_ad_o ;
-
-wire [3:0] pci_cbe_oe,
- pci_cbe_i,
- pci_cbe_o ;
-
-bufif0 ad_buffer00 (pci_ad0_pad_io , pci_ad_o[0] , pci_ad_oe[0] ) ;
-bufif0 ad_buffer01 (pci_ad1_pad_io , pci_ad_o[1] , pci_ad_oe[1] ) ;
-bufif0 ad_buffer02 (pci_ad2_pad_io , pci_ad_o[2] , pci_ad_oe[2] ) ;
-bufif0 ad_buffer03 (pci_ad3_pad_io , pci_ad_o[3] , pci_ad_oe[3] ) ;
-bufif0 ad_buffer04 (pci_ad4_pad_io , pci_ad_o[4] , pci_ad_oe[4] ) ;
-bufif0 ad_buffer05 (pci_ad5_pad_io , pci_ad_o[5] , pci_ad_oe[5] ) ;
-bufif0 ad_buffer06 (pci_ad6_pad_io , pci_ad_o[6] , pci_ad_oe[6] ) ;
-bufif0 ad_buffer07 (pci_ad7_pad_io , pci_ad_o[7] , pci_ad_oe[7] ) ;
-bufif0 ad_buffer08 (pci_ad8_pad_io , pci_ad_o[8] , pci_ad_oe[8] ) ;
-bufif0 ad_buffer09 (pci_ad9_pad_io , pci_ad_o[9] , pci_ad_oe[9] ) ;
-bufif0 ad_buffer10 (pci_ad10_pad_io, pci_ad_o[10], pci_ad_oe[10]) ;
-bufif0 ad_buffer11 (pci_ad11_pad_io, pci_ad_o[11], pci_ad_oe[11]) ;
-bufif0 ad_buffer12 (pci_ad12_pad_io, pci_ad_o[12], pci_ad_oe[12]) ;
-bufif0 ad_buffer13 (pci_ad13_pad_io, pci_ad_o[13], pci_ad_oe[13]) ;
-bufif0 ad_buffer14 (pci_ad14_pad_io, pci_ad_o[14], pci_ad_oe[14]) ;
-bufif0 ad_buffer15 (pci_ad15_pad_io, pci_ad_o[15], pci_ad_oe[15]) ;
-bufif0 ad_buffer16 (pci_ad16_pad_io, pci_ad_o[16], pci_ad_oe[16]) ;
-bufif0 ad_buffer17 (pci_ad17_pad_io, pci_ad_o[17], pci_ad_oe[17]) ;
-bufif0 ad_buffer18 (pci_ad18_pad_io, pci_ad_o[18], pci_ad_oe[18]) ;
-bufif0 ad_buffer19 (pci_ad19_pad_io, pci_ad_o[19], pci_ad_oe[19]) ;
-bufif0 ad_buffer20 (pci_ad20_pad_io, pci_ad_o[20], pci_ad_oe[20]) ;
-bufif0 ad_buffer21 (pci_ad21_pad_io, pci_ad_o[21], pci_ad_oe[21]) ;
-bufif0 ad_buffer22 (pci_ad22_pad_io, pci_ad_o[22], pci_ad_oe[22]) ;
-bufif0 ad_buffer23 (pci_ad23_pad_io, pci_ad_o[23], pci_ad_oe[23]) ;
-bufif0 ad_buffer24 (pci_ad24_pad_io, pci_ad_o[24], pci_ad_oe[24]) ;
-bufif0 ad_buffer25 (pci_ad25_pad_io, pci_ad_o[25], pci_ad_oe[25]) ;
-bufif0 ad_buffer26 (pci_ad26_pad_io, pci_ad_o[26], pci_ad_oe[26]) ;
-bufif0 ad_buffer27 (pci_ad27_pad_io, pci_ad_o[27], pci_ad_oe[27]) ;
-bufif0 ad_buffer28 (pci_ad28_pad_io, pci_ad_o[28], pci_ad_oe[28]) ;
-bufif0 ad_buffer29 (pci_ad29_pad_io, pci_ad_o[29], pci_ad_oe[29]) ;
-bufif0 ad_buffer30 (pci_ad30_pad_io, pci_ad_o[30], pci_ad_oe[30]) ;
-bufif0 ad_buffer31 (pci_ad31_pad_io, pci_ad_o[31], pci_ad_oe[31]) ;
-
-bufif0 cbe_buffer0 (pci_cbe0_pad_io, pci_cbe_o[0], pci_cbe_oe[0]) ;
-bufif0 cbe_buffer1 (pci_cbe1_pad_io, pci_cbe_o[1], pci_cbe_oe[1]) ;
-bufif0 cbe_buffer2 (pci_cbe2_pad_io, pci_cbe_o[2], pci_cbe_oe[2]) ;
-bufif0 cbe_buffer3 (pci_cbe3_pad_io, pci_cbe_o[3], pci_cbe_oe[3]) ;
-
-assign pci_ad_i = {
- pci_ad31_pad_io,
- pci_ad30_pad_io,
- pci_ad29_pad_io,
- pci_ad28_pad_io,
- pci_ad27_pad_io,
- pci_ad26_pad_io,
- pci_ad25_pad_io,
- pci_ad24_pad_io,
- pci_ad23_pad_io,
- pci_ad22_pad_io,
- pci_ad21_pad_io,
- pci_ad20_pad_io,
- pci_ad19_pad_io,
- pci_ad18_pad_io,
- pci_ad17_pad_io,
- pci_ad16_pad_io,
- pci_ad15_pad_io,
- pci_ad14_pad_io,
- pci_ad13_pad_io,
- pci_ad12_pad_io,
- pci_ad11_pad_io,
- pci_ad10_pad_io,
- pci_ad9_pad_io,
- pci_ad8_pad_io,
- pci_ad7_pad_io,
- pci_ad6_pad_io,
- pci_ad5_pad_io,
- pci_ad4_pad_io,
- pci_ad3_pad_io,
- pci_ad2_pad_io,
- pci_ad1_pad_io,
- pci_ad0_pad_io
-} ;
-
-assign pci_cbe_i = {
- pci_cbe3_pad_io,
- pci_cbe2_pad_io,
- pci_cbe1_pad_io,
- pci_cbe0_pad_io
-} ;
-
-bufif0 req_buf (pci_req_pad_o, pci_req_o, pci_req_oe) ;
-
-bufif0 frame_buf (pci_frame_pad_io, pci_frame_o, pci_frame_oe) ;
-assign pci_frame_i = pci_frame_pad_io ;
-
-bufif0 irdy_buf (pci_irdy_pad_io, pci_irdy_o, pci_irdy_oe) ;
-assign pci_irdy_i = pci_irdy_pad_io ;
-
-bufif0 devsel_buf (pci_devsel_pad_io, pci_devsel_o, pci_devsel_oe) ;
-assign pci_devsel_i = pci_devsel_pad_io ;
-
-bufif0 trdy_buf (pci_trdy_pad_io, pci_trdy_o, pci_trdy_oe) ;
-assign pci_trdy_i = pci_trdy_pad_io ;
-
-bufif0 stop_buf (pci_stop_pad_io, pci_stop_o, pci_stop_oe) ;
-assign pci_stop_i = pci_stop_pad_io ;
-
-bufif0 par_buf (pci_par_pad_io, pci_par_o, pci_par_oe) ;
-assign pci_par_i = pci_par_pad_io ;
-
-bufif0 perr_buf (pci_perr_pad_io, pci_perr_o, pci_perr_oe) ;
-assign pci_perr_i = pci_perr_pad_io ;
-
-bufif0 serr_buf (pci_serr_pad_o, pci_serr_o, pci_serr_oe) ;
-
-pci_bridge32 i_pci_bridge32
-(
- // WISHBONE system signals
- .wb_clk_i(wb_clk),
- .wb_rst_i(1'b0),
- .wb_rst_o(wb_rst),
- .wb_int_i(1'b0),
- .wb_int_o(),
-
- // WISHBONE slave interface
- .wbs_adr_i(wbm_test_wbs_pci_adr),
- .wbs_dat_i(wbm_test_wbs_pci_dat),
- .wbs_dat_o(wbs_pci_wbm_test_dat),
- .wbs_sel_i(wbm_test_wbs_pci_sel),
- .wbs_cyc_i(pci_wbs_cyc),
- .wbs_stb_i(wbm_test_wbs_pci_stb),
- .wbs_we_i (wbm_test_wbs_pci_we),
- .wbs_cab_i(wbm_test_wbs_pci_cab),
- .wbs_ack_o(wbs_pci_wbm_test_ack),
- .wbs_rty_o(),
- .wbs_err_o(),
-
- // WISHBONE master interface
- .wbm_adr_o(wbm_pci_wbs_test_adr),
- .wbm_dat_i(wbs_test_wbm_pci_dat),
- .wbm_dat_o(wbm_pci_wbs_test_dat),
- .wbm_sel_o(wbm_pci_wbs_test_sel),
- .wbm_cyc_o(wbm_pci_wbs_test_cyc),
- .wbm_stb_o(wbm_pci_wbs_test_stb),
- .wbm_we_o (wbm_pci_wbs_test_we),
- .wbm_cab_o(wbm_pci_wbs_test_cab),
- .wbm_ack_i(wbs_test_wbm_pci_ack),
- .wbm_rty_i(1'b0),
- .wbm_err_i(1'b0),
-
- // pci interface - system pins
- .pci_clk_i (pci_clk_pad_i),
- .pci_rst_i (pci_rst_pad_i),
- .pci_rst_o (),
- .pci_inta_i (1'b1),
- .pci_inta_o (),
- .pci_rst_oe_o (),
- .pci_inta_oe_o (),
-
- // arbitration pins
- .pci_req_o (pci_req_o),
- .pci_req_oe_o (pci_req_oe),
-
- .pci_gnt_i (pci_gnt_pad_i),
-
- // protocol pins
- .pci_frame_i (pci_frame_i),
- .pci_frame_o (pci_frame_o),
-
- .pci_frame_oe_o (pci_frame_oe),
- .pci_irdy_oe_o (pci_irdy_oe),
- .pci_devsel_oe_o(pci_devsel_oe),
- .pci_trdy_oe_o (pci_trdy_oe),
- .pci_stop_oe_o (pci_stop_oe),
- .pci_ad_oe_o (pci_ad_oe),
- .pci_cbe_oe_o (pci_cbe_oe),
-
- .pci_irdy_i (pci_irdy_i),
- .pci_irdy_o (pci_irdy_o),
-
- .pci_idsel_i (pci_idsel_pad_i),
-
- .pci_devsel_i (pci_devsel_i),
- .pci_devsel_o (pci_devsel_o),
-
- .pci_trdy_i (pci_trdy_i),
- .pci_trdy_o (pci_trdy_o),
-
- .pci_stop_i (pci_stop_i),
- .pci_stop_o (pci_stop_o),
-
- // data transfer pins
- .pci_ad_i (pci_ad_i),
- .pci_ad_o (pci_ad_o),
-
- .pci_cbe_i (pci_cbe_i),
- .pci_cbe_o (pci_cbe_o),
-
- // parity generation and checking pins
- .pci_par_i (pci_par_i),
- .pci_par_o (pci_par_o),
- .pci_par_oe_o (pci_par_oe),
-
- .pci_perr_i (pci_perr_i),
- .pci_perr_o (pci_perr_o),
- .pci_perr_oe_o (pci_perr_oe),
-
- // system error pin
- .pci_serr_o (pci_serr_o),
- .pci_serr_oe_o (pci_serr_oe)
-);
-endmodule // pci_test_top
trunk/apps/test/rtl/verilog/pci_test_top_1clk.v~
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/apps/test/syn/synplify/pci_test_top.sdc~
===================================================================
--- trunk/apps/test/syn/synplify/pci_test_top.sdc~ (revision 97)
+++ trunk/apps/test/syn/synplify/pci_test_top.sdc~ (nonexistent)
@@ -1,246 +0,0 @@
-# Synplicity, Inc. constraint file
-# /shared/projects/pci/mihad/pci/apps/test/syn/synplify/pci_test_top.sdc
-# Written on Fri Apr 4 20:00:42 2003
-# by Amplify, Amplify 3.1 Scope Editor
-
-#
-# Clocks
-#
-define_clock -name {pci_clk_pad_i} -period 30.000 -clockgroup pci_clkgrp
-define_clock -name {i_clkdll.CLKDV} -period 20.000 -clockgroup clk_clkgrp
-
-#
-# Inputs/Outputs
-#
-define_input_delay {pci_devsel_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_trdy_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_stop_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_idsel_pad_i} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_frame_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_irdy_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_gnt_pad_i} 20.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_par_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_perr_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad0_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad1_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad2_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad3_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad4_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad5_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad6_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad7_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad8_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad9_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad10_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad11_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad12_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad13_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad14_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad15_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad16_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad17_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad18_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad19_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad20_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad21_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad22_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad23_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad24_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad25_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad26_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad27_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad28_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad29_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad30_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad31_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_cbe0_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_cbe1_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_cbe2_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_cbe3_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad0_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad1_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad2_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad3_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad4_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad5_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad6_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad7_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad8_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad9_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad10_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad11_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad12_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad13_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad14_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad15_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad16_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad17_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad18_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad19_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad20_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad21_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad22_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad23_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad24_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad25_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad26_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad27_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad28_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad29_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad30_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad31_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_cbe0_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_cbe1_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_cbe2_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_cbe3_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_devsel_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_trdy_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_stop_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_frame_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_irdy_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_req_pad_o} 18.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_par_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_perr_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_serr_pad_o} 19.00 -ref pci_clk_pad_i:r
-
-#
-# Registers
-#
-define_reg_output_delay {*sync_data_out*} -route 10.00
-
-#
-# Multicycle Path
-#
-
-#
-# False Path
-#
-
-#
-# Attributes
-#
-define_attribute {pci_clk_pad_i} xc_loc {P185}
-define_attribute {pci_rst_pad_i} xc_loc {P199}
-define_attribute {pci_gnt_pad_i} xc_loc {P200}
-define_attribute {pci_req_pad_o} xc_loc {P201}
-define_attribute {pci_ad31_pad_io} xc_loc {P203}
-define_attribute {pci_ad30_pad_io} xc_loc {P204}
-define_attribute {pci_ad29_pad_io} xc_loc {P205}
-define_attribute {pci_ad28_pad_io} xc_loc {P206}
-define_attribute {pci_ad27_pad_io} xc_loc {P3}
-define_attribute {pci_ad26_pad_io} xc_loc {P4}
-define_attribute {pci_ad25_pad_io} xc_loc {P5}
-define_attribute {pci_ad24_pad_io} xc_loc {P6}
-define_attribute {pci_cbe3_pad_io} xc_loc {P8}
-define_attribute {pci_idsel_pad_i} xc_loc {P9}
-define_attribute {pci_ad23_pad_io} xc_loc {P10}
-define_attribute {pci_ad22_pad_io} xc_loc {P14}
-define_attribute {pci_ad21_pad_io} xc_loc {P15}
-define_attribute {pci_ad20_pad_io} xc_loc {P16}
-define_attribute {pci_ad19_pad_io} xc_loc {P17}
-define_attribute {pci_ad18_pad_io} xc_loc {P18}
-define_attribute {pci_ad17_pad_io} xc_loc {P20}
-define_attribute {pci_ad16_pad_io} xc_loc {P21}
-define_attribute {pci_cbe2_pad_io} xc_loc {P22}
-define_attribute {pci_frame_pad_io} xc_loc {P23}
-define_attribute {pci_irdy_pad_io} xc_loc {P24}
-define_attribute {pci_trdy_pad_io} xc_loc {P27}
-define_attribute {pci_devsel_pad_io} xc_loc {P29}
-define_attribute {pci_stop_pad_io} xc_loc {P30}
-define_attribute {pci_perr_pad_io} xc_loc {P31}
-define_attribute {pci_serr_pad_o} xc_loc {P33}
-define_attribute {pci_par_pad_io} xc_loc {P34}
-define_attribute {pci_cbe1_pad_io} xc_loc {P35}
-define_attribute {pci_ad15_pad_io} xc_loc {P36}
-define_attribute {pci_ad14_pad_io} xc_loc {P37}
-define_attribute {pci_ad13_pad_io} xc_loc {P41}
-define_attribute {pci_ad12_pad_io} xc_loc {P42}
-define_attribute {pci_ad11_pad_io} xc_loc {P43}
-define_attribute {pci_ad10_pad_io} xc_loc {P45}
-define_attribute {pci_ad9_pad_io} xc_loc {P46}
-define_attribute {pci_ad8_pad_io} xc_loc {P47}
-define_attribute {pci_cbe0_pad_io} xc_loc {P48}
-define_attribute {pci_ad7_pad_io} xc_loc {P49}
-define_attribute {pci_ad6_pad_io} xc_loc {P57}
-define_attribute {pci_ad5_pad_io} xc_loc {P58}
-define_attribute {pci_ad4_pad_io} xc_loc {P59}
-define_attribute {pci_ad3_pad_io} xc_loc {P61}
-define_attribute {pci_ad2_pad_io} xc_loc {P62}
-define_attribute {pci_ad1_pad_io} xc_loc {P63}
-define_attribute {pci_ad0_pad_io} xc_loc {P67}
-define_attribute {clk_pad_i} xc_loc {P182}
-define_global_attribute syn_useioff {1}
-define_attribute {v:work.pci_cbe_en_crit} syn_hier {hard}
-define_attribute {v:work.pci_frame_crit} syn_hier {hard}
-define_attribute {v:work.pci_frame_en_crit} syn_hier {hard}
-define_attribute {v:work.pci_frame_load_crit} syn_hier {hard}
-define_attribute {v:work.pci_irdy_out_crit} syn_hier {hard}
-define_attribute {v:work.pci_mas_ad_en_crit} syn_hier {hard}
-define_attribute {v:work.pci_mas_ad_load_crit} syn_hier {hard}
-define_attribute {v:work.pci_mas_ch_state_crit} syn_hier {hard}
-define_attribute {v:work.pci_par_crit} syn_hier {hard}
-define_attribute {v:work.pci_io_mux_ad_en_crit} syn_hier {hard}
-define_attribute {v:work.pci_io_mux_ad_load_crit} syn_hier {hard}
-define_attribute {v:work.pci_target32_clk_en} syn_hier {hard}
-define_attribute {v:work.pci_target32_devs_crit} syn_hier {hard}
-define_attribute {v:work.pci_target32_stop_crit} syn_hier {hard}
-define_attribute {v:work.pci_target32_trdy_crit} syn_hier {hard}
-define_attribute {v:work.pci_perr_crit} syn_hier {hard}
-define_attribute {v:work.pci_perr_en_crit} syn_hier {hard}
-define_attribute {v:work.pci_serr_crit} syn_hier {hard}
-define_attribute {v:work.pci_serr_en_crit} syn_hier {hard}
-define_attribute {pci_gnt_pad_i} xc_padtype {IBUF_PCI33_5}
-define_attribute {pci_req_pad_o} xc_padtype {OBUFT_PCI33_5}
-define_attribute {pci_ad31_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad30_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad29_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad28_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad27_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad26_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad25_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad24_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_cbe3_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_idsel_pad_i} xc_padtype {IBUF_PCI33_5}
-define_attribute {pci_ad23_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad22_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad21_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad20_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad19_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad18_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad17_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad16_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_cbe2_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_frame_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_irdy_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_trdy_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_devsel_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_stop_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_perr_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_serr_pad_o} xc_padtype {OBUFT_PCI33_5}
-define_attribute {pci_par_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_cbe1_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad15_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad14_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad13_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad12_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad11_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad10_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad9_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad8_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_cbe0_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad7_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad6_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad5_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad4_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad3_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad2_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad1_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad0_pad_io} xc_padtype {IOBUF_PCI33_5}
-
-#
-# Other Constraints
-#
-
-#
-# Order of waveforms
-#
Index: trunk/apps/test/syn/synplify/pci_test_top.prj~
===================================================================
--- trunk/apps/test/syn/synplify/pci_test_top.prj~ (revision 97)
+++ trunk/apps/test/syn/synplify/pci_test_top.prj~ (nonexistent)
@@ -1,122 +0,0 @@
-#-- Synplicity, Inc.
-#-- Version Amplify 3.1
-#-- Project file /shared/projects/pci/mihad/pci/apps/test/syn/synplify/pci_test_top.prj
-#-- Written on Thu Apr 10 12:03:11 2003
-
-
-#add_file options
-add_file -verilog "$LIB/xilinx/virtex.v"
-add_file -verilog "../../../../rtl/verilog/meta_flop.v"
-add_file -verilog "../../../../rtl/verilog/pci_async_reset_flop.v"
-add_file -verilog "../../../../rtl/verilog/pci_bridge32.v"
-add_file -verilog "../../../../rtl/verilog/pci_cbe_en_crit.v"
-add_file -verilog "../../../../rtl/verilog/pci_conf_cyc_addr_dec.v"
-add_file -verilog "../../../../rtl/verilog/pci_conf_space.v"
-add_file -verilog "../../../../rtl/verilog/pci_cur_out_reg.v"
-add_file -verilog "../../../../rtl/verilog/pci_delayed_sync.v"
-add_file -verilog "../../../../rtl/verilog/pci_delayed_write_reg.v"
-add_file -verilog "../../../../rtl/verilog/pci_frame_crit.v"
-add_file -verilog "../../../../rtl/verilog/pci_frame_en_crit.v"
-add_file -verilog "../../../../rtl/verilog/pci_frame_load_crit.v"
-add_file -verilog "../../../../rtl/verilog/pci_in_reg.v"
-add_file -verilog "../../../../rtl/verilog/pci_io_mux_ad_en_crit.v"
-add_file -verilog "../../../../rtl/verilog/pci_io_mux_ad_load_crit.v"
-add_file -verilog "../../../../rtl/verilog/pci_io_mux.v"
-add_file -verilog "../../../../rtl/verilog/pci_irdy_out_crit.v"
-add_file -verilog "../../../../rtl/verilog/pci_mas_ad_en_crit.v"
-add_file -verilog "../../../../rtl/verilog/pci_mas_ad_load_crit.v"
-add_file -verilog "../../../../rtl/verilog/pci_mas_ch_state_crit.v"
-add_file -verilog "../../../../rtl/verilog/pci_master32_sm_if.v"
-add_file -verilog "../../../../rtl/verilog/pci_master32_sm.v"
-add_file -verilog "../../../../rtl/verilog/pci_out_reg.v"
-add_file -verilog "../../../../rtl/verilog/pci_par_crit.v"
-add_file -verilog "../../../../rtl/verilog/pci_parity_check.v"
-add_file -verilog "../../../../rtl/verilog/pci_pci_decoder.v"
-add_file -verilog "../../../../rtl/verilog/pci_pcir_fifo_control.v"
-add_file -verilog "../../../../rtl/verilog/pci_pci_tpram.v"
-add_file -verilog "../../../../rtl/verilog/pci_pciw_fifo_control.v"
-add_file -verilog "../../../../rtl/verilog/pci_pciw_pcir_fifos.v"
-add_file -verilog "../../../../rtl/verilog/pci_perr_crit.v"
-add_file -verilog "../../../../rtl/verilog/pci_perr_en_crit.v"
-add_file -verilog "../../../../rtl/verilog/pci_ram_16x40d.v"
-add_file -verilog "../../../../rtl/verilog/pci_rst_int.v"
-add_file -verilog "../../../../rtl/verilog/pci_serr_crit.v"
-add_file -verilog "../../../../rtl/verilog/pci_serr_en_crit.v"
-add_file -verilog "../../../../rtl/verilog/pci_sync_module.v"
-add_file -verilog "../../../../rtl/verilog/pci_target32_clk_en.v"
-add_file -verilog "../../../../rtl/verilog/pci_target32_devs_crit.v"
-add_file -verilog "../../../../rtl/verilog/pci_target32_interface.v"
-add_file -verilog "../../../../rtl/verilog/pci_target32_sm.v"
-add_file -verilog "../../../../rtl/verilog/pci_target32_stop_crit.v"
-add_file -verilog "../../../../rtl/verilog/pci_target32_trdy_crit.v"
-add_file -verilog "../../../../rtl/verilog/pci_target_unit.v"
-add_file -verilog "../../../../rtl/verilog/pci_wb_addr_mux.v"
-add_file -verilog "../../../../rtl/verilog/pci_wb_decoder.v"
-add_file -verilog "../../../../rtl/verilog/pci_wb_master.v"
-add_file -verilog "../../../../rtl/verilog/pci_wbr_fifo_control.v"
-add_file -verilog "../../../../rtl/verilog/pci_wb_slave_unit.v"
-add_file -verilog "../../../../rtl/verilog/pci_wb_slave.v"
-add_file -verilog "../../../../rtl/verilog/pci_wb_tpram.v"
-add_file -verilog "../../../../rtl/verilog/pci_wbw_fifo_control.v"
-add_file -verilog "../../../../rtl/verilog/pci_wbw_wbr_fifos.v"
-add_file -verilog "../../../../rtl/verilog/synchronizer_flop.v"
-add_file -verilog "../../rtl/verilog/test.v"
-add_file -verilog "../../rtl/verilog/pci_test_top_1clk.v"
-add_file -constraint "pci_test_top_1clk.sdc"
-
-#reporting options
-
-
-#implementation: "rev_1"
-impl -add rev_1
-
-#device options
-set_option -technology SPARTAN2
-set_option -part XC2S150
-set_option -package PQ208
-set_option -speed_grade -5
-
-#compilation/mapping options
-set_option -default_enum_encoding default
-set_option -symbolic_fsm_compiler 0
-set_option -resource_sharing 1
-set_option -use_fsm_explorer 0
-
-#map options
-set_option -frequency 50.000
-set_option -fanout_limit 16
-set_option -disable_io_insertion 0
-set_option -pipe 0
-set_option -fixgatedclocks 0
-set_option -retiming 0
-set_option -modular 0
-
-#simulation options
-set_option -write_verilog 0
-set_option -write_vhdl 0
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#set result format/file last
-project -result_file "rev_1/pci_test_top.edf"
-
-#implementation attributes
-set_option -vlog_std v2001
-set_option -compiler_compatible 0
-set_option -random_floorplan 0
-set_option -update_models_cp 0
-set_option -verification_mode 0
-set_option -include_path "../../rtl/verilog/;../../../../rtl/verilog/"
-
-#netlist optimizer options
-set_option -enable_nfilter 0
-set_option -feedthrough 1
-set_option -constant_prop 1
-set_option -level_hierarchy 0
-
-#physical constraint options
-set_option -floorplan ""
-set_option -nfilter_user_path ""
-set_option -pin_assignment ""
-impl -active "rev_1"
trunk/apps/test/syn/synplify/pci_test_top.prj~
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/apps/test/syn/synplify/pci_test_top_1clk.sdc~
===================================================================
--- trunk/apps/test/syn/synplify/pci_test_top_1clk.sdc~ (revision 97)
+++ trunk/apps/test/syn/synplify/pci_test_top_1clk.sdc~ (nonexistent)
@@ -1,254 +0,0 @@
-# Synplicity, Inc. constraint file
-# /shared/projects/pci/mihad/pci/apps/test/syn/synplify/pci_test_top.sdc
-# Written on Thu Apr 17 16:11:16 2003
-# by Amplify, Amplify 3.1 Scope Editor
-
-#
-# Clocks
-#
-define_clock -name {pci_clk_pad_i} -period 30.000 -clockgroup pci_clkgrp
-define_clock -name {i_bufg_wb_clk} -period 20.000 -clockgroup clk_clkgrp
-
-#
-# Inputs/Outputs
-#
-define_input_delay {pci_devsel_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_trdy_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_stop_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_idsel_pad_i} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_frame_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_irdy_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_gnt_pad_i} 20.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_par_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_perr_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad0_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad1_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad2_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad3_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad4_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad5_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad6_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad7_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad8_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad9_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad10_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad11_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad12_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad13_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad14_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad15_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad16_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad17_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad18_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad19_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad20_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad21_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad22_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad23_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad24_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad25_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad26_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad27_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad28_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad29_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad30_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad31_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_cbe0_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_cbe1_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_cbe2_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_cbe3_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad0_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad1_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad2_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad3_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad4_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad5_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad6_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad7_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad8_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad9_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad10_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad11_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad12_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad13_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad14_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad15_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad16_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad17_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad18_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad19_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad20_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad21_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad22_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad23_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad24_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad25_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad26_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad27_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad28_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad29_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad30_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad31_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_cbe0_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_cbe1_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_cbe2_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_cbe3_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_devsel_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_trdy_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_stop_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_frame_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_irdy_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_req_pad_o} 18.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_par_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_perr_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_serr_pad_o} 19.00 -ref pci_clk_pad_i:r
-
-#
-# Registers
-#
-define_reg_output_delay {*sync_data_out*} -route 10.00
-
-#
-# Multicycle Path
-#
-
-#
-# False Path
-#
-
-#
-# Attributes
-#
-define_attribute {pci_clk_pad_i} xc_loc {P185}
-define_attribute {pci_rst_pad_i} xc_loc {P199}
-define_attribute {pci_gnt_pad_i} xc_loc {P200}
-define_attribute {pci_req_pad_o} xc_loc {P201}
-define_attribute {pci_ad31_pad_io} xc_loc {P203}
-define_attribute {pci_ad30_pad_io} xc_loc {P204}
-define_attribute {pci_ad29_pad_io} xc_loc {P205}
-define_attribute {pci_ad28_pad_io} xc_loc {P206}
-define_attribute {pci_ad27_pad_io} xc_loc {P3}
-define_attribute {pci_ad26_pad_io} xc_loc {P4}
-define_attribute {pci_ad25_pad_io} xc_loc {P5}
-define_attribute {pci_ad24_pad_io} xc_loc {P6}
-define_attribute {pci_cbe3_pad_io} xc_loc {P8}
-define_attribute {pci_idsel_pad_i} xc_loc {P9}
-define_attribute {pci_ad23_pad_io} xc_loc {P10}
-define_attribute {pci_ad22_pad_io} xc_loc {P14}
-define_attribute {pci_ad21_pad_io} xc_loc {P15}
-define_attribute {pci_ad20_pad_io} xc_loc {P16}
-define_attribute {pci_ad19_pad_io} xc_loc {P17}
-define_attribute {pci_ad18_pad_io} xc_loc {P18}
-define_attribute {pci_ad17_pad_io} xc_loc {P20}
-define_attribute {pci_ad16_pad_io} xc_loc {P21}
-define_attribute {pci_cbe2_pad_io} xc_loc {P22}
-define_attribute {pci_frame_pad_io} xc_loc {P23}
-define_attribute {pci_irdy_pad_io} xc_loc {P24}
-define_attribute {pci_trdy_pad_io} xc_loc {P27}
-define_attribute {pci_devsel_pad_io} xc_loc {P29}
-define_attribute {pci_stop_pad_io} xc_loc {P30}
-define_attribute {pci_perr_pad_io} xc_loc {P31}
-define_attribute {pci_serr_pad_o} xc_loc {P33}
-define_attribute {pci_par_pad_io} xc_loc {P34}
-define_attribute {pci_cbe1_pad_io} xc_loc {P35}
-define_attribute {pci_ad15_pad_io} xc_loc {P36}
-define_attribute {pci_ad14_pad_io} xc_loc {P37}
-define_attribute {pci_ad13_pad_io} xc_loc {P41}
-define_attribute {pci_ad12_pad_io} xc_loc {P42}
-define_attribute {pci_ad11_pad_io} xc_loc {P43}
-define_attribute {pci_ad10_pad_io} xc_loc {P45}
-define_attribute {pci_ad9_pad_io} xc_loc {P46}
-define_attribute {pci_ad8_pad_io} xc_loc {P47}
-define_attribute {pci_cbe0_pad_io} xc_loc {P48}
-define_attribute {pci_ad7_pad_io} xc_loc {P49}
-define_attribute {pci_ad6_pad_io} xc_loc {P57}
-define_attribute {pci_ad5_pad_io} xc_loc {P58}
-define_attribute {pci_ad4_pad_io} xc_loc {P59}
-define_attribute {pci_ad3_pad_io} xc_loc {P61}
-define_attribute {pci_ad2_pad_io} xc_loc {P62}
-define_attribute {pci_ad1_pad_io} xc_loc {P63}
-define_attribute {pci_ad0_pad_io} xc_loc {P67}
-define_attribute {clk_pad_i} xc_loc {P182}
-define_global_attribute syn_useioff {1}
-define_attribute {v:work.pci_cbe_en_crit} syn_hier {hard}
-define_attribute {v:work.pci_frame_crit} syn_hier {hard}
-define_attribute {v:work.pci_frame_en_crit} syn_hier {hard}
-define_attribute {v:work.pci_frame_load_crit} syn_hier {hard}
-define_attribute {v:work.pci_irdy_out_crit} syn_hier {hard}
-define_attribute {v:work.pci_mas_ad_en_crit} syn_hier {hard}
-define_attribute {v:work.pci_mas_ad_load_crit} syn_hier {hard}
-define_attribute {v:work.pci_mas_ch_state_crit} syn_hier {hard}
-define_attribute {v:work.pci_par_crit} syn_hier {hard}
-define_attribute {v:work.pci_io_mux_ad_en_crit} syn_hier {hard}
-define_attribute {v:work.pci_io_mux_ad_load_crit} syn_hier {hard}
-define_attribute {v:work.pci_target32_clk_en} syn_hier {hard}
-define_attribute {v:work.pci_target32_devs_crit} syn_hier {hard}
-define_attribute {v:work.pci_target32_stop_crit} syn_hier {hard}
-define_attribute {v:work.pci_target32_trdy_crit} syn_hier {hard}
-define_attribute {v:work.pci_perr_crit} syn_hier {hard}
-define_attribute {v:work.pci_perr_en_crit} syn_hier {hard}
-define_attribute {v:work.pci_serr_crit} syn_hier {hard}
-define_attribute {v:work.pci_serr_en_crit} syn_hier {hard}
-define_attribute {pci_gnt_pad_i} xc_padtype {IBUF_PCI33_5}
-define_attribute {pci_req_pad_o} xc_padtype {OBUFT_PCI33_5}
-define_attribute {pci_ad31_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad30_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad29_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad28_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad27_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad26_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad25_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad24_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_cbe3_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_idsel_pad_i} xc_padtype {IBUF_PCI33_5}
-define_attribute {pci_ad23_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad22_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad21_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad20_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad19_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad18_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad17_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad16_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_cbe2_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_frame_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_irdy_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_trdy_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_devsel_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_stop_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_perr_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_serr_pad_o} xc_padtype {OBUFT_PCI33_5}
-define_attribute {pci_par_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_cbe1_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad15_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad14_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad13_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad12_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad11_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad10_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad9_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad8_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_cbe0_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad7_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad6_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad5_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad4_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad3_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad2_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad1_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad0_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {v:work.synchronizer_flop_1_0} syn_hier {hard}
-define_attribute {v:work.synchronizer_flop_3_0} syn_hier {hard}
-define_attribute {v:work.synchronizer_flop_4_0} syn_hier {hard}
-define_attribute {v:work.synchronizer_flop_4_1} syn_hier {hard}
-define_attribute {v:work.synchronizer_flop_4_3} syn_hier {hard}
-define_attribute {v:work.synchronizer_flop_6_0} syn_hier {hard}
-define_attribute {v:work.synchronizer_flop_7_0} syn_hier {hard}
-define_attribute {v:work.synchronizer_flop_7_3} syn_hier {hard}
-
-#
-# Other Constraints
-#
-
-#
-# Order of waveforms
-#
Index: trunk/apps/test/syn/synplify/pci_test_top_2clks.sdc~
===================================================================
--- trunk/apps/test/syn/synplify/pci_test_top_2clks.sdc~ (revision 97)
+++ trunk/apps/test/syn/synplify/pci_test_top_2clks.sdc~ (nonexistent)
@@ -1,254 +0,0 @@
-# Synplicity, Inc. constraint file
-# /shared/projects/pci/mihad/pci/apps/test/syn/synplify/pci_test_top.sdc
-# Written on Thu Apr 17 16:11:16 2003
-# by Amplify, Amplify 3.1 Scope Editor
-
-#
-# Clocks
-#
-define_clock -name {pci_clk_pad_i} -period 30.000 -clockgroup pci_clkgrp
-define_clock -name {i_bufg_wb_clk} -period 20.000 -clockgroup clk_clkgrp
-
-#
-# Inputs/Outputs
-#
-define_input_delay {pci_devsel_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_trdy_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_stop_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_idsel_pad_i} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_frame_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_irdy_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_gnt_pad_i} 20.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_par_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_perr_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad0_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad1_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad2_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad3_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad4_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad5_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad6_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad7_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad8_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad9_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad10_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad11_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad12_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad13_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad14_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad15_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad16_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad17_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad18_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad19_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad20_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad21_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad22_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad23_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad24_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad25_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad26_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad27_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad28_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad29_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad30_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_ad31_pad_io} 23.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_cbe0_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_cbe1_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_cbe2_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_input_delay {pci_cbe3_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad0_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad1_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad2_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad3_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad4_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad5_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad6_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad7_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad8_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad9_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad10_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad11_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad12_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad13_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad14_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad15_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad16_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad17_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad18_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad19_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad20_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad21_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad22_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad23_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad24_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad25_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad26_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad27_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad28_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad29_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad30_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_ad31_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_cbe0_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_cbe1_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_cbe2_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_cbe3_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_devsel_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_trdy_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_stop_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_frame_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_irdy_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_req_pad_o} 18.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_par_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_perr_pad_io} 19.00 -ref pci_clk_pad_i:r
-define_output_delay {pci_serr_pad_o} 19.00 -ref pci_clk_pad_i:r
-
-#
-# Registers
-#
-define_reg_output_delay {*sync_data_out*} -route 10.00
-
-#
-# Multicycle Path
-#
-
-#
-# False Path
-#
-
-#
-# Attributes
-#
-define_attribute {pci_clk_pad_i} xc_loc {P185}
-define_attribute {pci_rst_pad_i} xc_loc {P199}
-define_attribute {pci_gnt_pad_i} xc_loc {P200}
-define_attribute {pci_req_pad_o} xc_loc {P201}
-define_attribute {pci_ad31_pad_io} xc_loc {P203}
-define_attribute {pci_ad30_pad_io} xc_loc {P204}
-define_attribute {pci_ad29_pad_io} xc_loc {P205}
-define_attribute {pci_ad28_pad_io} xc_loc {P206}
-define_attribute {pci_ad27_pad_io} xc_loc {P3}
-define_attribute {pci_ad26_pad_io} xc_loc {P4}
-define_attribute {pci_ad25_pad_io} xc_loc {P5}
-define_attribute {pci_ad24_pad_io} xc_loc {P6}
-define_attribute {pci_cbe3_pad_io} xc_loc {P8}
-define_attribute {pci_idsel_pad_i} xc_loc {P9}
-define_attribute {pci_ad23_pad_io} xc_loc {P10}
-define_attribute {pci_ad22_pad_io} xc_loc {P14}
-define_attribute {pci_ad21_pad_io} xc_loc {P15}
-define_attribute {pci_ad20_pad_io} xc_loc {P16}
-define_attribute {pci_ad19_pad_io} xc_loc {P17}
-define_attribute {pci_ad18_pad_io} xc_loc {P18}
-define_attribute {pci_ad17_pad_io} xc_loc {P20}
-define_attribute {pci_ad16_pad_io} xc_loc {P21}
-define_attribute {pci_cbe2_pad_io} xc_loc {P22}
-define_attribute {pci_frame_pad_io} xc_loc {P23}
-define_attribute {pci_irdy_pad_io} xc_loc {P24}
-define_attribute {pci_trdy_pad_io} xc_loc {P27}
-define_attribute {pci_devsel_pad_io} xc_loc {P29}
-define_attribute {pci_stop_pad_io} xc_loc {P30}
-define_attribute {pci_perr_pad_io} xc_loc {P31}
-define_attribute {pci_serr_pad_o} xc_loc {P33}
-define_attribute {pci_par_pad_io} xc_loc {P34}
-define_attribute {pci_cbe1_pad_io} xc_loc {P35}
-define_attribute {pci_ad15_pad_io} xc_loc {P36}
-define_attribute {pci_ad14_pad_io} xc_loc {P37}
-define_attribute {pci_ad13_pad_io} xc_loc {P41}
-define_attribute {pci_ad12_pad_io} xc_loc {P42}
-define_attribute {pci_ad11_pad_io} xc_loc {P43}
-define_attribute {pci_ad10_pad_io} xc_loc {P45}
-define_attribute {pci_ad9_pad_io} xc_loc {P46}
-define_attribute {pci_ad8_pad_io} xc_loc {P47}
-define_attribute {pci_cbe0_pad_io} xc_loc {P48}
-define_attribute {pci_ad7_pad_io} xc_loc {P49}
-define_attribute {pci_ad6_pad_io} xc_loc {P57}
-define_attribute {pci_ad5_pad_io} xc_loc {P58}
-define_attribute {pci_ad4_pad_io} xc_loc {P59}
-define_attribute {pci_ad3_pad_io} xc_loc {P61}
-define_attribute {pci_ad2_pad_io} xc_loc {P62}
-define_attribute {pci_ad1_pad_io} xc_loc {P63}
-define_attribute {pci_ad0_pad_io} xc_loc {P67}
-define_attribute {clk_pad_i} xc_loc {P182}
-define_global_attribute syn_useioff {1}
-define_attribute {v:work.pci_cbe_en_crit} syn_hier {hard}
-define_attribute {v:work.pci_frame_crit} syn_hier {hard}
-define_attribute {v:work.pci_frame_en_crit} syn_hier {hard}
-define_attribute {v:work.pci_frame_load_crit} syn_hier {hard}
-define_attribute {v:work.pci_irdy_out_crit} syn_hier {hard}
-define_attribute {v:work.pci_mas_ad_en_crit} syn_hier {hard}
-define_attribute {v:work.pci_mas_ad_load_crit} syn_hier {hard}
-define_attribute {v:work.pci_mas_ch_state_crit} syn_hier {hard}
-define_attribute {v:work.pci_par_crit} syn_hier {hard}
-define_attribute {v:work.pci_io_mux_ad_en_crit} syn_hier {hard}
-define_attribute {v:work.pci_io_mux_ad_load_crit} syn_hier {hard}
-define_attribute {v:work.pci_target32_clk_en} syn_hier {hard}
-define_attribute {v:work.pci_target32_devs_crit} syn_hier {hard}
-define_attribute {v:work.pci_target32_stop_crit} syn_hier {hard}
-define_attribute {v:work.pci_target32_trdy_crit} syn_hier {hard}
-define_attribute {v:work.pci_perr_crit} syn_hier {hard}
-define_attribute {v:work.pci_perr_en_crit} syn_hier {hard}
-define_attribute {v:work.pci_serr_crit} syn_hier {hard}
-define_attribute {v:work.pci_serr_en_crit} syn_hier {hard}
-define_attribute {pci_gnt_pad_i} xc_padtype {IBUF_PCI33_5}
-define_attribute {pci_req_pad_o} xc_padtype {OBUFT_PCI33_5}
-define_attribute {pci_ad31_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad30_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad29_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad28_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad27_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad26_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad25_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad24_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_cbe3_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_idsel_pad_i} xc_padtype {IBUF_PCI33_5}
-define_attribute {pci_ad23_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad22_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad21_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad20_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad19_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad18_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad17_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad16_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_cbe2_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_frame_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_irdy_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_trdy_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_devsel_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_stop_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_perr_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_serr_pad_o} xc_padtype {OBUFT_PCI33_5}
-define_attribute {pci_par_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_cbe1_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad15_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad14_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad13_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad12_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad11_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad10_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad9_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad8_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_cbe0_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad7_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad6_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad5_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad4_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad3_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad2_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad1_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {pci_ad0_pad_io} xc_padtype {IOBUF_PCI33_5}
-define_attribute {v:work.synchronizer_flop_1_0} syn_hier {hard}
-define_attribute {v:work.synchronizer_flop_3_0} syn_hier {hard}
-define_attribute {v:work.synchronizer_flop_4_0} syn_hier {hard}
-define_attribute {v:work.synchronizer_flop_4_1} syn_hier {hard}
-define_attribute {v:work.synchronizer_flop_4_3} syn_hier {hard}
-define_attribute {v:work.synchronizer_flop_6_0} syn_hier {hard}
-define_attribute {v:work.synchronizer_flop_7_0} syn_hier {hard}
-define_attribute {v:work.synchronizer_flop_7_3} syn_hier {hard}
-
-#
-# Other Constraints
-#
-
-#
-# Order of waveforms
-#