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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

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Rev 97 → Rev 98

/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
1,18 → 1,3
versatile_library.v:
async_fifo_dw_simplex_actel.v:
svn export http://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk/rtl/verilog/async_fifo_dw_simplex_actel.v
 
VERSATILE_COUNTER_PROJECT_FILES =versatile_counter_generator.php
VERSATILE_COUNTER_PROJECT_FILES +=CSV.class.php
 
versatile_counter_generator.php:
svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/ $(VERSATILE_COUNTER_PROJECT_FILES)
 
ref_counter.v: versatile_counter_generator.php
excel2csv ref_counter.xls -S ,
./versatile_counter_generator.php ref_counter.csv > ref_counter.v
 
sdr_sdram_16_ctrl_actel.v:
vppreproc --noline --noblank +define+RFR_LENGTH+10 +define+RFR_WRAP_VALUE+1001 +define+ACTEL sdr_sdram_16_ctrl.v > sdr_sdram_16_ctrl_actel.v
 
/versatile_mem_ctrl/trunk/rtl/verilog/wbwb_bridge.v
44,7 → 44,6
parameter wbm_adr0 = 2'b00;
parameter wbm_adr1 = 2'b01;
parameter wbm_data = 2'b10;
parameter wbm_wait = 2'b11;
 
reg wbs_we_reg;
reg [1:0] wbs_bte_reg;
117,7 → 116,6
else
{wbs_we_reg,wbs_bte_reg} <= {wbs_we_i,wbs_bte_i};
 
// wbm FIFO
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
always @ (posedge wbm_clk or posedge wbm_rst)
133,14 → 131,12
if (wbm_rst)
wbm <= wbm_adr0;
else
casex ({wbm,b_fifo_empty,wbm_we_o,wbm_ack_i,wbm_eoc}) // ,b_q[`WE]
{wbm_adr0,1'b0,1'bx,1'bx,1'bx} : wbm <= wbm_adr1; // if write wait for !fifo_empty
{wbm_adr1,1'b0,1'b1,1'bx,1'bx} : wbm <= wbm_data; // if write wait for !fifo_empty
{wbm_adr1,1'bx,1'b0,1'bx,1'bx} : wbm <= wbm_data; // if read go ahead
{wbm_data,1'bx,1'bx,1'b1,1'b1} : wbm <= wbm_adr0; //
{wbm_wait,1'bx,1'bx,1'bx,1'bx} : wbm <= wbm_adr0;
default : wbm <= wbm;
endcase
if ((wbm==wbm_adr0 & !b_fifo_empty) |
(wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
(wbm==wbm_adr1 & !wbm_we_o) |
(wbm==wbm_data & wbm_ack_i & wbm_eoc))
wbm <= {wbm[0],!(wbm[1] ^ wbm[0])}; // count sequence 00,01,10
 
assign b_d = {wbm_dat_i,4'b1111};
assign b_wr = !wbm_we_o & wbm_ack_i;
assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty);
176,7 → 172,6
else if (wbm_eoc_alert & wbm_ack_i)
wbm_cti_o <= endofburst;
end
//assign {wbm_dat_o,wbm_sel_o} = b_q;
 
//async_fifo_dw_simplex_top
vl_fifo_2r2w_async_simplex
/versatile_mem_ctrl/trunk/rtl/verilog/sdr_sdram_16_ctrl.v
1,6 → 1,6
`timescale 1ns/1ns
//`sinclude "type_definitions.struct"
`include "sdr_16_defines.v"
//`include "sdr_16_defines.v"
`ifdef ACTEL
`define SYN /*synthesis syn_useioff=1 syn_allow_retiming=0 */
`else
7,78 → 7,89
`define SYN
`endif
module sdr_sdram_16_ctrl (
// wisbone i/f
dat_i, adr_i, sel_i, cti_i, bte_i, we_i, cyc_i, stb_i, dat_o, ack_o,
// SDR SDRAM
ba, a, cmd, cke, cs_n, dqm, dq_i, dq_o, dq_oe,
// system
clk, rst);
// wisbone i/f
dat_i, adr_i, sel_i, cti_i, bte_i, we_i, cyc_i, stb_i, dat_o, ack_o,
// SDR SDRAM
ba, a, cmd, cke, cs_n, dqm, dq_i, dq_o, dq_oe,
// system
clk, rst);
 
parameter ba_size = 2;
parameter row_size = 13;
parameter col_size = 9;
parameter cl = 2;
 
// LMR
// [12:10] reserved
// [9] WB, write burst; 0 - programmed burst length, 1 - single location
// [8:7] OP Mode, 2'b00
// [6:4] CAS Latency; 3'b010 - 2, 3'b011 - 3
// [3] BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
// [2:0] Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
parameter init_wb = 1'b0;
parameter init_cl = 3'b010;
parameter init_bt = 1'b0;
parameter init_bl = 3'b001;
input [31:0] dat_i;
input [ba_size+col_size+row_size:1] adr_i;
input [3:0] sel_i;
input [2:0] cti_i;
input [1:0] bte_i;
input we_i, cyc_i, stb_i;
output reg [31:0] dat_o;
output ack_o;
input [31:0] dat_i;
input [ba_size+col_size+row_size:1] adr_i;
input [3:0] sel_i;
input [2:0] cti_i;
input [1:0] bte_i;
input we_i, cyc_i, stb_i;
output reg [31:0] dat_o;
output ack_o;
 
output reg [1:0] ba `SYN;
output reg [12:0] a `SYN;
output reg [2:0] cmd `SYN;
output cke, cs_n;
output reg [1:0] dqm `SYN;
output reg [15:0] dq_o `SYN;
output reg dq_oe;
input [15:0] dq_i;
output reg [1:0] ba `SYN;
output reg [12:0] a `SYN;
output reg [2:0] cmd `SYN;
output cke, cs_n;
output reg [1:0] dqm `SYN;
output reg [15:0] dq_o `SYN;
output reg dq_oe;
input [15:0] dq_i;
 
input clk, rst;
input clk, rst;
 
wire [ba_size-1:0] bank;
wire [row_size-1:0] row;
wire [col_size-1:0] col;
wire [12:0] col_a10_fix;
reg [4:0] col_reg;
wire [0:31] shreg;
reg count0;
wire stall; // active if write burst need data
reg ref_cnt_zero, refresh_req;
reg cmd_read;
reg wb_flag;
reg [1:6] ack_rd;
wire ack_wr;
wire [ba_size-1:0] bank;
wire [row_size-1:0] row;
wire [col_size-1:0] col;
wire [12:0] col_a10_fix;
reg [4:0] col_reg;
wire [0:31] shreg;
reg count0;
wire stall; // active if write burst need data
reg ref_cnt_zero, refresh_req;
reg wb_flag;
 
reg [1:6] ack_rd;
wire ack_wr;
 
// to keep track of open rows per bank
reg [row_size-1:0] open_row[0:3];
reg [0:3] open_ba;
reg current_bank_closed, current_row_open;
reg [row_size-1:0] open_row[0:3];
reg [0:3] open_ba;
reg current_bank_closed, current_row_open;
`ifndef RFR_WRAP_VALUE
parameter rfr_length = 10;
parameter rfr_wrap_value = 1010;
parameter rfr_length = 10;
parameter rfr_wrap_value = 1010;
`else
parameter rfr_length = `RFR_LENGTH;
parameter rfr_wrap_value = `RFR_WRAP_VALUE;
parameter rfr_length = `RFR_LENGTH;
parameter rfr_wrap_value = `RFR_WRAP_VALUE;
`endif
parameter [1:0] linear = 2'b00,
beat4 = 2'b01,
beat8 = 2'b10,
beat16 = 2'b11;
parameter [1:0] linear = 2'b00,
beat4 = 2'b01,
beat8 = 2'b10,
beat16 = 2'b11;
 
parameter [2:0] cmd_nop = 3'b111,
cmd_act = 3'b011,
cmd_rd = 3'b101,
cmd_wr = 3'b100,
cmd_pch = 3'b010,
cmd_rfr = 3'b001,
cmd_lmr = 3'b000;
parameter [2:0] cmd_nop = 3'b111,
cmd_act = 3'b011,
cmd_rd = 3'b101,
cmd_wr = 3'b100,
cmd_pch = 3'b010,
cmd_rfr = 3'b001,
cmd_lmr = 3'b000;
 
// ctrl FSM
`define FSM_INIT 3'b000
118,12 → 129,11
 
assign {bank,row,col} = adr_i;
 
always @ (posedge clk or posedge rst) begin
always @ (posedge clk or posedge rst)
if (rst)
state <= `FSM_INIT;
else
state <= next;
end
always @*
begin
149,15 → 159,11
`FSM_ACT:
if (shreg[2]) next = `FSM_RW;
else next = `FSM_ACT;
// `FSM_W4D:
// if (!fifo_empty) next = `FSM_RW;
// else next = `FSM_W4D;
`FSM_RW:
if (bte_i==linear & shreg[1]) next = `FSM_IDLE;
else if (bte_i==beat4 & shreg[7]) next = `FSM_IDLE;
`ifdef BEAT8
else if (bte_i==beat8 & shreg[15])
next = `FSM_IDLE;
else if (bte_i==beat8 & shreg[15]) next = `FSM_IDLE;
`endif
`ifdef BEAT16
else if (bte_i==beat16 & shreg[31]) next = `FSM_IDLE;
178,19 → 184,8
wb_flag <= 1'b1;
else if ((cti_i==3'b000 | cti_i==3'b111) & ack_o)
wb_flag <= 1'b0;
//// counter
//always @ (posedge clk or posedge rst)
//if (rst)
// {shreg,count0} <= {32'h80000000,1'b0};
//else
// if (!stall)
// if (state==next)
// {shreg,count0} <= {shreg >> 1,!count0};
// else
// {shreg,count0} <= {32'h80000000,1'b0};
// counter
 
// counter
cnt_shreg_ce_clear # ( .length(32))
cnt0 (
.cke(!stall),
228,12 → 223,12
case (state)
`FSM_INIT:
if (shreg[3]) begin
{ba,a,cmd} <= {2'b00, 13'b0010000000000, cmd_pch};
{ba,a,cmd} <= {2'b00, 13'b0010000000000, cmd_pch};
open_ba[bank] <= 1'b0;
end else if (shreg[7] | shreg[19])
{ba,a,cmd} <= {2'b00, 13'd0, cmd_rfr};
{ba,a,cmd} <= {2'b00, 13'd0, cmd_rfr};
else if (shreg[31])
{ba,a,cmd} <= {2'b00,3'b000,`INIT_WB,2'b00,`INIT_CL,`INIT_BT,`INIT_BL, cmd_lmr};
{ba,a,cmd} <= {2'b00,3'b000,init_wb,2'b00,init_cl,init_bt,init_bl,cmd_lmr};
`FSM_RFR:
if (shreg[0]) begin
{ba,a,cmd} <= {2'b00, 13'b0010000000000, cmd_pch};
241,11 → 236,10
end else if (shreg[2])
{ba,a,cmd} <= {2'b00, 13'd0, cmd_rfr};
`FSM_IDLE:
col_reg <= col[4:0];
col_reg <= col[4:0];
`FSM_PCH:
if (shreg[0]) begin
{ba,a,cmd} <= {ba,13'd0,cmd_pch};
//open_ba <= 4'b0000;
open_ba[bank] <= 1'b0;
end
`FSM_ACT:
258,7 → 252,7
if (we_i & !count0)
cmd <= cmd_wr;
else if (!count0)
{cmd,cmd_read} <= {cmd_rd,1'b1};
cmd <= cmd_rd;
else
cmd <= cmd_nop;
if (we_i & !count0)
305,12 → 299,7
else if (state==`FSM_RFR)
refresh_req <= 1'b0;
// data to WB
//always @ (posedge clk or posedge rst)
//if (rst)
// dat_o <= 32'h00000000;
//else
// dat_o <= {dat_o[15:0],dq_i};
 
dff # ( .width(32)) wb_dat_dff ( .d({dat_o[15:0],dq_i}), .q(dat_o), .clk(clk), .rst(rst));
assign ack_wr = (state==`FSM_RW & count0 & we_i);

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