URL
https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
Subversion Repositories xulalx25soc
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 97 to Rev 98
- ↔ Reverse comparison
Rev 97 → Rev 98
/xulalx25soc/trunk/rtl/cpu/div.v
12,7 → 12,7
// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
/xulalx25soc/trunk/rtl/cpu/idecode.v
19,7 → 19,7
// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
/xulalx25soc/trunk/rtl/cpu/zipjiffies.v
45,7 → 45,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
/xulalx25soc/trunk/rtl/cpu/zipsystem.v
64,7 → 64,7
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
/xulalx25soc/trunk/rtl/cpu/zipcpu.v
1741,47 → 1741,22
`ifdef DEBUG_SCOPE |
always @(posedge i_clk) |
o_debug <= { |
/* |
/* |
o_break, i_wb_err, pf_pc[1:0], |
// |
flags, |
// |
pf_valid, dcdvalid, opvalid, alu_valid, |
// |
mem_valid, |
pf_valid, dcdvalid, opvalid, alu_valid, mem_valid, |
op_ce, alu_ce, mem_ce, |
// |
master_ce, |
opvalid_alu, opvalid_mem, alu_stall, |
master_ce, opvalid_alu, opvalid_mem, |
// |
mem_busy, op_pipe, |
`ifdef OPT_PIPELINED_BUS_ACCESS |
mem_pipe_stalled, |
`else |
1'b0, |
`endif |
alu_stall, mem_busy, op_pipe, mem_pipe_stalled, |
mem_we, |
// |
// ((opvalid_alu)&&(alu_stall)) |
// ||((opvalid_mem)&&(~op_pipe)&&(mem_busy)) |
// ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled))); |
// opA[23:20], opA[3:0], |
gie, sleep, wr_reg_ce, wr_reg_vl[4:0] |
*/ |
|
o_break, i_wb_err, o_wb_gbl_cyc, o_wb_gbl_stb, |
pf_valid, dcdvalid, opvalid, alu_valid, |
mem_valid, dcd_ce, op_ce, alu_ce, |
mem_ce, |
// |
(new_pc)||((dcd_early_branch)&&(~clear_pipeline)), |
gie, sleep, |
{ ((o_wb_gbl_cyc)&&(o_wb_gbl_stb)&&(o_wb_we)) |
? o_wb_data[15:0] |
: ((o_wb_gbl_cyc)&&(~o_wb_we)&&(i_wb_ack)) |
? i_wb_data[15:0] |
: o_wb_addr[15:0] |
} |
gie, sleep, wr_reg_ce, wr_gpreg_vl[4:0] |
*/ |
/* |
i_rst, master_ce, (new_pc), |
((dcd_early_branch)&&(dcdvalid)), |
1790,7 → 1765,7
pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err, |
pf_pc[7:0], pf_addr[7:0] |
*/ |
/* |
|
i_wb_err, gie, alu_illegal, |
(new_pc)||((dcd_early_branch)&&(~clear_pipeline)), |
mem_busy, |
1799,7 → 1774,7
: { instruction[31:21] }, |
pf_valid, (pf_valid) ? alu_pc[14:0] |
:{ pf_cyc, pf_stb, pf_pc[12:0] } |
*/ |
|
/* |
i_wb_err, gie, new_pc, dcd_early_branch, // 4 |
pf_valid, pf_cyc, pf_stb, instruction_pc[0], // 4 |