Subversion Repositories 8051

/trunk/sim/rtl_sim/src/verilog/oc8051_xram.v File deleted

/trunk/sim/rtl_sim/src/verilog/oc8051_rom_fpga.v File deleted

trunk/sim/rtl_sim/src/verilog/oc8051_rom_fpga.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/sim/rtl_sim/src/verilog/oc8051_uart_test.v =================================================================== --- trunk/sim/rtl_sim/src/verilog/oc8051_uart_test.v (revision 98) +++ trunk/sim/rtl_sim/src/verilog/oc8051_uart_test.v (nonexistent) @@ -1,103 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// 8051 uart test //// -//// //// -//// This file is part of the 8051 cores project //// -//// http://www.opencores.org/cores/8051/ //// -//// //// -//// Description //// -//// submodul of oc8051_tb, used to comunicate with 8051 //// -//// serial potr //// -//// //// -//// To Do: //// -//// nothing //// -//// //// -//// Author(s): //// -//// - Simon Teran, simont@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// - -// synopsys translate_off -`include "oc8051_timescale.v" -// synopsys translate_on - - -module oc8051_uart_test (clk, rst, addr, wr, wr_bit, data_in, data_out, bit_out, rxd, txd, ow, intr, ack, stb); -// -// serial interface simulation. part of oc8051_tb -// -// clk (in) clock -// rst (in) reset -// addr (in) addres [oc8051.ext_addr] -// wr (in) write [oc8051.write] -// wr_bit (in) write bit addresable [oc8051.p3_out.0] -// data_in (out) data input [oc8051.data_out] -// data_out (in) data output [oc8051.data_in] -// rxd (in) receive data [oc8051.txd] -// txd (out) transmit data [oc8051.rxd] -// ow (in) owerflov (used in mode 1 and 3) [oc8051.p3_out.1] -// intr (out) interrupt request [oc8051.p3_in.0] -// - -input clk, rst, wr, wr_bit, rxd, ow, stb; -input [7:0] addr, data_in; - -output txd, intr, bit_out, ack; -output [7:0] data_out; - -wire syn; -reg wr_r, ack; -reg [7:0] addr_r, data_in_r; - - -oc8051_uart oc8051_uart_test(.rst(rst), .clk(clk), .bit_in(data_in[0]), .rd_addr(addr), .data_in(data_in_r), - .wr(wr_r), .wr_bit(wr_bit), .wr_addr(addr_r), .data_out(data_out), .bit_out(bit_out), - .rxd(rxd), .txd(txd), .intr(intr), .t1_ow(ow)); - - -always @(posedge clk) -begin - if (ack) ack <= #1 1'b0; - else - ack <= #1 stb; -end - -always @(posedge clk) -begin - wr_r <= #1 wr; - addr_r <= #1 addr; - data_in_r <= #1 data_in; -end - - -endmodule Index: trunk/sim/rtl_sim/src/verilog/oc8051_rom.v =================================================================== --- trunk/sim/rtl_sim/src/verilog/oc8051_rom.v (revision 98) +++ trunk/sim/rtl_sim/src/verilog/oc8051_rom.v (nonexistent) @@ -1,93 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// 8051 internal program rom //// -//// //// -//// This file is part of the 8051 cores project //// -//// http://www.opencores.org/cores/8051/ //// -//// //// -//// Description //// -//// internal program rom for 8051 core //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Simon Teran, simont@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.3 2002/09/30 17:34:01 simont -// prepared header -// -// - -module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3); - -//parameter INT_ROM_WID= 15; - -input rst, clk; -input [15:0] addr; -output ea_int; -output [7:0] data1, data2, data3; - -reg ea_int; -reg [7:0] data1, data2, data3; -reg [7:0] buff [65535:0]; -integer i; - -wire ea; - -//assign ea = | addr[15:INT_ROM_WID]; -assign ea = 1'b0; -//assign ea_int = ! ea; - -initial -begin - for (i=0; i<65536; i=i+1) - buff [i] = 8'h00; - $readmemh("../../../asm/in/oc8051_rom.in", buff); -end - -always @(posedge clk or posedge rst) - if (rst) - ea_int <= #1 1'b1; - else ea_int <= #1 !ea; - -always @(posedge clk) -begin - data1 <= #1 buff [addr]; - data2 <= #1 buff [addr+1]; - data3 <= #1 buff [addr+2]; -end - -endmodule - -

trunk/sim/rtl_sim/src/verilog/oc8051_rom.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/sim/rtl_sim/src/verilog/oc8051_cache_ram.v =================================================================== --- trunk/sim/rtl_sim/src/verilog/oc8051_cache_ram.v (revision 98) +++ trunk/sim/rtl_sim/src/verilog/oc8051_cache_ram.v (nonexistent) @@ -1,113 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// 8051 cache ram //// -//// //// -//// This file is part of the 8051 cores project //// -//// http://www.opencores.org/cores/8051/ //// -//// //// -//// Description //// -//// 64x32 dual port ram for instruction cache //// -//// //// -//// To Do: //// -//// nothing //// -//// //// -//// Author(s): //// -//// - Simon Teran, simont@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.1 2002/10/23 16:58:21 simont -// initial import -// -// - -// synopsys translate_off -`include "oc8051_timescale.v" -// synopsys translate_on - - -module oc8051_cache_ram (clk, rst, addr0, data0, addr1, data1_i, data1_o, wr1); -// -// this module is part of oc8051_icache -// it's tehnology dependent -// -// clk (in) clock -// addr0 (in) addres port 0 -// data0 (out) data output port 0 -// addr1 (in) address port 1 -// data1_i (in) data input port 1 -// data1_o (out) data output port 1 -// wr1 (in) write port 1 -// - -parameter ADR_WIDTH = 7; // cache address wihth -parameter CACHE_RAM = 128; // cache ram x 32 (2^ADR_WIDTH) - -input clk, wr1, rst; -input [ADR_WIDTH-1:0] addr0, addr1; -input [31:0] data1_i; -output [31:0] data0, data1_o; - -reg [31:0] data0, data1_o; - -// -// buffer -reg [31:0] buff [CACHE_RAM:0]; - -// -// port 1 -// -always @(posedge clk or posedge rst) -begin - if (rst) - data1_o <= #1 32'h0; - else if (wr1) begin - buff[addr1] <= #1 data1_i; - data1_o <= #1 data1_i; - end else - data1_o <= #1 buff[addr1]; -end - -// -// port 0 -// -always @(posedge clk or posedge rst) -begin - if (rst) - data0 <= #1 32'h0; - else if ((addr0==addr1) & wr1) - data0 <= #1 data1_i; - else - data0 <= #1 buff[addr0]; -end - - -endmodule

trunk/sim/rtl_sim/src/verilog/oc8051_cache_ram.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/sim/rtl_sim/src/verilog/oc8051_xrom.v =================================================================== --- trunk/sim/rtl_sim/src/verilog/oc8051_xrom.v (revision 98) +++ trunk/sim/rtl_sim/src/verilog/oc8051_xrom.v (nonexistent) @@ -1,99 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// 8051 exteranl program rom //// -//// //// -//// This file is part of the 8051 cores project //// -//// http://www.opencores.org/cores/8051/ //// -//// //// -//// Description //// -//// external program rom for 8051 core //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Simon Teran, simont@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// - -module oc8051_xrom (rst, clk, addr, data, stb_i, cyc_i, ack_o); - -parameter DELAY=5; - - -input rst, clk, stb_i, cyc_i; -input [15:0] addr; -output ack_o; -output [31:0] data; - -reg ack_o; -reg [31:0] data; -reg [7:0] buff [65535:0]; -reg [2:0] cnt; -integer i; - - -initial -begin - for (i=0; i<65536; i=i+1) - buff [i] = 8'h00; - $readmemh("../../../asm/in/oc8051_xrom.in", buff); -end - -always @(posedge clk or posedge rst) -begin - if (rst) begin - data <= #1 31'h0; - ack_o <= #1 1'b0; - end else if (stb_i && ((DELAY==3'b000) || (cnt==3'b000))) begin - data <= #1 {buff [addr], buff[addr+1], buff[addr+2], buff[addr+3]}; - ack_o <= #1 1'b1; - end else - ack_o <= #1 1'b0; -end - -always @(posedge clk or posedge rst) -begin - if (rst) - cnt <= #1 DELAY; - else if (cnt == 3'b000) - cnt <= #1 DELAY; - else if (stb_i) - cnt <= #1 cnt - 3'b001; - else cnt <= #1 DELAY; -end - - -endmodule - -

trunk/sim/rtl_sim/src/verilog/oc8051_xrom.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/sim/rtl_sim/src/verilog/oc8051_timescale.v =================================================================== --- trunk/sim/rtl_sim/src/verilog/oc8051_timescale.v (revision 98) +++ trunk/sim/rtl_sim/src/verilog/oc8051_timescale.v (nonexistent) @@ -1,3 +0,0 @@ - - -`timescale 1ns/10ps

trunk/sim/rtl_sim/src/verilog/oc8051_timescale.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property