URL
https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk
Subversion Repositories 6809_6309_compatible_core
Compare Revisions
- This comparison shows the changes necessary to convert path
/6809_6309_compatible_core/trunk/rtl
- from Rev 14 to Rev 15
- ↔ Reverse comparison
Rev 14 → Rev 15
/verilog/Changelog.txt
1,5 → 1,9
Changelong |
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|
20.07.14 |
--------- |
- decoders.v : fix decoding of STD, LDD |
16.07.14 |
-------- |
- decoders.v : decode of some opcodes modified to improve size & speed |
/verilog/decoders.v
118,10 → 118,11
8'hcx, 8'hdx, 8'hex, 8'hfx: |
case (opcode[3:0]) |
4'h1, 4'h5: path_left_addr = `RN_ACCB; // CMP, BIT |
4'h3, 4'hc: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end |
4'h7: begin path_left_addr = `RN_ACCB; dest_reg = `RN_MEM8; end // store to mem |
4'hd: begin path_left_addr = `RN_ACCD; end // LDD |
4'he: begin path_left_addr = `RN_U; dest_reg = `RN_U; end // LDU |
4'h3: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end // addd |
4'h7: begin path_left_addr = `RN_ACCB; dest_reg = `RN_MEM8; end // stb |
4'hc: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end // ldd |
4'hd: begin path_left_addr = `RN_ACCD; dest_reg = `RN_MEM16; end // STD |
4'he: begin dest_reg = `RN_U; end // LDU |
4'hf: begin path_left_addr = `RN_U; dest_reg = `RN_MEM16; end // STU |
default: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end |
endcase |
128,16 → 129,25
endcase |
casex (opcode) // right arm |
// 8x and Cx |
8'b1x00_000x, 8'b1x00_0010: path_right_addr = `RN_IMM8; // sub, cmp, scb |
8'b1x00_0011, 8'b1x00_11x0: path_right_addr = `RN_IMM16; // cmpd, cmpx, ldx |
8'b1x00_000x, 8'b1x00_0010, // sub, cmp, scb |
8'b1x00_010x, 8'b1x00_0110, 8'b1x00_10xx: path_right_addr = `RN_IMM8; |
// 83, C3, 8C, CC, 8E, CE |
8'b1x00_0011, 8'b1x00_11x0: path_right_addr = `RN_IMM16; // cmpd, cmpx, ldx |
// 9, A, B, D, E, F |
8'b1x01_000x, 8'b1x01_0010: path_right_addr = `RN_MEM8; |
8'b1x01_0011, 8'b1x01_11x0: path_right_addr = `RN_MEM16; // cmpd, cmpx, ldx |
8'b1x01_010x, 8'b1x01_0110, 8'b1x01_10xx: path_right_addr = `RN_MEM8; |
8'b1x1x_000x, 8'b1x1x_0010: path_right_addr = `RN_MEM8; |
8'b1x1x_0011, 8'b1x1x_11x0: path_right_addr = `RN_MEM16; |
8'b1x01_000x, 8'b1x01_0010, // x0, x1, x2: sub cmp, scb |
8'b1x01_010x, 8'b1x01_0110, 8'b1x01_10xx, |
8'b1x1x_000x, 8'b1x1x_0010, |
8'b1x1x_010x, 8'b1x1x_0110, 8'b1x1x_10xx: path_right_addr = `RN_MEM8; |
// 9x, Ax, Bx, Dx, Ex, Fx |
8'h93, 8'ha3, 8'hb3, // subd |
8'hd3, 8'he3, 8'hf3, // addd |
8'h9c, 8'hac, 8'hbc, // cmpx |
8'hdc, 8'hec, 8'hfc, // ldd |
//8'hdd, 8'hed, 8'hfd, // std |
8'h9e, 8'hae, 8'hbe, // ldx |
8'hde, 8'hee, 8'hfe, // ldu |
//8'h9f, 8'haf, 8'hbf, // stx |
8'hdf, 8'hef, 8'hff: path_right_addr = `RN_MEM16;// stu |
endcase |
end |
// latched versions are used to fetch regsiters |
360,7 → 370,7
8'b1xxx_1011: alu_opcode = `ADD; |
8'b10xx_1100: alu_opcode = `SUB; // CMP |
8'b11xx_1100: alu_opcode = `LD; |
8'b11xx_1101: alu_opcode = `LD; |
8'b11xx_1101: alu_opcode = `ST; |
8'b1xxx_1110: alu_opcode = `LD; |
8'b1xxx_1111: alu_opcode = `ST; |
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