URL
https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk
Subversion Repositories 6809_6309_compatible_core
Compare Revisions
- This comparison shows the changes necessary to convert path
/6809_6309_compatible_core/trunk/syn
- from Rev 12 to Rev 13
- ↔ Reverse comparison
Rev 12 → Rev 13
/lattice/P68091.sty
9,6 → 9,7
<Property name="PROP_BD_ParSearchPath" value="" time="0"/> |
<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/> |
<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/> |
<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/> |
<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/> |
<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/> |
<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/> |
67,6 → 68,7
<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/> |
<Property name="PROP_LST_ResourceShare" value="True" time="0"/> |
<Property name="PROP_LST_UseIOReg" value="True" time="0"/> |
<Property name="PROP_LST_VHDL2008" value="False" time="0"/> |
<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/> |
<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/> |
<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/> |
/lattice/P6809/hdla_gen_hierarchy.html
18,16 → 18,16
(VERI-1482) Analyzing Verilog file C:/02_Elektronik/020_V6809/trunk/syn/lattice/textmem4k.v |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/CC3_top.v(10,8-10,15) (VERI-1018) compiling module CC3_top |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/CC3_top.v(10,1-175,10) (VERI-9000) elaborating module 'CC3_top' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/MC6809_cpu.v(10,1-1115,10) (VERI-9000) elaborating module 'MC6809_cpu_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/MC6809_cpu.v(10,1-1137,10) (VERI-9000) elaborating module 'MC6809_cpu_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/bios2k.v(8,1-171,10) (VERI-9000) elaborating module 'bios2k_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/vgatext.v(2,1-192,10) (VERI-9000) elaborating module 'vgatext_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(15,1-57,10) (VERI-9000) elaborating module 'alu_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(15,1-61,10) (VERI-9000) elaborating module 'alu_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/regblock.v(7,1-188,10) (VERI-9000) elaborating module 'regblock_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(9,1-144,10) (VERI-9000) elaborating module 'decode_regs_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(147,1-270,10) (VERI-9000) elaborating module 'decode_op_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(275,1-299,10) (VERI-9000) elaborating module 'decode_ea_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(301,1-372,10) (VERI-9000) elaborating module 'decode_alu_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(374,1-410,10) (VERI-9000) elaborating module 'test_condition_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(9,1-152,10) (VERI-9000) elaborating module 'decode_regs_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(155,1-281,10) (VERI-9000) elaborating module 'decode_op_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(286,1-310,10) (VERI-9000) elaborating module 'decode_ea_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(312,1-383,10) (VERI-9000) elaborating module 'decode_alu_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(385,1-422,10) (VERI-9000) elaborating module 'test_condition_uniq_1' |
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1' |
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_1' |
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_2' |
34,8 → 34,9
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/fontrom.v(8,1-295,10) (VERI-9000) elaborating module 'fontrom_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/textmem4k.v(8,1-305,10) (VERI-9000) elaborating module 'textmem4k_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(198,1-323,10) (VERI-9000) elaborating module 'alu8_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(326,1-602,10) (VERI-9000) elaborating module 'alu16_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(604,1-628,10) (VERI-9000) elaborating module 'mul8x8_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(202,1-326,10) (VERI-9000) elaborating module 'alu8_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(329,1-602,10) (VERI-9000) elaborating module 'alu16_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/regblock.v(191,1-285,10) (VERI-9000) elaborating module 'calc_ea_uniq_1' |
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_2' |
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_3' |
49,11 → 50,10
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_10' |
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_2' |
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_3' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(62,1-79,10) (VERI-9000) elaborating module 'logic8_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(85,1-123,10) (VERI-9000) elaborating module 'arith8_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(158,1-195,10) (VERI-9000) elaborating module 'shift8_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(604,1-628,10) (VERI-9000) elaborating module 'mul8x8_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(129,1-156,10) (VERI-9000) elaborating module 'arith16_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(66,1-83,10) (VERI-9000) elaborating module 'logic8_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(89,1-127,10) (VERI-9000) elaborating module 'arith8_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(162,1-199,10) (VERI-9000) elaborating module 'shift8_uniq_1' |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(133,1-160,10) (VERI-9000) elaborating module 'arith16_uniq_1' |
Done: design load finished with (0) errors, and (0) warnings |
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</PRE></BODY></HTML> |
/lattice/P6809/P6809_P6809_summary.html
146,7 → 146,7
</TR> |
<TR> |
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD> |
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2014/07/06 07:47:16</SPAN></TD> |
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2014/07/06 13:38:36</SPAN></TD> |
</TR> |
<TR> |
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD> |
/lattice/CC3_top.v
155,7 → 155,7
.QB() |
); |
|
|
/* 80x38 VGA Controller, using 40 MHz clock, 800x600@60 Hz timing */ |
vgatext textctrl( |
.CLK(clk40_i), |
.RESET(cpu_reset), |