OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /8051/tags/rel0/syn/src/verilog
    from Rev 185 to Rev 186
    ↔ Reverse comparison
  •

Rev 185 → Rev 186

/oc8051_rom.v
0,0 → 1,183
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 program rom ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// program rom ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// ver: 1
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
//`include "oc8051_defines.v"
 
module ROM32X1(O, A0, A1, A2, A3, A4); // synthesis syn_black_box syn_resources="luts=2"
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
endmodule
 
//rom for 8051 processor
 
module oc8051_rom (clk, rst, addr, data1, data2, data3);
 
input clk, rst;
input [15:0] addr;
output [7:0] data1, data2, data3;
 
reg [7:0] data1, data2, data3;
reg [4:0] addr01;
 
wire [15:0] addr_rst;
wire [7:0] int_data0, int_data1, int_data2, int_data3;
 
assign addr_rst = rst ? 16'h0000 : addr;
 
rom0 rom_0 (.a(addr01), .o(int_data0));
rom1 rom_1 (.a(addr01), .o(int_data1));
rom2 rom_2 (.a(addr_rst[6:2]), .o(int_data2));
rom3 rom_3 (.a(addr_rst[6:2]), .o(int_data3));
 
always @(addr_rst)
begin
if (addr_rst[1])
addr01= addr_rst[6:2]+5'b00001;
else
addr01= addr_rst[6:2];
end
 
//
// always read tree bits in row
always @(posedge clk)
begin
case(addr[1:0])
2'b00: begin
data1 <= #1 int_data0;
data2 <= #1 int_data1;
data3 <= #1 int_data2;
end
2'b01:begin
data1 <= #1 int_data1;
data2 <= #1 int_data2;
data3 <= #1 int_data3;
end
2'b10:begin
data1 <= #1 int_data2;
data2 <= #1 int_data3;
data3 <= #1 int_data0;
end
2'b11:begin
data1 <= #1 int_data3;
data2 <= #1 int_data0;
data3 <= #1 int_data1;
end
default: begin
data1 <= #1 8'h00;
data2 <= #1 8'h00;
data3 <= #1 8'h00;
end
endcase
end
 
endmodule
 
 
//rom0
module rom0 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00003810" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=08047212" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=04003e00" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00043412" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0c023c10" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0c063f12" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=04063d10" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000634b2" */;
endmodule
 
//rom1
module rom1 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=040061c4" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00061100" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00100094" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00027292" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00123256" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00147096" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00107096" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00006880" */;
endmodule
 
//rom2
module rom2 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02101c53" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00023040" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02005261" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02023360" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02005801" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02023241" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02023201" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00023224" */;
endmodule
 
//rom3
module rom3 (o,a);
input [4:0] a;
output [7:0] o;
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02100b16" */;
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02200604" */;
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02103416" */;
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02100846" */;
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00331c33" */;
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0033381a" */;
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0013181a" */;
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000061" */;
endmodule
 
 
oc8051_rom.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: oc8051_fpga_top.v =================================================================== --- oc8051_fpga_top.v (nonexistent) +++ oc8051_fpga_top.v (revision 186) @@ -0,0 +1,122 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// 8051 fpga top module //// +//// //// +//// This file is part of the 8051 cores project //// +//// http://www.opencores.org/cores/8051/ //// +//// //// +//// Description //// +//// tpo module used for testing in xilinx fpga chip //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Simon Teran, simont@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// ver: 1 +// + + +// synopsys translate_off +`include "oc8051_timescale.v" +// synopsys translate_on + +module oc8051_fpga_top (clk, rst, int1, int2, int3, sw1, sw2, sw3, sw4, int_act, dispout, p0_out, p1_out, p2_out, p3_out, data_out, ext_addr); + +input clk, rst, int1, int2, int3; +output sw1, sw2, sw3, sw4, int_act; +output [13:0] dispout; +output [7:0] p0_out, p1_out, p2_out, p3_out, data_out; +output [15:0] ext_addr; + + +reg int; +reg [7:0] int_v; + +wire reti, write; +wire [7:0] data_out; +wire nrst; + +reg int_act, ok; + +assign nrst = ~rst; + +assign sw1 = int1; +assign sw2 = int2; +assign sw3 = int3; +assign sw4 = nrst; + +oc8051_top oc8051_top_1(.rst(nrst), .clk(clk), .int(int), .int_v(int_v), .reti(reti), .data_in(8'h00), .data_out(data_out), + .ext_addr(ext_addr), .write(write), .p0_in(8'hb0), .p1_in(8'hb1), .p2_in(8'hb2), .p3_in(8'hb3), .p0_out(p0_out), + .p1_out(p1_out), .p2_out(p2_out), .p3_out(p3_out)); + + + disp disp1(.in(p0_out), .out(dispout)); + +always @(posedge clk) +begin + if (int_act) begin + int <= #1 1'b0; + end else if (ok==1'b0) begin + if (int1==1'b0) begin + int_v <= #1 8'h40; + int <= #1 1'b1; + end + else if (int2==1'b0) begin + int_v <= #1 8'h50; + int <= #1 1'b1; + end + else if (int3==1'b0) begin + int_v <= #1 8'h65; + int <= #1 1'b1; + end else int <= #1 1'b0; + end +end + +always @(posedge clk) +begin + if (nrst) + int_act <= #1 1'b0; + else if (reti) + int_act <= #1 1'b0; + else if (int) + int_act <= #1 1'b1; +end + +always @(posedge clk) +begin + case ({int1, int2, int3}) + 3'b111: ok <= #1 1'b0; + default: ok <= #1 1'b1; + endcase +end + +endmodule
oc8051_fpga_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: oc8051_ram.v =================================================================== --- oc8051_ram.v (nonexistent) +++ oc8051_ram.v (revision 186) @@ -0,0 +1,88 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// 8051 data ram //// +//// //// +//// This file is part of the 8051 cores project //// +//// http://www.opencores.org/cores/8051/ //// +//// //// +//// Description //// +//// data ram for virtex //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Simon Teran, simont@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// ver: 1 +// + +// synopsys translate_off +`include "oc8051_timescale.v" +// synopsys translate_on + +module oc8051_ram (clk, rst, rd_addr, rd_data, wr_addr, wr_data, wr); +// clk clock +// rd_addr read addres +// rd_data read data +// wr_addr write addres +// wr_data write data +// wr write + + +input clk, wr, rst; +input [7:0] rd_addr, wr_addr, wr_data; +output [7:0] rd_data; + +wire [7:0] dob; +RAMB4_S8_S8 ram1(.DOA(rd_data), .DOB(dob), .ADDRA({1'b0, rd_addr}), .DIA(8'h00), .ENA(1'b1), .CLKA(clk), .WEA(1'b0), + .RSTA(rst), .ADDRB({1'b0, wr_addr}), .DIB(wr_data), .ENB(1'b1), .CLKB(clk), .WEB(wr), .RSTB(rst)); + + +endmodule + + + +module RAMB4_S8_S8(DOA, DOB, ADDRA, DIA, ENA, CLKA, WEA, RSTA, ADDRB, DIB, ENB, CLKB, WEB, RSTB); // synthesis syn_black_box +output [7:0] DOA; +output [7:0] DOB; +input [8:0] ADDRA; +input [7:0] DIA; +input ENA; +input CLKA; +input WEA; +input RSTA; +input [8:0] ADDRB; +input [7:0] DIB; +input ENB; +input CLKB; +input WEB; +input RSTB; +endmodule
oc8051_ram.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: disp.v =================================================================== --- disp.v (nonexistent) +++ disp.v (revision 186) @@ -0,0 +1,55 @@ +// +// decoder for 7 led display +// + +module disp (in, out); + +input [7:0] in; +output [13:0] out; + +reg [13:0] out; + +always @(in) +begin + case (in[7:4]) + 4'h0: out[13:7] = 7'b1110111; + 4'h1: out[13:7] = 7'b0100100; + 4'h2: out[13:7] = 7'b1011101; + 4'h3: out[13:7] = 7'b1101101; + 4'h4: out[13:7] = 7'b0101110; + 4'h5: out[13:7] = 7'b1101011; + 4'h6: out[13:7] = 7'b1111011; + 4'h7: out[13:7] = 7'b0100111; + 4'h8: out[13:7] = 7'b1111111; + 4'h9: out[13:7] = 7'b1101111; + 4'ha: out[13:7] = 7'b0111111; + 4'hb: out[13:7] = 7'b1111010; + 4'hc: out[13:7] = 7'b1010011; + 4'hd: out[13:7] = 7'b1111100; + 4'he: out[13:7] = 7'b1011011; + 4'hf: out[13:7] = 7'b0011011; + default: out[13:7] = 7'b0000000; + endcase + + case (in[3:0]) + 4'h0: out[6:0] = 7'b1110111; + 4'h1: out[6:0] = 7'b0100100; + 4'h2: out[6:0] = 7'b1011101; + 4'h3: out[6:0] = 7'b1101101; + 4'h4: out[6:0] = 7'b0101110; + 4'h5: out[6:0] = 7'b1101011; + 4'h6: out[6:0] = 7'b1111011; + 4'h7: out[6:0] = 7'b0100111; + 4'h8: out[6:0] = 7'b1111111; + 4'h9: out[6:0] = 7'b1101111; + 4'ha: out[6:0] = 7'b0111111; + 4'hb: out[6:0] = 7'b1111010; + 4'hc: out[6:0] = 7'b1010011; + 4'hd: out[6:0] = 7'b1111100; + 4'he: out[6:0] = 7'b1011011; + 4'hf: out[6:0] = 7'b0011011; + default: out[6:0] = 7'b0000000; + endcase +end + +endmodule
disp.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: read.me =================================================================== --- read.me (nonexistent) +++ read.me (revision 186) @@ -0,0 +1 @@ +These files are used for syntesis in xilinx virtex. \ No newline at end of file
read.me Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.