Subversion Repositories 8051

/rtl_sim/run/run_sim.scr

rtl_sim/run/run_sim.scr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl_sim/run/make_verilog =================================================================== --- rtl_sim/run/make_verilog (nonexistent) +++ rtl_sim/run/make_verilog (revision 186) @@ -0,0 +1,32 @@ +verilog \ +../../../bench/verilog/oc8051_tb.v \ +../../../bench/verilog/oc8051_xram.v \ +../../../bench/verilog/oc8051_uart_test.v \ +../../../bench/verilog/oc8051_xrom.v \ +../../../rtl/verilog/oc8051_top.v \ +../../../rtl/verilog/oc8051_alu_src_sel.v \ +../../../rtl/verilog/oc8051_alu.v \ +../../../rtl/verilog/oc8051_decoder.v \ +../../../rtl/verilog/oc8051_divide.v \ +../../../rtl/verilog/oc8051_multiply.v \ +../../../rtl/verilog/oc8051_memory_interface.v \ +../../../rtl/verilog/oc8051_ram_top.v \ +../../../rtl/verilog/oc8051_acc.v \ +../../../rtl/verilog/oc8051_comp.v \ +../../../rtl/verilog/oc8051_sp.v \ +../../../rtl/verilog/oc8051_dptr.v \ +../../../rtl/verilog/oc8051_cy_select.v \ +../../../rtl/verilog/oc8051_psw.v \ +../../../rtl/verilog/oc8051_indi_addr.v \ +../../../rtl/verilog/oc8051_ports.v \ +../../../rtl/verilog/oc8051_b_register.v \ +../../../rtl/verilog/oc8051_uart.v \ +../../../rtl/verilog/oc8051_int.v \ +../../../rtl/verilog/oc8051_tc.v \ +../../../rtl/verilog/oc8051_tc2.v \ +../../../rtl/verilog/oc8051_icache.v \ +../../../rtl/verilog/oc8051_wb_iinterface.v \ +../../../rtl/verilog/oc8051_sfr.v \ +../../../rtl/verilog/oc8051_rom.v \ +../../../rtl/verilog/oc8051_cache_ram.v \ +../../../../common/generic_memories/rtl/verilog/generic_dpram.v

rtl_sim/run/make_verilog Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl_sim/run/run =================================================================== --- rtl_sim/run/run (nonexistent) +++ rtl_sim/run/run (revision 186) @@ -0,0 +1,136 @@ +#!/bin/csh -f + +set failedi = 0; +set failedx = 0; +set all_testsi = 0; +set all_testsx = 0; + + +set internal_tests=(testall lcall negcnt gcd int2bin cast divmul fib sort sqroot div16u test_xram xram_m timer_test counter_test timer2_test interrupt_test serial_test r_bank) +set external_tests=(testall lcall negcnt gcd int2bin cast divmul fib sort sqroot div16u test_xram xram_m interrupt_test r_bank xrom_test) + +# Prepare all .args files +iteration: +echo "" +echo "" +echo " preparing files" +echo "" + +ncprep -f make > ../out/ncprep.out + +if (`tail -1 ../out/ncprep.out | grep Failed` != "") then + echo "" + cat ../out/ncprep.out + exit +endif + +# Run NC-Verilog compiler +echo "" +echo "\t@@@" +echo "\t@@@ Compiling sources" +echo "\t@@@" + +ncvlog -NOCOPYRIGHT -f ncvlog.args > ../out/ncvlog.out +if ($status != 0) then + echo "\t@@@ FAILED" + echo "" + cat ../out/ncvlog.out + exit +else + echo "\t@@@ Passed" +endif + +# Run the NC-Verilog elaborator (build the design hierarchy) +echo "" +echo "\t@@@" +echo "\t@@@ Building design hierarchy (elaboration)" +echo "\t@@@" +ncelab -NOTIMINGCHECKS -NOCOPYRIGHT -f ncelab.args > ../out/ncelab.out +if ($status != 0) then + echo "\t@@@ FAILED" + echo "" + cat ../out/ncelab.out + exit +else + echo "\t@@@ Passed" +endif + +# Run the NC-Verilog simulator (simulate the design) + +echo "" +echo "\t@@@" +echo "\t@@@ Tesing programs from internal rom" +echo "\t@@@" + +cp ../oc8051_eai.in ../oc8051_ea.in +set i = 0; +foreach internal_test ($internal_tests) + @ i += 1; + echo "" + echo "\t###" + echo "\t### Running test ${i}: ${internal_test}" + echo "\t###" + + cp ../../../asm/in/${internal_test}.in ../../../asm/in/oc8051_rom.in + cp ../../../asm/vec/${internal_test}.vec ../../../asm/vec/oc8051_test.vec + ncsim -NOCOPYRIGHT -f ncsim.args > ../out/ncsim.out + if ($status != 0) then + cat ../out/ncsim.out + exit + else if (`tail -4 ../out/ncsim.out | grep Done` == "") then + echo "\t### FAILED" + @ failedi += 1; + @ all_testsi += 1; + else + echo "\t### Passed" + @ all_testsi += 1; + endif + mv ../out/ncsim.out ../out/${internal_test}.out + + +end + +echo "" +echo "\t@@@" +echo "\t@@@ tesing programs from external rom" +echo "\t@@@" + +cp ../oc8051_eax.in ../oc8051_ea.in +set i = 0; +foreach external_test ($external_tests) + @ i += 1; + echo "" + echo "\t###" + echo "\t### Running test ${i}: ${external_test}" + echo "\t###" + + cp ../../../asm/in/${external_test}.in ../../../asm/in/oc8051_xrom.in + cp ../../../asm/vec/${external_test}.vec ../../../asm/vec/oc8051_test.vec + cp ../oc8051_eax.in ../oc8051_ea.in + ncsim -NOCOPYRIGHT -f ncsim.args > ../out/ncsim.out + if ($status != 0) then + cat ../out/ncsim.out + exit + else if (`tail -4 ../out/ncsim.out | grep Done` == "") then + echo "\t### FAILED" + @ failedx += 1; + @ all_testsx += 1; + else + echo "\t### Passed" + @ all_testsx += 1; + endif + mv ../out/ncsim.out ../out/x_${external_test}.out + +end + + echo "" + echo "\t###" + echo "\t### Failed $failedi of $all_testsi internal tests" + echo "\t###" + echo "\t### Failed $failedx of $all_testsx external tests" + echo "\t###" + +rm cds.lib hdl.var RUN_NC +rm nc* +rm -r INCA_libs +

rtl_sim/run/run Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl_sim/run/make =================================================================== --- rtl_sim/run/make (nonexistent) +++ rtl_sim/run/make (revision 186) @@ -0,0 +1 @@ +../../../bench/verilog/oc8051_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src_sel.v ../../../rtl/verilog/oc8051_alu.v ../../../rtl/verilog/oc8051_decoder.v ../../../rtl/verilog/oc8051_divide.v ../../../rtl/verilog/oc8051_multiply.v ../../../rtl/verilog/oc8051_memory_interface.v ../../../rtl/verilog/oc8051_ram_top.v ../../../sim/rtl_sim/src/verilog/oc8051_xram.v ../../../sim/rtl_sim/src/verilog/oc8051_ram.v ../../../rtl/verilog/oc8051_acc.v ../../../rtl/verilog/oc8051_comp.v ../../../rtl/verilog/oc8051_sp.v ../../../sim/rtl_sim/src/verilog/oc8051_uart_test.v ../../../sim/rtl_sim/src/verilog/oc8051_rom.v ../../../sim/rtl_sim/src/verilog/oc8051_xrom.v ../../../rtl/verilog/oc8051_dptr.v ../../../rtl/verilog/oc8051_cy_select.v ../../../rtl/verilog/oc8051_psw.v ../../../rtl/verilog/oc8051_indi_addr.v ../../../rtl/verilog/oc8051_ports.v ../../../rtl/verilog/oc8051_b_register.v ../../../rtl/verilog/oc8051_uart.v ../../../rtl/verilog/oc8051_int.v ../../../rtl/verilog/oc8051_tc.v ../../../rtl/verilog/oc8051_tc2.v ../../../rtl/verilog/oc8051_icache.v ../src/verilog/oc8051_cache_ram.v ../../../rtl/verilog/oc8051_wb_iinterface.v ../../../rtl/verilog/oc8051_sfr.v

rtl_sim/run/make Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl_sim/run/oc8051_defines.v =================================================================== --- rtl_sim/run/oc8051_defines.v (nonexistent) +++ rtl_sim/run/oc8051_defines.v (revision 186) @@ -0,0 +1,491 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// 8051 cores Definitions //// +//// //// +//// This file is part of the 8051 cores project //// +//// http://www.opencores.org/cores/8051/ //// +//// //// +//// Description //// +//// 8051 definitions. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Simon Teran, simont@opencores.org //// +//// - Jaka Simsic, jakas@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// ver: 1 +// + +// +// oc8051 cache +// +`define OC8051_CACHE + +// +// operation codes for alu +// + + +`define OC8051_ALU_NOP 4'b0000 +`define OC8051_ALU_ADD 4'b0001 +`define OC8051_ALU_SUB 4'b0010 +`define OC8051_ALU_MUL 4'b0011 +`define OC8051_ALU_DIV 4'b0100 +`define OC8051_ALU_DA 4'b0101 +`define OC8051_ALU_NOT 4'b0110 +`define OC8051_ALU_AND 4'b0111 +`define OC8051_ALU_XOR 4'b1000 +`define OC8051_ALU_OR 4'b1001 +`define OC8051_ALU_RL 4'b1010 +`define OC8051_ALU_RLC 4'b1011 +`define OC8051_ALU_RR 4'b1100 +`define OC8051_ALU_RRC 4'b1101 +`define OC8051_ALU_PCS 4'b1110 +`define OC8051_ALU_XCH 4'b1111 + +// +// sfr addresses +// + +`define OC8051_SFR_ACC 8'he0 //accumulator +`define OC8051_SFR_B 8'hf0 //b register +`define OC8051_SFR_PSW 8'hd0 //program status word +`define OC8051_SFR_P0 8'h80 //port 0 +`define OC8051_SFR_P1 8'h90 //port 1 +`define OC8051_SFR_P2 8'ha0 //port 2 +`define OC8051_SFR_P3 8'hb0 //port 3 +`define OC8051_SFR_DPTR_LO 8'h82 // data pointer high bits +`define OC8051_SFR_DPTR_HI 8'h83 // data pointer low bits +`define OC8051_SFR_IP0 8'hb8 // interrupt priority +`define OC8051_SFR_IEN0 8'ha8 // interrupt enable 0 +`define OC8051_SFR_TMOD 8'h89 // timer/counter mode +`define OC8051_SFR_TCON 8'h88 // timer/counter control +`define OC8051_SFR_TH0 8'h8c // timer/counter 0 high bits +`define OC8051_SFR_TL0 8'h8a // timer/counter 0 low bits +`define OC8051_SFR_TH1 8'h8d // timer/counter 1 high bits +`define OC8051_SFR_TL1 8'h8b // timer/counter 1 low bits + +`define OC8051_SFR_SCON 8'h98 // serial control 0 +`define OC8051_SFR_SBUF 8'h99 // serial data buffer 0 +`define OC8051_SFR_SADDR 8'ha9 // serila address register 0 +`define OC8051_SFR_SADEN 8'hb9 // serila address enable 0 + +`define OC8051_SFR_PCON 8'h87 // power control +`define OC8051_SFR_SP 8'h81 // stack pointer + + + +`define OC8051_SFR_IE 8'ha8 // interrupt enable +`define OC8051_SFR_IP 8'hb7 // interrupt priority + +`define OC8051_SFR_RCAP2H 8'hcb // timer 2 capture high +`define OC8051_SFR_RCAP2L 8'hca // timer 2 capture low + +`define OC8051_SFR_T2CON 8'hc8 // timer 2 control register +`define OC8051_SFR_T2MOD 8'hc9 // timer 2 mode control +`define OC8051_SFR_TH2 8'hcd // timer 2 high +`define OC8051_SFR_TL2 8'hcc // timer 2 low + + + +// +// sfr bit addresses +// +`define OC8051_SFR_B_ACC 5'b11100 //accumulator +`define OC8051_SFR_B_PSW 5'b11010 //program status word +`define OC8051_SFR_B_P0 5'b10000 //port 0 +`define OC8051_SFR_B_P1 5'b10010 //port 1 +`define OC8051_SFR_B_P2 5'b10100 //port 2 +`define OC8051_SFR_B_P3 5'b10110 //port 3 +`define OC8051_SFR_B_B 5'b11110 // b register +`define OC8051_SFR_B_IP 5'b10111 // interrupt priority control 0 +`define OC8051_SFR_B_IE 5'b10101 // interrupt enable control 0 +`define OC8051_SFR_B_SCON 5'b10011 // serial control +`define OC8051_SFR_B_TCON 5'b10001 // timer/counter control +`define OC8051_SFR_B_T2CON 5'b11001 // timer/counter2 control + + +// +//carry input in alu +// +`define OC8051_CY_0 2'b00 // 1'b0; +`define OC8051_CY_PSW 2'b01 // carry from psw +`define OC8051_CY_RAM 2'b10 // carry from ram +`define OC8051_CY_1 2'b11 // 1'b1; +`define OC8051_CY_DC 2'b00 // carry from psw + +// +// instruction set +// + +//op_code [4:0] +`define OC8051_ACALL 8'bxxx1_0001 // absolute call +`define OC8051_AJMP 8'bxxx0_0001 // absolute jump + +//op_code [7:3] +`define OC8051_ADD_R 8'b0010_1xxx // add A=A+Rx +`define OC8051_ADDC_R 8'b0011_1xxx // add A=A+Rx+c +`define OC8051_ANL_R 8'b0101_1xxx // and A=A^Rx +`define OC8051_CJNE_R 8'b1011_1xxx // compare and jump if not equal; Rx<>constant +`define OC8051_DEC_R 8'b0001_1xxx // decrement reg Rn=Rn-1 +`define OC8051_DJNZ_R 8'b1101_1xxx // decrement and jump if not zero +`define OC8051_INC_R 8'b0000_1xxx // increment Rn +`define OC8051_MOV_R 8'b1110_1xxx // move A=Rn +`define OC8051_MOV_AR 8'b1111_1xxx // move Rn=A +`define OC8051_MOV_DR 8'b1010_1xxx // move Rn=(direct) +`define OC8051_MOV_CR 8'b0111_1xxx // move Rn=constant +`define OC8051_MOV_RD 8'b1000_1xxx // move (direct)=Rn +`define OC8051_ORL_R 8'b0100_1xxx // or A=A or Rn +`define OC8051_SUBB_R 8'b1001_1xxx // substract with borrow A=A-c-Rn +`define OC8051_XCH_R 8'b1100_1xxx // exchange A<->Rn +`define OC8051_XRL_R 8'b0110_1xxx // XOR A=A XOR Rn + +//op_code [7:1] +`define OC8051_ADD_I 8'b0010_011x // add A=A+@Ri +`define OC8051_ADDC_I 8'b0011_011x // add A=A+@Ri+c +`define OC8051_ANL_I 8'b0101_011x // and A=A^@Ri +`define OC8051_CJNE_I 8'b1011_011x // compare and jump if not equal; @Ri<>constant +`define OC8051_DEC_I 8'b0001_011x // decrement indirect @Ri=@Ri-1 +`define OC8051_INC_I 8'b0000_011x // increment @Ri +`define OC8051_MOV_I 8'b1110_011x // move A=@Ri +`define OC8051_MOV_ID 8'b1000_011x // move (direct)=@Ri +`define OC8051_MOV_AI 8'b1111_011x // move @Ri=A +`define OC8051_MOV_DI 8'b1010_011x // move @Ri=(direct) +`define OC8051_MOV_CI 8'b0111_011x // move @Ri=constant +`define OC8051_MOVX_IA 8'b1110_001x // move A=(@Ri) +`define OC8051_MOVX_AI 8'b1111_001x // move (@Ri)=A +`define OC8051_ORL_I 8'b0100_011x // or A=A or @Ri +`define OC8051_SUBB_I 8'b1001_011x // substract with borrow A=A-c-@Ri +`define OC8051_XCH_I 8'b1100_011x // exchange A<->@Ri +`define OC8051_XCHD 8'b1101_011x // exchange digit A<->Ri +`define OC8051_XRL_I 8'b0110_011x // XOR A=A XOR @Ri + +//op_code [7:0] +`define OC8051_ADD_D 8'b0010_0101 // add A=A+(direct) +`define OC8051_ADD_C 8'b0010_0100 // add A=A+constant +`define OC8051_ADDC_D 8'b0011_0101 // add A=A+(direct)+c +`define OC8051_ADDC_C 8'b0011_0100 // add A=A+constant+c +`define OC8051_ANL_D 8'b0101_0101 // and A=A^(direct) +`define OC8051_ANL_C 8'b0101_0100 // and A=A^constant +`define OC8051_ANL_DD 8'b0101_0010 // and (direct)=(direct)^A +`define OC8051_ANL_DC 8'b0101_0011 // and (direct)=(direct)^constant +`define OC8051_ANL_B 8'b1000_0010 // and c=c^bit +`define OC8051_ANL_NB 8'b1011_0000 // and c=c^!bit +`define OC8051_CJNE_D 8'b1011_0101 // compare and jump if not equal; a<>(direct) +`define OC8051_CJNE_C 8'b1011_0100 // compare and jump if not equal; a<>constant +`define OC8051_CLR_A 8'b1110_0100 // clear accumulator +`define OC8051_CLR_C 8'b1100_0011 // clear carry +`define OC8051_CLR_B 8'b1100_0010 // clear bit +`define OC8051_CPL_A 8'b1111_0100 // complement accumulator +`define OC8051_CPL_C 8'b1011_0011 // complement carry +`define OC8051_CPL_B 8'b1011_0010 // complement bit +`define OC8051_DA 8'b1101_0100 // decimal adjust (A) +`define OC8051_DEC_A 8'b0001_0100 // decrement accumulator a=a-1 +`define OC8051_DEC_D 8'b0001_0101 // decrement direct (direct)=(direct)-1 +`define OC8051_DIV 8'b1000_0100 // divide +`define OC8051_DJNZ_D 8'b1101_0101 // decrement and jump if not zero (direct) +`define OC8051_INC_A 8'b0000_0100 // increment accumulator +`define OC8051_INC_D 8'b0000_0101 // increment (direct) +`define OC8051_INC_DP 8'b1010_0011 // increment data pointer +`define OC8051_JB 8'b0010_0000 // jump if bit set +`define OC8051_JBC 8'b0001_0000 // jump if bit set and clear bit +`define OC8051_JC 8'b0100_0000 // jump if carry is set +`define OC8051_JMP_D 8'b0111_0011 // jump indirect +`define OC8051_JNB 8'b0011_0000 // jump if bit not set +`define OC8051_JNC 8'b0101_0000 // jump if carry not set +`define OC8051_JNZ 8'b0111_0000 // jump if accumulator not zero +`define OC8051_JZ 8'b0110_0000 // jump if accumulator zero +`define OC8051_LCALL 8'b0001_0010 // long call +`define OC8051_LJMP 8'b0000_0010 // long jump +`define OC8051_MOV_D 8'b1110_0101 // move A=(direct) +`define OC8051_MOV_C 8'b0111_0100 // move A=constant +`define OC8051_MOV_DA 8'b1111_0101 // move (direct)=A +`define OC8051_MOV_DD 8'b1000_0101 // move (direct)=(direct) +`define OC8051_MOV_CD 8'b0111_0101 // move (direct)=constant +`define OC8051_MOV_BC 8'b1010_0010 // move c=bit +`define OC8051_MOV_CB 8'b1001_0010 // move bit=c +`define OC8051_MOV_DP 8'b1001_0000 // move dptr=constant(16 bit) +`define OC8051_MOVC_DP 8'b1001_0011 // move A=dptr+A +`define OC8051_MOVC_PC 8'b1000_0011 // move A=pc+A +`define OC8051_MOVX_PA 8'b1110_0000 // move A=(dptr) +`define OC8051_MOVX_AP 8'b1111_0000 // move (dptr)=A +`define OC8051_MUL 8'b1010_0100 // multiply a*b +`define OC8051_NOP 8'b0000_0000 // no operation +`define OC8051_ORL_D 8'b0100_0101 // or A=A or (direct) +`define OC8051_ORL_C 8'b0100_0100 // or A=A or constant +`define OC8051_ORL_AD 8'b0100_0010 // or (direct)=(direct) or A +`define OC8051_ORL_CD 8'b0100_0011 // or (direct)=(direct) or constant +`define OC8051_ORL_B 8'b0111_0010 // or c = c or bit +`define OC8051_ORL_NB 8'b1010_0000 // or c = c or !bit +`define OC8051_POP 8'b1101_0000 // stack pop +`define OC8051_PUSH 8'b1100_0000 // stack push +`define OC8051_RET 8'b0010_0010 // return from subrutine +`define OC8051_RETI 8'b0011_0010 // return from interrupt +`define OC8051_RL 8'b0010_0011 // rotate left +`define OC8051_RLC 8'b0011_0011 // rotate left thrugh carry +`define OC8051_RR 8'b0000_0011 // rotate right +`define OC8051_RRC 8'b0001_0011 // rotate right thrugh carry +`define OC8051_SETB_C 8'b1101_0011 // set carry +`define OC8051_SETB_B 8'b1101_0010 // set bit +`define OC8051_SJMP 8'b1000_0000 // short jump +`define OC8051_SUBB_D 8'b1001_0101 // substract with borrow A=A-c-(direct) +`define OC8051_SUBB_C 8'b1001_0100 // substract with borrow A=A-c-constant +`define OC8051_SWAP 8'b1100_0100 // swap A(0-3) <-> A(4-7) +`define OC8051_XCH_D 8'b1100_0101 // exchange A<->(direct) +`define OC8051_XRL_D 8'b0110_0101 // XOR A=A XOR (direct) +`define OC8051_XRL_C 8'b0110_0100 // XOR A=A XOR constant +`define OC8051_XRL_AD 8'b0110_0010 // XOR (direct)=(direct) XOR A +`define OC8051_XRL_CD 8'b0110_0011 // XOR (direct)=(direct) XOR constant + + +// +// default values (used after reset) +// +`define OC8051_RST_PC 23'h0 // program counter +`define OC8051_RST_ACC 8'h00 // accumulator +`define OC8051_RST_B 8'h00 // b register +`define OC8051_RST_PSW 8'h00 // program status word +`define OC8051_RST_SP 8'b0000_0111 // stack pointer +`define OC8051_RST_DPH 8'h00 // data pointer (high) +`define OC8051_RST_DPL 8'h00 // data pointer (low) +`define OC8051_RST_P0 8'b1111_1111 // port 0 +`define OC8051_RST_P1 8'b1111_1111 // port 1 +`define OC8051_RST_P2 8'b1111_1111 // port 2 +`define OC8051_RST_P3 8'b1111_1111 // port 3 +`define OC8051_RST_IP 8'b0000_0000 // interrupt priority +`define OC8051_RST_IE 8'b0000_0000 // interrupt enable +`define OC8051_RST_TMOD 8'b0000_0000 // timer/counter mode control +`define OC8051_RST_TCON 8'b0000_0000 // timer/counter control +`define OC8051_RST_TH0 8'b0000_0000 // timer/counter 0 high bits +`define OC8051_RST_TL0 8'b0000_0000 // timer/counter 0 low bits +`define OC8051_RST_TH1 8'b0000_0000 // timer/counter 1 high bits +`define OC8051_RST_TL1 8'b0000_0000 // timer/counter 1 low bits +`define OC8051_RST_SCON 8'b0000_0000 // serial control +`define OC8051_RST_SBUF 8'b0000_0000 // serial data buffer +`define OC8051_RST_PCON 8'b0000_0000 // power control register + + + +`define OC8051_RST_RCAP2H 8'h00 // timer 2 capture high +`define OC8051_RST_RCAP2L 8'h00 // timer 2 capture low + +`define OC8051_RST_T2CON 8'h00 // timer 2 control register +`define OC8051_RST_T2MOD 8'h00 // timer 2 mode control +`define OC8051_RST_TH2 8'h00 // timer 2 high +`define OC8051_RST_TL2 8'h00 // timer 2 low + + +// +// alu source 1 select +// +`define OC8051_AS1_RAM 3'b000 // RAM +`define OC8051_AS1_OP1 3'b111 // +`define OC8051_AS1_OP2 3'b001 // +`define OC8051_AS1_OP3 3'b010 // +`define OC8051_AS1_ACC 3'b011 // accumulator +`define OC8051_AS1_PCH 3'b100 // +`define OC8051_AS1_PCL 3'b101 // +`define OC8051_AS1_DC 3'b000 // + +// +// alu source 2 select +// +`define OC8051_AS2_RAM 3'b000 // RAM +`define OC8051_AS2_ACC 3'b001 // accumulator +`define OC8051_AS2_ZERO 3'b010 // 8'h00 +`define OC8051_AS2_OP2 3'b011 // +`define OC8051_AS2_PCL 3'b100 // + +`define OC8051_AS2_DC 3'b000 // + +// +// alu source 3 select +// +`define OC8051_AS3_DP 1'b0 // data pointer +`define OC8051_AS3_PC 1'b1 // program clunter +//`define OC8051_AS3_PCU 3'b101 // program clunter not registered +`define OC8051_AS3_DC 1'b0 // + + +// +//write sfr +// +`define OC8051_WRS_N 3'b000 //no +`define OC8051_WRS_ACC1 3'b001 // acc destination 1 +`define OC8051_WRS_ACC2 3'b010 // acc destination 2 +`define OC8051_WRS_DPTR 3'b011 // data pointer +`define OC8051_WRS_BA 3'b100 // a, b register + + +// +// ram read select +// + +`define OC8051_RRS_RN 3'b000 // registers +`define OC8051_RRS_I 3'b001 // indirect addressing (op2) +`define OC8051_RRS_D 3'b010 // direct addressing +`define OC8051_RRS_SP 3'b011 // stack pointer + +`define OC8051_RRS_B 3'b100 // b register +`define OC8051_RRS_DPTR 3'b101 // data pointer + +`define OC8051_RRS_DC 3'b000 // don't c + +// +// ram write select +// + +`define OC8051_RWS_RN 3'b000 // registers +`define OC8051_RWS_D 3'b001 // direct addressing +`define OC8051_RWS_I 3'b010 // indirect addressing +`define OC8051_RWS_SP 3'b011 // stack pointer +`define OC8051_RWS_D3 3'b101 // direct address (op3) +`define OC8051_RWS_D1 3'b110 // direct address (op1) +`define OC8051_RWS_DC 3'b000 // + +// +// pc in select +// +`define OC8051_PIS_DC 3'b000 // dont c +`define OC8051_PIS_AL 3'b000 // alu low +`define OC8051_PIS_AH 3'b001 // alu high +`define OC8051_PIS_ALU 3'b010 // alu {des1, des2} +`define OC8051_PIS_I11 3'b011 // 11 bit immediate +`define OC8051_PIS_I16 3'b100 // 16 bit immediate + +// +// compare source select +// +`define OC8051_CSS_AZ 2'b00 // eq = accumulator == zero +`define OC8051_CSS_DES 2'b01 // eq = destination == zero +`define OC8051_CSS_CY 2'b10 // eq = cy +`define OC8051_CSS_BIT 2'b11 // eq = b_in +`define OC8051_CSS_DC 2'b00 // don't care + + +// +// pc Write +// +`define OC8051_PCW_N 1'b0 // not +`define OC8051_PCW_Y 1'b1 // yes + +// +//psw set +// +`define OC8051_PS_NOT 2'b00 // DONT +`define OC8051_PS_CY 2'b01 // only carry +`define OC8051_PS_OV 2'b10 // carry and overflov +`define OC8051_PS_AC 2'b11 // carry, overflov an ac... + +// +// rom address select +// +`define OC8051_RAS_PC 1'b0 // program counter +`define OC8051_RAS_DES 1'b1 // alu destination + +//// +//// write accumulator +//// +//`define OC8051_WA_N 1'b0 // not +//`define OC8051_WA_Y 1'b1 // yes + + +// +//memory action select +// +`define OC8051_MAS_DPTR_R 3'b000 // read from external rom: acc=(dptr) +`define OC8051_MAS_DPTR_W 3'b001 // write to external rom: (dptr)=acc +`define OC8051_MAS_RI_R 3'b010 // read from external rom: acc=(Ri) +`define OC8051_MAS_RI_W 3'b011 // write to external rom: (Ri)=acc +`define OC8051_MAS_CODE 3'b100 // read from program memory +`define OC8051_MAS_NO 3'b111 // no action + + +//////////////////////////////////////////////////// + +// +// Timer/Counter modes +// + +`define OC8051_MODE0 2'b00 // mode 0 +`define OC8051_MODE1 2'b01 // mode 0 +`define OC8051_MODE2 2'b10 // mode 0 +`define OC8051_MODE3 2'b11 // mode 0 + + +// +// Interrupt numbers (vectors) +// + +`define OC8051_INT_X0 8'h03 // external interrupt 0 +`define OC8051_INT_T0 8'h0b // T/C 0 owerflow interrupt +`define OC8051_INT_X1 8'h13 // external interrupt 1 +`define OC8051_INT_T1 8'h1b // T/C 1 owerflow interrupt +`define OC8051_INT_UART 8'h23 // uart interrupt +`define OC8051_INT_T2 8'h2b // T/C 2 owerflow interrupt + + +// +// interrupt levels +// + +`define OC8051_ILEV_L0 1'b0 // interrupt on level 0 +`define OC8051_ILEV_L1 1'b1 // interrupt on level 1 + +// +// interrupt sources +// +`define OC8051_ISRC_NO 3'b000 // no interrupts +`define OC8051_ISRC_IE0 3'b001 // EXTERNAL INTERRUPT 0 +`define OC8051_ISRC_TF0 3'b010 // t/c owerflov 0 +`define OC8051_ISRC_IE1 3'b011 // EXTERNAL INTERRUPT 1 +`define OC8051_ISRC_TF1 3'b100 // t/c owerflov 1 +`define OC8051_ISRC_UART 3'b101 // UART Interrupt +`define OC8051_ISRC_T2 3'b110 // t/c owerflov 2 + + + +// +// miscellaneus +// + +`define OC8051_RW0 1'b1 +`define OC8051_RW1 1'b0 + + +// +// read modify write instruction +// + +`define OC8051_RMW_Y 1'b1 // yes +`define OC8051_RMW_N 1'b0 // no +

rtl_sim/run/oc8051_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl_sim/run/verilog.log =================================================================== --- rtl_sim/run/verilog.log (nonexistent) +++ rtl_sim/run/verilog.log (revision 186) @@ -0,0 +1,295 @@ +Host command: /shared/tools/ncsim/tools/verilog/bin/verilog.exe +Command arguments: + ../../../bench/verilog/oc8051_tb.v + ../../../rtl/verilog/oc8051_top.v + ../../../rtl/verilog/oc8051_alu_src1_sel.v + ../../../rtl/verilog/oc8051_alu_src2_sel.v + ../../../rtl/verilog/oc8051_alu_src3_sel.v + ../../../rtl/verilog/oc8051_alu.v + ../../../rtl/verilog/oc8051_decoder.v + ../../../rtl/verilog/oc8051_divide.v + ../../../rtl/verilog/oc8051_immediate_sel.v + ../../../rtl/verilog/oc8051_multiply.v + ../../../rtl/verilog/oc8051_op_select.v + ../../../rtl/verilog/oc8051_pc.v + ../../../rtl/verilog/oc8051_reg8.v + ../../../rtl/verilog/oc8051_reg2.v + ../../../rtl/verilog/oc8051_reg1.v + ../../../rtl/verilog/oc8051_reg4.v + ../../../rtl/verilog/oc8051_ram_wr_sel.v + ../../../rtl/verilog/oc8051_ram_rd_sel.v + ../../../rtl/verilog/oc8051_ram_top.v + ../../../sim/rtl_sim/src/verilog/oc8051_ram.v + ../../../sim/rtl_sim/src/verilog/oc8051_xram.v + ../../../rtl/verilog/oc8051_acc.v + ../../../rtl/verilog/oc8051_comp.v + ../../../rtl/verilog/oc8051_sp.v + ../../../sim/rtl_sim/src/verilog/oc8051_uart_test.v + ../../../sim/rtl_sim/src/verilog/oc8051_rom.v + ../../../rtl/verilog/oc8051_dptr.v + ../../../rtl/verilog/oc8051_cy_select.v + ../../../rtl/verilog/oc8051_psw.v + ../../../rtl/verilog/oc8051_indi_addr.v + ../../../rtl/verilog/oc8051_rom_addr_sel.v + ../../../rtl/verilog/oc8051_ext_addr_sel.v + ../../../rtl/verilog/oc8051_reg3.v + ../../../rtl/verilog/oc8051_ram_sel.v + ../../../rtl/verilog/oc8051_ports.v + ../../../rtl/verilog/oc8051_b_register.v + ../../../rtl/verilog/oc8051_uart.v + ../../../rtl/verilog/oc8051_int.v + ../../../rtl/verilog/oc8051_tc.v + +VERILOG-XL 3.30.p001 log file created Aug 3, 2001 12:27:17 +VERILOG-XL 3.30.p001 Aug 3, 2001 12:27:17 + +Copyright (c) 1995 Cadence Design Systems, Inc. All Rights Reserved. +Unpublished -- rights reserved under the copyright laws of the United States. + +Copyright (c) 1995 UNIX Systems Laboratories, Inc. Reproduced with Permission. + +THIS SOFTWARE AND ON-LINE DOCUMENTATION CONTAIN CONFIDENTIAL INFORMATION +AND TRADE SECRETS OF CADENCE DESIGN SYSTEMS, INC. USE, DISCLOSURE, OR +REPRODUCTION IS PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF +CADENCE DESIGN SYSTEMS, INC. +RESTRICTED RIGHTS LEGEND + +Use, duplication, or disclosure by the Government is subject to +restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in +Technical Data and Computer Software clause at DFARS 252.227-7013 or +subparagraphs (c)(1) and (2) of Commercial Computer Software -- Restricted +Rights at 48 CFR 52.227-19, as applicable. + + Cadence Design Systems, Inc. + 555 River Oaks Parkway + San Jose, California 95134 + +For technical assistance please contact the Cadence Response Center at +1-877-CDS-4911 or send email to support@cadence.com + +For more information on Cadence's Verilog-XL product line send email to +talkv@cadence.com + +Compiling source file "../../../bench/verilog/oc8051_tb.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../bench/verilog/oc8051_tb.v" +Compiling source file "../../../rtl/verilog/oc8051_top.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_top.v" +Compiling source file "../../../rtl/verilog/oc8051_alu_src1_sel.v" + +Warning! Code following `include command is ignored [Verilog-CAICI] + "../../../rtl/verilog/oc8051_alu_src1_sel.v", + 48: +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_alu_src1_sel.v" + +Warning! Code following `include command is ignored [Verilog-CAICI] + "../../../rtl/verilog/oc8051_alu_src1_sel.v", + 51: +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_alu_src1_sel.v" +Compiling source file "../../../rtl/verilog/oc8051_alu_src2_sel.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_alu_src2_sel.v" +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_alu_src2_sel.v" +Compiling source file "../../../rtl/verilog/oc8051_alu_src3_sel.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_alu_src3_sel.v" +Compiling source file "../../../rtl/verilog/oc8051_alu.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_alu.v" +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_alu.v" +Compiling source file "../../../rtl/verilog/oc8051_decoder.v" + +Warning! Code following `include command is ignored [Verilog-CAICI] + "../../../rtl/verilog/oc8051_decoder.v", 49: +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_decoder.v" + +Warning! Code following `include command is ignored [Verilog-CAICI] + "../../../rtl/verilog/oc8051_decoder.v", 52: +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_decoder.v" +Compiling source file "../../../rtl/verilog/oc8051_divide.v" + +Warning! Code following `include command is ignored [Verilog-CAICI] + "../../../rtl/verilog/oc8051_divide.v", 51: +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_divide.v" +Compiling source file "../../../rtl/verilog/oc8051_immediate_sel.v" + +Warning! Code following `include command is ignored [Verilog-CAICI] + "../../../rtl/verilog/oc8051_immediate_sel.v", + 49: +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_immediate_sel.v" + +Warning! Code following `include command is ignored [Verilog-CAICI] + "../../../rtl/verilog/oc8051_immediate_sel.v", + 52: +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_immediate_sel.v" +Compiling source file "../../../rtl/verilog/oc8051_multiply.v" + +Warning! Code following `include command is ignored [Verilog-CAICI] + "../../../rtl/verilog/oc8051_multiply.v", 56: +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_multiply.v" +Compiling source file "../../../rtl/verilog/oc8051_op_select.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_op_select.v" +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_op_select.v" +Compiling source file "../../../rtl/verilog/oc8051_pc.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_pc.v" +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_pc.v" +Compiling source file "../../../rtl/verilog/oc8051_reg8.v" + +Warning! Code following `include command is ignored [Verilog-CAICI] + "../../../rtl/verilog/oc8051_reg8.v", 48: +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_reg8.v" +Compiling source file "../../../rtl/verilog/oc8051_reg2.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_reg2.v" +Compiling source file "../../../rtl/verilog/oc8051_reg1.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_reg1.v" +Compiling source file "../../../rtl/verilog/oc8051_reg4.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_reg4.v" +Compiling source file "../../../rtl/verilog/oc8051_ram_wr_sel.v" + +Warning! Code following `include command is ignored [Verilog-CAICI] + "../../../rtl/verilog/oc8051_ram_wr_sel.v", 48: +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_ram_wr_sel.v" + +Warning! Code following `include command is ignored [Verilog-CAICI] + "../../../rtl/verilog/oc8051_ram_wr_sel.v", 51: +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_ram_wr_sel.v" +Compiling source file "../../../rtl/verilog/oc8051_ram_rd_sel.v" + +Warning! Code following `include command is ignored [Verilog-CAICI] + "../../../rtl/verilog/oc8051_ram_rd_sel.v", 48: +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_ram_rd_sel.v" + +Warning! Code following `include command is ignored [Verilog-CAICI] + "../../../rtl/verilog/oc8051_ram_rd_sel.v", 51: +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_ram_rd_sel.v" +Compiling source file "../../../rtl/verilog/oc8051_ram_top.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_ram_top.v" +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_ram_top.v" +Compiling source file "../../../sim/rtl_sim/src/verilog/oc8051_ram.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../sim/rtl_sim/src/verilog/oc8051_ram.v" +Compiling source file "../../../sim/rtl_sim/src/verilog/oc8051_xram.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../sim/rtl_sim/src/verilog/oc8051_xram.v" +Compiling source file "../../../rtl/verilog/oc8051_acc.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_acc.v" +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_acc.v" +Compiling source file "../../../rtl/verilog/oc8051_comp.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_comp.v" +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_comp.v" +Compiling source file "../../../rtl/verilog/oc8051_sp.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_sp.v" +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_sp.v" +Compiling source file "../../../sim/rtl_sim/src/verilog/oc8051_uart_test.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../sim/rtl_sim/src/verilog/oc8051_uart_test.v" +Compiling source file "../../../sim/rtl_sim/src/verilog/oc8051_rom.v" +Compiling source file "../../../rtl/verilog/oc8051_dptr.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_dptr.v" +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_dptr.v" +Compiling source file "../../../rtl/verilog/oc8051_cy_select.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_cy_select.v" +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_cy_select.v" +Compiling source file "../../../rtl/verilog/oc8051_psw.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_psw.v" +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_psw.v" +Compiling source file "../../../rtl/verilog/oc8051_indi_addr.v" + +Warning! Code following `include command is ignored [Verilog-CAICI] + "../../../rtl/verilog/oc8051_indi_addr.v", 49: +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_indi_addr.v" +Compiling source file "../../../rtl/verilog/oc8051_rom_addr_sel.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_rom_addr_sel.v" +Compiling source file "../../../rtl/verilog/oc8051_ext_addr_sel.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_ext_addr_sel.v" +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_ext_addr_sel.v" +Compiling source file "../../../rtl/verilog/oc8051_reg3.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_reg3.v" +Compiling source file "../../../rtl/verilog/oc8051_ram_sel.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_ram_sel.v" +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_ram_sel.v" +Compiling source file "../../../rtl/verilog/oc8051_ports.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_ports.v" +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_ports.v" +Compiling source file "../../../rtl/verilog/oc8051_b_register.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_b_register.v" +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_b_register.v" +Compiling source file "../../../rtl/verilog/oc8051_uart.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_uart.v" +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_uart.v" +Compiling source file "../../../rtl/verilog/oc8051_int.v" +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_int.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_int.v" +Compiling source file "../../../rtl/verilog/oc8051_tc.v" +Compiling included source file "oc8051_defines.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_tc.v" +Compiling included source file "oc8051_timescale.v" +Continuing compilation of source file "../../../rtl/verilog/oc8051_tc.v" +Highest level modules: +oc8051_tb + +time 1 step 0: pass +time 186 step 1: pass +time 306 step 2: pass +time 426 step 3: pass +time 546 step 4: pass +time 656 step 5: pass + + Done! +L155 "../../../bench/verilog/oc8051_tb.v": $finish at simulation time 65600 +14 warnings +0 simulation events (use +profile or +listcounts option to count) +CPU time: 0.3 secs to compile + 0.1 secs to link + 0.1 secs in simulation +End of VERILOG-XL 3.30.p001 Aug 3, 2001 12:27:19 Index: rtl_sim/run/oc8051_timescale.v =================================================================== --- rtl_sim/run/oc8051_timescale.v (nonexistent) +++ rtl_sim/run/oc8051_timescale.v (revision 186) @@ -0,0 +1,3 @@ + + +`timescale 1ns/10ps

rtl_sim/run/oc8051_timescale.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl_sim/run/make_fpga =================================================================== --- rtl_sim/run/make_fpga (nonexistent) +++ rtl_sim/run/make_fpga (revision 186) @@ -0,0 +1 @@ +verilog ../../../syn/src/verilog/oc8051_fpga_top.v ../../../bench/verilog/oc8051_fpga_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src1_sel.v ../../../rtl/verilog/oc8051_alu_src2_sel.v ../../../rtl/verilog/oc8051_alu_src3_sel.v ../../../rtl/verilog/oc8051_alu.v ../../../rtl/verilog/oc8051_decoder.v ../../../rtl/verilog/oc8051_divide.v ../../../rtl/verilog/oc8051_immediate_sel.v ../../../rtl/verilog/oc8051_multiply.v ../../../rtl/verilog/oc8051_op_select.v ../../../rtl/verilog/oc8051_pc.v ../../../rtl/verilog/oc8051_reg8.v ../../../rtl/verilog/oc8051_reg2.v ../../../rtl/verilog/oc8051_reg1.v ../../../rtl/verilog/oc8051_reg4.v ../../../rtl/verilog/oc8051_ram_wr_sel.v ../../../rtl/verilog/oc8051_ram_rd_sel.v ../../../rtl/verilog/oc8051_ram_top.v ../../../sim/rtl_sim/src/verilog/oc8051_ram.v ../../../rtl/verilog/oc8051_acc.v ../../../rtl/verilog/oc8051_comp.v ../../../rtl/verilog/oc8051_sp.v ../../../sim/rtl_sim/src/verilog/oc8051_rom.v ../../../rtl/verilog/oc8051_dptr.v ../../../rtl/verilog/oc8051_cy_select.v ../../../rtl/verilog/oc8051_psw.v ../../../rtl/verilog/oc8051_indi_addr.v ../../../rtl/verilog/oc8051_reg5.v ../../../rtl/verilog/oc8051_rom_addr_sel.v ../../../rtl/verilog/oc8051_ext_addr_sel.v ../../../rtl/verilog/oc8051_reg3.v ../../../rtl/verilog/oc8051_ram_sel.v ../../../rtl/verilog/oc8051_ports.v ../../../syn/src/verilog/disp.v

rtl_sim/run/make_fpga Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl_sim/oc8051_eax.in =================================================================== --- rtl_sim/oc8051_eax.in (nonexistent) +++ rtl_sim/oc8051_eax.in (revision 186) @@ -0,0 +1,8 @@ +/// +/// input for external access (ea signal) +/// +/// ea=0 program is in external rom +/// ea=1 program is in internal rom +/// +/// +0 Index: rtl_sim/oc8051_eai.in =================================================================== --- rtl_sim/oc8051_eai.in (nonexistent) +++ rtl_sim/oc8051_eai.in (revision 186) @@ -0,0 +1,8 @@ +/// +/// input for external access (ea signal) +/// +/// ea=0 program is in external rom +/// ea=1 program is in internal rom +/// +/// +1 Index: rtl_sim/oc8051_ea.in =================================================================== --- rtl_sim/oc8051_ea.in (nonexistent) +++ rtl_sim/oc8051_ea.in (revision 186) @@ -0,0 +1,8 @@ +/// +/// input for external access (ea signal) +/// +/// ea=0 program is in external rom +/// ea=1 program is in internal rom +/// +/// +0 Index: rtl_sim/out/counter_test.out =================================================================== --- rtl_sim/out/counter_test.out (nonexistent) +++ rtl_sim/out/counter_test.out (revision 186) @@ -0,0 +1,17 @@ +Loading snapshot worklib.oc8051_tb:v .................... Done +ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc +ncsim> run + +Warning! some objects excluded from $dumpvars due to -access -R + File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16 + Scope: oc8051_tb + Time: 0 FS + 0 + +time 1 step 0: pass +time 5216 step 1: pass +time 9546 step 2: pass + + Done! +Simulation complete via $finish(1) at time 9546 NS + 2 +/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155 $finish; +ncsim> exit Index: rtl_sim/out/div16u.out =================================================================== --- rtl_sim/out/div16u.out (nonexistent) +++ rtl_sim/out/div16u.out (revision 186) @@ -0,0 +1,26 @@ +Loading snapshot worklib.oc8051_tb:v .................... Done +ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc +ncsim> run + +Warning! some objects excluded from $dumpvars due to -access -R + File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16 + Scope: oc8051_tb + Time: 0 FS + 0 + +time 1 step 0: pass +time 4566 step 1: pass +time 4576 step 2: pass +time 4586 step 3: pass +time 4596 step 4: pass +time 4666 step 5: pass +time 4676 step 6: pass +time 4946 step 7: pass +time 4956 step 8: pass +time 5096 step 9: pass +time 5106 step 10: pass +time 5186 step 11: pass + + Done! +Simulation complete via $finish(1) at time 5186 NS + 2 +/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155 $finish; +ncsim> exit Index: rtl_sim/out/negcnt.out =================================================================== --- rtl_sim/out/negcnt.out (nonexistent) +++ rtl_sim/out/negcnt.out (revision 186) @@ -0,0 +1,25 @@ +Loading snapshot worklib.oc8051_tb:v .................... Done +ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc +ncsim> run + +Warning! some objects excluded from $dumpvars due to -access -R + File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16 + Scope: oc8051_tb + Time: 0 FS + 0 + +time 1 step 0: pass +time 6496 step 1: pass +time 6646 step 2: pass +time 6796 step 3: pass +time 6946 step 4: pass +time 7096 step 5: pass +time 7246 step 6: pass +time 7396 step 7: pass +time 7546 step 8: pass +time 7696 step 9: pass +time 7846 step 10: pass + + Done! +Simulation complete via $finish(1) at time 7846 NS + 2 +/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155 $finish; +ncsim> exit Index: rtl_sim/out/serial_test.out =================================================================== --- rtl_sim/out/serial_test.out (nonexistent) +++ rtl_sim/out/serial_test.out (revision 186) @@ -0,0 +1,19 @@ +Loading snapshot worklib.oc8051_tb:v .................... Done +ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc +ncsim> run + +Warning! some objects excluded from $dumpvars due to -access -R + File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16 + Scope: oc8051_tb + Time: 0 FS + 0 + +time 1 step 0: pass +time 3416 step 1: pass +time 213656 step 2: pass +time 243546 step 3: pass +time 359246 step 4: pass + + Done! +Simulation complete via $finish(1) at time 359246 NS + 2 +/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155 $finish; +ncsim> exit Index: rtl_sim/out/timer_test.out =================================================================== --- rtl_sim/out/timer_test.out (nonexistent) +++ rtl_sim/out/timer_test.out (revision 186) @@ -0,0 +1,17 @@ +Loading snapshot worklib.oc8051_tb:v .................... Done +ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc +ncsim> run + +Warning! some objects excluded from $dumpvars due to -access -R + File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16 + Scope: oc8051_tb + Time: 0 FS + 0 + +time 1 step 0: pass +time 4686 step 1: pass +time 8426 step 2: pass + + Done! +Simulation complete via $finish(1) at time 8426 NS + 2 +/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155 $finish; +ncsim> exit Index: rtl_sim/out/xram_m.out =================================================================== --- rtl_sim/out/xram_m.out (nonexistent) +++ rtl_sim/out/xram_m.out (revision 186) @@ -0,0 +1,16 @@ +Loading snapshot worklib.oc8051_tb:v .................... Done +ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc +ncsim> run + +Warning! some objects excluded from $dumpvars due to -access -R + File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16 + Scope: oc8051_tb + Time: 0 FS + 0 + +time 1 step 0: pass +time 1199286 step 1: pass + + Done! +Simulation complete via $finish(1) at time 1199286 NS + 2 +/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155 $finish; +ncsim> exit Index: rtl_sim/out/ncelab.out =================================================================== --- rtl_sim/out/ncelab.out (nonexistent) +++ rtl_sim/out/ncelab.out (revision 186) @@ -0,0 +1,109 @@ + Elaborating the design hierarchy: + Caching library 'worklib' ....... Done + Building instance overlay tables: + $readmemh("../src/oc8051_test.vec", buff); + | +ncelab: *W,MEMODR (/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v,133|41): $readmem default memory order incompatible with IEEE1364. +.............. + $readmemh("../src/oc8051_rom.in", buff); + | +ncelab: *W,MEMODR (../src/verilog/oc8051_rom.v,34|39): $readmem default memory order incompatible with IEEE1364. +...... Done + Generating native compiled code: + worklib.oc0851_int:v <0x42e3c287> + streams: 102, words: 76709 + worklib.oc8051_acc:v <0x1240b0c4> + streams: 12, words: 9266 + worklib.oc8051_alu:v <0x36548d1c> + streams: 19, words: 31722 + worklib.oc8051_alu_src1_sel:v <0x49045171> + streams: 1, words: 1014 + worklib.oc8051_alu_src2_sel:v <0x7e59f8f4> + streams: 1, words: 962 + worklib.oc8051_alu_src3_sel:v <0x4a887dff> + streams: 1, words: 396 + worklib.oc8051_b_register:v <0x7f8909e8> + streams: 9, words: 7095 + worklib.oc8051_comp:v <0x32453df9> + streams: 1, words: 1188 + worklib.oc8051_cy_select:v <0x3920b7c3> + streams: 1, words: 924 + worklib.oc8051_decoder:v <0x28b2f0c5> + streams: 37, words: 374153 + worklib.oc8051_divide:v <0x6c098db6> + streams: 15, words: 7930 + worklib.oc8051_dptr:v <0x3105e8b6> + streams: 7, words: 5614 + worklib.oc8051_ext_addr_sel:v <0x6603647c> + streams: 8, words: 4449 + worklib.oc8051_immediate_sel:v <0x5b114496> + streams: 10, words: 8328 + worklib.oc8051_indi_addr:v <0x4d1dae6d> + streams: 2, words: 5837 + worklib.oc8051_multiply:v <0x2c1d9278> + streams: 10, words: 5525 + worklib.oc8051_op_select:v <0x6dcc019b> + streams: 25, words: 14949 + worklib.oc8051_pc:v <0x07ddc3c8> + streams: 19, words: 25611 + worklib.oc8051_ports:v <0x0c7b97ea> + streams: 36, words: 32841 + worklib.oc8051_psw:v <0x0ba437aa> + streams: 18, words: 16488 + worklib.oc8051_ram:v <0x276638b3> + streams: 8, words: 4982 + worklib.oc8051_ram_rd_sel:v <0x2da76cf3> + streams: 1, words: 1899 + worklib.oc8051_ram_sel:v <0x2c8f228b> + streams: 2, words: 4403 + worklib.oc8051_ram_top:v <0x4b18fe14> + streams: 10, words: 8226 + worklib.oc8051_ram_wr_sel:v <0x61b65dfb> + streams: 10, words: 4203 + worklib.oc8051_reg1:v <0x5eeb0e90> + streams: 3, words: 1141 + worklib.oc8051_reg2:v <0x33db6894> + streams: 3, words: 1203 + worklib.oc8051_reg3:v <0x68157157> + streams: 3, words: 1203 + worklib.oc8051_reg3:v <0x788a669a> + streams: 3, words: 1339 + worklib.oc8051_reg4:v <0x6ea93a4e> + streams: 3, words: 1211 + worklib.oc8051_reg8:v <0x6d379d10> + streams: 3, words: 1203 + worklib.oc8051_reg8:v <0x7dac9253> + streams: 3, words: 1335 + worklib.oc8051_rom:v <0x08c719d5> + streams: 7, words: 3947 + worklib.oc8051_rom_addr_sel:v <0x6c560c33> + streams: 1, words: 608 + worklib.oc8051_sp:v <0x7c2e5f6c> + streams: 13, words: 7484 + worklib.oc8051_tb:v <0x577c1173> + streams: 23, words: 11573 + worklib.oc8051_tc:v <0x3c6915f1> + streams: 44, words: 32060 + worklib.oc8051_top:v <0x5117fb59> + streams: 4, words: 1620 + worklib.oc8051_uart:v <0x5c872655> + streams: 135, words: 100926 + worklib.oc8051_uart_test:v <0x0cbc1f71> + streams: 8, words: 3386 + worklib.oc8051_xram:v <0x322d2b1f> + streams: 8, words: 5421 + Loading native compiled code: .................... Done + Building instance specific data structures. + Design hierarchy summary: + Instances Unique + Modules: 51 39 + Registers: 213 181 + Scalar wires: 73 - + Expanded wires: 80 8 + Vectored wires: 121 - + Always blocks: 114 94 + Initial blocks: 6 6 + Cont. assignments: 69 91 + Pseudo assignments: 20 20 + Simulation timescale: 10ps + Writing initial simulation snapshot: worklib.oc8051_tb:v Index: rtl_sim/out/sqroot.out =================================================================== --- rtl_sim/out/sqroot.out (nonexistent) +++ rtl_sim/out/sqroot.out (revision 186) @@ -0,0 +1,19 @@ +Loading snapshot worklib.oc8051_tb:v .................... Done +ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc +ncsim> run + +Warning! some objects excluded from $dumpvars due to -access -R + File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16 + Scope: oc8051_tb + Time: 0 FS + 0 + +time 1 step 0: pass +time 12816 step 1: pass +time 18636 step 2: pass +time 25306 step 3: pass +time 54416 step 4: pass + + Done! +Simulation complete via $finish(1) at time 54416 NS + 2 +/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155 $finish; +ncsim> exit Index: rtl_sim/out/lcall.out =================================================================== --- rtl_sim/out/lcall.out (nonexistent) +++ rtl_sim/out/lcall.out (revision 186) @@ -0,0 +1,17 @@ +Loading snapshot worklib.oc8051_tb:v .................... Done +ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc +ncsim> run + +Warning! some objects excluded from $dumpvars due to -access -R + File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16 + Scope: oc8051_tb + Time: 0 FS + 0 + +time 1 step 0: pass +time 86 step 1: pass +time 136 step 2: pass + + Done! +Simulation complete via $finish(1) at time 136 NS + 2 +/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155 $finish; +ncsim> exit Index: rtl_sim/out/sort.out =================================================================== --- rtl_sim/out/sort.out (nonexistent) +++ rtl_sim/out/sort.out (revision 186) @@ -0,0 +1,26 @@ +Loading snapshot worklib.oc8051_tb:v .................... Done +ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc +ncsim> run + +Warning! some objects excluded from $dumpvars due to -access -R + File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16 + Scope: oc8051_tb + Time: 0 FS + 0 + +time 1 step 0: pass +time 69446 step 1: pass +time 70026 step 2: pass +time 70486 step 3: pass +time 70946 step 4: pass +time 71406 step 5: pass +time 71866 step 6: pass +time 72326 step 7: pass +time 72786 step 8: pass +time 73246 step 9: pass +time 73706 step 10: pass +time 74166 step 11: pass + + Done! +Simulation complete via $finish(1) at time 74166 NS + 2 +/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155 $finish; +ncsim> exit Index: rtl_sim/out/cast.out =================================================================== --- rtl_sim/out/cast.out (nonexistent) +++ rtl_sim/out/cast.out (revision 186) @@ -0,0 +1,19 @@ +Loading snapshot worklib.oc8051_tb:v .................... Done +ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc +ncsim> run + +Warning! some objects excluded from $dumpvars due to -access -R + File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16 + Scope: oc8051_tb + Time: 0 FS + 0 + +time 1 step 0: pass +time 10836 step 1: pass +time 13816 step 2: pass +time 15436 step 3: pass +time 15586 step 4: pass + + Done! +Simulation complete via $finish(1) at time 15586 NS + 2 +/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155 $finish; +ncsim> exit Index: rtl_sim/out/interrupt_test.out =================================================================== --- rtl_sim/out/interrupt_test.out (nonexistent) +++ rtl_sim/out/interrupt_test.out (revision 186) @@ -0,0 +1,17 @@ +Loading snapshot worklib.oc8051_tb:v .................... Done +ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc +ncsim> run + +Warning! some objects excluded from $dumpvars due to -access -R + File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16 + Scope: oc8051_tb + Time: 0 FS + 0 + +time 1 step 0: pass +time 6436 step 1: pass +time 8876 step 2: pass + + Done! +Simulation complete via $finish(1) at time 8876 NS + 2 +/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155 $finish; +ncsim> exit Index: rtl_sim/out/r_bank.out =================================================================== --- rtl_sim/out/r_bank.out (nonexistent) +++ rtl_sim/out/r_bank.out (revision 186) @@ -0,0 +1,20 @@ +Loading snapshot worklib.oc8051_tb:v .................... Done +ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc +ncsim> run + +Warning! some objects excluded from $dumpvars due to -access -R + File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16 + Scope: oc8051_tb + Time: 0 FS + 0 + +time 1 step 0: pass +time 186 step 1: pass +time 306 step 2: pass +time 426 step 3: pass +time 546 step 4: pass +time 656 step 5: pass + + Done! +Simulation complete via $finish(1) at time 656 NS + 2 +/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155 $finish; +ncsim> exit Index: rtl_sim/out/gcd.out =================================================================== --- rtl_sim/out/gcd.out (nonexistent) +++ rtl_sim/out/gcd.out (revision 186) @@ -0,0 +1,21 @@ +Loading snapshot worklib.oc8051_tb:v .................... Done +ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc +ncsim> run + +Warning! some objects excluded from $dumpvars due to -access -R + File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16 + Scope: oc8051_tb + Time: 0 FS + 0 + +time 1 step 0: pass +time 6636 step 1: pass +time 6826 step 2: pass +time 7016 step 3: pass +time 7206 step 4: pass +time 7396 faulire: mismatch on ports in step 5 + p0_out 03 p1_out 08 p2_out ff + testvecp 01xxxx + p_out 0308ff +Simulation complete via $finish(1) at time 7418 NS + 0 +/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:146 $finish; +ncsim> exit Index: rtl_sim/out/fib.out =================================================================== --- rtl_sim/out/fib.out (nonexistent) +++ rtl_sim/out/fib.out (revision 186) @@ -0,0 +1,24 @@ +Loading snapshot worklib.oc8051_tb:v .................... Done +ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc +ncsim> run + +Warning! some objects excluded from $dumpvars due to -access -R + File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16 + Scope: oc8051_tb + Time: 0 FS + 0 + +time 1 step 0: pass +time 15916 step 1: pass +time 16836 step 2: pass +time 17296 step 3: pass +time 17756 step 4: pass +time 18216 step 5: pass +time 18676 step 6: pass +time 19136 step 7: pass +time 19596 step 8: pass +time 20056 step 9: pass + + Done! +Simulation complete via $finish(1) at time 20056 NS + 2 +/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155 $finish; +ncsim> exit Index: rtl_sim/out/divmul.out =================================================================== --- rtl_sim/out/divmul.out (nonexistent) +++ rtl_sim/out/divmul.out (revision 186) @@ -0,0 +1,18 @@ +Loading snapshot worklib.oc8051_tb:v .................... Done +ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc +ncsim> run + +Warning! some objects excluded from $dumpvars due to -access -R + File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16 + Scope: oc8051_tb + Time: 0 FS + 0 + +time 1 step 0: pass +time 9416 step 1: pass +time 9426 step 2: pass +time 9436 step 3: pass + + Done! +Simulation complete via $finish(1) at time 9436 NS + 2 +/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155 $finish; +ncsim> exit Index: rtl_sim/out/int2bin.out =================================================================== --- rtl_sim/out/int2bin.out (nonexistent) +++ rtl_sim/out/int2bin.out (revision 186) @@ -0,0 +1,23 @@ +Loading snapshot worklib.oc8051_tb:v .................... Done +ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc +ncsim> run + +Warning! some objects excluded from $dumpvars due to -access -R + File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16 + Scope: oc8051_tb + Time: 0 FS + 0 + +time 1 step 0: pass +time 6706 step 1: pass +time 7096 step 2: pass +time 7546 step 3: pass +time 8116 step 4: pass +time 8746 step 5: pass +time 9496 step 6: pass +time 10306 step 7: pass +time 11236 step 8: pass + + Done! +Simulation complete via $finish(1) at time 11236 NS + 2 +/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155 $finish; +ncsim> exit Index: rtl_sim/out/testall.out =================================================================== --- rtl_sim/out/testall.out (nonexistent) +++ rtl_sim/out/testall.out (revision 186) @@ -0,0 +1,16 @@ +Loading snapshot worklib.oc8051_tb:v .................... Done +ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc +ncsim> run + +Warning! some objects excluded from $dumpvars due to -access -R + File: /projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v, line = 161, pos = 16 + Scope: oc8051_tb + Time: 0 FS + 0 + +time 1 step 0: pass +time 30576 step 1: pass + + Done! +Simulation complete via $finish(1) at time 30576 NS + 2 +/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v:155 $finish; +ncsim> exit Index: rtl_sim/out/timer.out =================================================================== --- rtl_sim/out/timer.out (nonexistent) +++ rtl_sim/out/timer.out (revision 186) @@ -0,0 +1,18 @@ +Loading snapshot worklib.oc8051_tb:v .................... Done +ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc +ncsim> run + +Warning! some objects excluded from $dumpvars due to -access -R + File: /home/simont/oc8051/bench/verilog/oc8051_tb.v, line = 154, pos = 16 + Scope: oc8051_tb + Time: 0 FS + 0 + +time 1 step 0: pass +time 36056 step 1: pass +time 36156 step 2: pass +time 36246 step 3: pass + + Done! +Simulation complete via $finish(1) at time 36246 NS + 2 +/home/simont/oc8051/bench/verilog/oc8051_tb.v:148 $finish; +ncsim> exit Index: rtl_sim/out/ncprep.out =================================================================== --- rtl_sim/out/ncprep.out (nonexistent) +++ rtl_sim/out/ncprep.out (revision 186) @@ -0,0 +1,3 @@ +ncprep: v03.30.(p001): (c) Copyright 1995 - 2001 Cadence Design Systems, Inc. +Adding -UPDATE option, to disable update run ncprep with the +noupdate +Translation successful. Index: rtl_sim/out/ncvlog.out =================================================================== --- rtl_sim/out/ncvlog.out (nonexistent) +++ rtl_sim/out/ncvlog.out (revision 186) @@ -0,0 +1,117 @@ +file: ../../../bench/verilog/oc8051_tb.v + module worklib.oc8051_tb:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_top.v + module worklib.oc8051_top:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_alu_src1_sel.v + module worklib.oc8051_alu_src1_sel:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_alu_src2_sel.v + module worklib.oc8051_alu_src2_sel:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_alu_src3_sel.v + module worklib.oc8051_alu_src3_sel:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_alu.v + module worklib.oc8051_alu:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_decoder.v + module worklib.oc8051_decoder:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_divide.v + module worklib.oc8051_divide:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_immediate_sel.v + module worklib.oc8051_immediate_sel:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_multiply.v + module worklib.oc8051_multiply:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_op_select.v + module worklib.oc8051_op_select:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_pc.v + module worklib.oc8051_pc:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_reg8.v + module worklib.oc8051_reg8:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_reg2.v + module worklib.oc8051_reg2:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_reg1.v + module worklib.oc8051_reg1:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_reg4.v + module worklib.oc8051_reg4:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_ram_wr_sel.v + module worklib.oc8051_ram_wr_sel:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_ram_rd_sel.v + module worklib.oc8051_ram_rd_sel:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_ram_top.v + module worklib.oc8051_ram_top:v + errors: 0, warnings: 0 +file: ../../../sim/rtl_sim/src/verilog/oc8051_xram.v + module worklib.oc8051_xram:v + errors: 0, warnings: 0 +file: ../../../sim/rtl_sim/src/verilog/oc8051_ram.v + module worklib.oc8051_ram:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_acc.v + module worklib.oc8051_acc:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_comp.v + module worklib.oc8051_comp:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_sp.v + module worklib.oc8051_sp:v + errors: 0, warnings: 0 +file: ../../../sim/rtl_sim/src/verilog/oc8051_uart_test.v + module worklib.oc8051_uart_test:v + errors: 0, warnings: 0 +file: ../../../sim/rtl_sim/src/verilog/oc8051_rom.v + module worklib.oc8051_rom:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_dptr.v + module worklib.oc8051_dptr:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_cy_select.v + module worklib.oc8051_cy_select:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_psw.v + module worklib.oc8051_psw:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_indi_addr.v + module worklib.oc8051_indi_addr:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_rom_addr_sel.v + module worklib.oc8051_rom_addr_sel:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_ext_addr_sel.v + module worklib.oc8051_ext_addr_sel:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_reg3.v + module worklib.oc8051_reg3:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_ram_sel.v + module worklib.oc8051_ram_sel:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_ports.v + module worklib.oc8051_ports:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_b_register.v + module worklib.oc8051_b_register:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_uart.v + module worklib.oc8051_uart:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_int.v + module worklib.oc0851_int:v + errors: 0, warnings: 0 +file: ../../../rtl/verilog/oc8051_tc.v + module worklib.oc8051_tc:v + errors: 0, warnings: 0 Index: rtl_sim/out/xrom_m.out =================================================================== --- rtl_sim/out/xrom_m.out (nonexistent) +++ rtl_sim/out/xrom_m.out (revision 186) @@ -0,0 +1,16 @@ +Loading snapshot worklib.oc8051_tb:v .................... Done +ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc +ncsim> run +$readmem error: number too long in file "../src/oc8051_test.vec" at line 2 + +Warning! some objects excluded from $dumpvars due to -access -R + File: /home/simont/oc8051/bench/verilog/oc8051_tb.v, line = 154, pos = 16 + Scope: oc8051_tb + Time: 0 FS + 0 + +time 1 step 0: pass + + Done! +Simulation complete via $finish(1) at time 1 NS + 2 +/home/simont/oc8051/bench/verilog/oc8051_tb.v:148 $finish; +ncsim> exit