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    /System09/rev_86/rtl/System09_BurchED_B5-X300
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Rev 66 → Rev 112

/System09_BurchED_B5-X300.ucf
0,0 → 1,230
#### UCF file created by Project Navigator
#
NET "reset_n" LOC = "p57" ;
NET "sysclk" LOC = "p77" ;
#
# For B5-Compact-Flash:
# Connector A
#
#NET "pin2" LOC = "P3" ; #J1-2
#NET "pin3" LOC = "P4" ; #J1-3
#NET "cf_intrq" LOC = "P5" ; #J1-4
NET "cf_wr_n" LOC = "P6" ; #J1-5
NET "cf_rd_n" LOC = "P7" ; #J1-6
NET "cf_cs1_n" LOC = "P8" ; #J1-7
NET "cf_d<15>" LOC = "P9" ; #J1-8
NET "cf_d<14>" LOC = "P10" ; #J1-9
NET "cf_d<13>" LOC = "P11" ; #J1-10
NET "cf_d<12>" LOC = "P15" ; #J1-11
NET "cf_d<11>" LOC = "P16" ; #J1-12
#NET "cf_present" LOC = "P17" ; #J1-13
NET "cf_d<3>" LOC = "P18" ; #J1-14
NET "cf_d<4>" LOC = "P20" ; #J1-15
NET "cf_d<5>" LOC = "P21" ; #J1-16
NET "cf_d<6>" LOC = "P22" ; #J1-17
NET "cf_d<7>" LOC = "P23" ; #J1-18
NET "cf_cs0_n" LOC = "P24" ; #J1-19
#
# For B5-Compact-Flash:
# Connector B
#
NET "cf_a<2>" LOC = "P33" ; #J2-6
NET "cf_a<1>" LOC = "P34" ; #J2-7
NET "cf_a<0>" LOC = "P35" ; #J2-8
NET "cf_d<0>" LOC = "P36" ; #J2-9
NET "cf_d<1>" LOC = "P40" ; #J2-10
NET "cf_d<2>" LOC = "P41" ; #J2-11
#NET "cf_cs16_n" LOC = "P42" ; #J2-12
NET "cf_d<10>" LOC = "P43" ; #J2-13
NET "cf_d<9>" LOC = "P44" ; #J2-14
NET "cf_d<8>" LOC = "P45" ; #J2-15
#NET "cf_pdiag" LOC = "P46" ; #J2-16
#NET "cf_dase" LOC = "P47" ; #J2-17
#NET "cf_iordy" LOC = "P48" ; #J2-18
NET "cf_rst_n" LOC = "P49" ; #J2-19
#
# For B5-Peripheral-Connectors
# Connector C
#
NET "v_drive" LOC = "p55" ; #pin 3
NET "h_drive" LOC = "p56" ; #pin 4
NET "blue_lo" LOC = "p58" ; #pin 5
NET "blue_hi" LOC = "p59" ; #pin 6
NET "green_lo" LOC = "p60" ; #pin 7
NET "green_hi" LOC = "p61" ; #pin 8
NET "red_lo" LOC = "p62" ; #pin 9
NET "red_hi" LOC = "p63" ; #pin 10
NET "kb_clock" LOC = "p64" ; #pin 11
NET "kb_data" LOC = "p68" ; #pin 12
#NET "mouse-clock" LOC = "p69" ; #pin 13
#NET "mouse_data" LOC = "p70" ; #pin 14
#NET "buzzer" LOC = "p71" ; #pin 15
NET "cts_n" LOC = "p73" ; #pin 16
NET "rxbit" LOC = "p74" ; #pin 17
NET "txbit" LOC = "p75" ; #pin 18
NET "rts_n" LOC = "p81" ; #pin 19
#
# I/O Port
# Connector D
#
#NET "pin2clk" LOC = "p80" ; #pin 2 (Clock input)
NET "led" LOC = "p82" ; #pin 3
NET "porta<0>" LOC = "p83" ; #pin 4
NET "porta<1>" LOC = "p84" ; #pin 5
NET "porta<2>" LOC = "p86" ; #pin 6
NET "porta<3>" LOC = "p87" ; #pin 7
NET "porta<4>" LOC = "p88" ; #pin 8
NET "porta<5>" LOC = "p89" ; #pin 9
NET "porta<6>" LOC = "p93" ; #pin 10
NET "porta<7>" LOC = "p94" ; #pin 11
NET "portb<0>" LOC = "p95" ; #pin 12
NET "portb<1>" LOC = "p96" ; #pin 13
NET "portb<2>" LOC = "p97" ; #pin 14
NET "portb<3>" LOC = "p98" ; #pin 15
NET "portb<4>" LOC = "p99" ; #pin 16
NET "portb<5>" LOC = "p100"; #pin 17
NET "portb<6>" LOC = "p101"; #pin 18
NET "portb<7>" LOC = "p102"; #pin 19
#
# For B5-SRAM
# Connector E
#
NET "ram_csn" LOC = "p108"; #J1.2
NET "ram_addr<16>" LOC = "p109"; #J1.3
NET "ram_addr<15>" LOC = "p110"; #J1.4
NET "ram_addr<14>" LOC = "p111"; #J1.5
NET "ram_addr<13>" LOC = "p112"; #J1.6
NET "ram_addr<12>" LOC = "p113"; #J1.7
NET "ram_addr<11>" LOC = "p114"; #J1.8
NET "ram_addr<10>" LOC = "p115"; #J1.9
NET "ram_addr<9>" LOC = "p116"; #J1.10
NET "ram_addr<8>" LOC = "p120"; #J1.11
NET "ram_addr<7>" LOC = "p121"; #J1.12
NET "ram_addr<6>" LOC = "p122"; #J1.13
NET "ram_addr<5>" LOC = "p123"; #J1.14
NET "ram_addr<4>" LOC = "p125"; #J1.15
NET "ram_addr<3>" LOC = "p126"; #J1.16
NET "ram_addr<2>" LOC = "p127"; #J1.17
NET "ram_addr<1>" LOC = "p129"; #J1.18
NET "ram_addr<0>" LOC = "p132"; #J1.19
#
# For B5-SRAM
# Connector F
#
NET "ram_wrun" LOC = "p133"; #J2.2
NET "ram_wrln" LOC = "p134"; #J2.3
NET "ram_data<15>" LOC = "p135"; #J2.4
NET "ram_data<14>" LOC = "p136"; #J2.5
NET "ram_data<13>" LOC = "p138"; #J2.6
NET "ram_data<12>" LOC = "p139"; #J2.7
NET "ram_data<11>" LOC = "p140"; #J2.8
NET "ram_data<10>" LOC = "p141"; #J2.9
NET "ram_data<9>" LOC = "p145"; #J2.10
NET "ram_data<8>" LOC = "p146"; #J2.11
NET "ram_data<7>" LOC = "p147"; #J2.12
NET "ram_data<6>" LOC = "p148"; #J2.13
NET "ram_data<5>" LOC = "p149"; #J2.14
NET "ram_data<4>" LOC = "p150"; #J2.15
NET "ram_data<3>" LOC = "p151"; #J2.16
NET "ram_data<2>" LOC = "p152"; #J2.17
NET "ram_data<1>" LOC = "p153"; #J2.18
NET "ram_data<0>" LOC = "p154"; #J2.19
#
# Connector G
#
#NET "pin2" LOC = "p182"; #pin 2 (clk input)
NET "bus_addr<0>" LOC = "p160"; #pin 3
NET "bus_addr<1>" LOC = "p161"; #pin 4
NET "bus_addr<2>" LOC = "p162"; #pin 5
NET "bus_addr<3>" LOC = "p163"; #pin 6
NET "bus_addr<4>" LOC = "p164"; #pin 7
NET "bus_addr<5>" LOC = "p165"; #pin 8
NET "bus_addr<6>" LOC = "p166"; #pin 9
NET "bus_addr<7>" LOC = "p167"; #pin 10
NET "bus_addr<8>" LOC = "p168"; #pin 11
NET "bus_addr<9>" LOC = "p169"; #pin 12
NET "bus_addr<10>" LOC = "p173"; #pin 13
NET "bus_addr<11>" LOC = "p174"; #pin 14
NET "bus_addr<12>" LOC = "p175"; #pin 15
NET "bus_addr<13>" LOC = "p176"; #pin 16
NET "bus_addr<14>" LOC = "p178"; #pin 17
NET "bus_addr<15>" LOC = "p179"; #pin 18
NET "bus_cs" LOC = "p180"; #pin 19
#
# Connector H
#
#NET "pin2" LOC = "p185"; #pin 2 (clk input)
NET "bus_clk" LOC = "p181"; #pin 3
NET "bus_reset" LOC = "p187"; #pin 4
#NET "pin5" LOC = "p188"; #pin 5
#NET "pin6" LOC = "p189"; #pin 6
#NET "pin7" LOC = "p191"; #pin 7
#NET "pin8" LOC = "p192"; #pin 8
#NET "pin9" LOC = "p193"; #pin 9
NET "timer_out" LOC = "p194"; #pin 10
NET "bus_data<0>" LOC = "p198"; #pin 11
NET "bus_data<1>" LOC = "p199"; #pin 12
NET "bus_data<2>" LOC = "p200"; #pin 13
NET "bus_data<3>" LOC = "p201"; #pin 14
NET "bus_data<4>" LOC = "p202"; #pin 15
NET "bus_data<5>" LOC = "p203"; #pin 16
NET "bus_data<6>" LOC = "p204"; #pin 17
NET "bus_data<7>" LOC = "p205"; #pin 18
NET "bus_rw" LOC = "p206"; #pin 19
#
# Timing Groups
#
INST "ram_addr<0>" TNM = "gram_addr";
INST "ram_addr<1>" TNM = "gram_addr";
INST "ram_addr<2>" TNM = "gram_addr";
INST "ram_addr<3>" TNM = "gram_addr";
INST "ram_addr<4>" TNM = "gram_addr";
INST "ram_addr<5>" TNM = "gram_addr";
INST "ram_addr<6>" TNM = "gram_addr";
INST "ram_addr<7>" TNM = "gram_addr";
INST "ram_addr<8>" TNM = "gram_addr";
INST "ram_addr<9>" TNM = "gram_addr";
INST "ram_addr<10>" TNM = "gram_addr";
INST "ram_addr<11>" TNM = "gram_addr";
INST "ram_addr<12>" TNM = "gram_addr";
INST "ram_addr<13>" TNM = "gram_addr";
INST "ram_addr<14>" TNM = "gram_addr";
INST "ram_addr<15>" TNM = "gram_addr";
INST "ram_addr<16>" TNM = "gram_addr";
INST "ram_data<0>" TNM = "gram_data";
INST "ram_data<1>" TNM = "gram_data";
INST "ram_data<2>" TNM = "gram_data";
INST "ram_data<3>" TNM = "gram_data";
INST "ram_data<4>" TNM = "gram_data";
INST "ram_data<5>" TNM = "gram_data";
INST "ram_data<6>" TNM = "gram_data";
INST "ram_data<7>" TNM = "gram_data";
INST "ram_data<8>" TNM = "gram_data";
INST "ram_data<9>" TNM = "gram_data";
INST "ram_data<10>" TNM = "gram_data";
INST "ram_data<11>" TNM = "gram_data";
INST "ram_data<12>" TNM = "gram_data";
INST "ram_data<13>" TNM = "gram_data";
INST "ram_data<14>" TNM = "gram_data";
INST "ram_data<15>" TNM = "gram_data";
INST "ram_wrln" TNM = "gram_wr";
INST "ram_wrun" TNM = "gram_wr";
INST "ram_csn" TNM = "gram_cs";
#
# Timing Constraints
#
#TIMEGRP "gram_cs" OFFSET = OUT 40 ns AFTER "sysclk";
#TIMEGRP "gram_wr" OFFSET = OUT 40 ns AFTER "sysclk";
#TIMEGRP "gram_addr" OFFSET = OUT 40 ns AFTER "sysclk";
#TIMEGRP "gram_data" OFFSET = OUT 40 ns AFTER "sysclk";
#TIMEGRP "gram_data" OFFSET = IN 15 ns BEFORE "sysclk";
#TIMEGRP "gtest_alu" OFFSET = OUT 90 ns AFTER "sysclk";
#TIMEGRP "gtest_cc" OFFSET = OUT 95 ns AFTER "sysclk";
NET "sysclk" TNM_NET = "sysclk";
TIMESPEC "TS_sysclk" = PERIOD "sysclk" 20 ns LOW 50 %;
#
# Fast I/O Pins
#
NET "ram_csn" FAST;
NET "ram_wrln" FAST;
NET "ram_wrun" FAST;
/System09_BurchED_B5-X300.vhd
0,0 → 1,1097
--===========================================================================----
--
-- S Y N T H E Z I A B L E System09 - SOC.
--
-- www.OpenCores.Org - September 2003
-- This core adheres to the GNU public license
--
-- File name : System09.vhd
--
-- Purpose : Top level file for 6809 compatible system on a chip
-- Designed with Xilinx XC2S300e Spartan 2+ FPGA.
-- Implemented With BurchED B5-X300 FPGA board,
-- B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO module
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- ieee.numeric_std
--
-- Uses :
-- cpu09 (cpu09.vhd) CPU core
-- mon_rom (sys09bug_rom2k_b4.vhd) Monitor ROM
-- dat_ram (datram.vhd) Dynamic Address Translation
-- acia_6850 (ACIA_6850.vhd) ACIA / MiniUART
-- (ACIA_RX.vhd)
-- (ACIA_TX.vhd)
-- ACIA_Clock (ACIA_Clock.vhd) ACIA Baud Clock Divider
-- keyboard (keyboard.vhd) PS/2 Keyboard Interface
-- vdu8 (vdu8.vhd) 80 x 25 Video Display
-- timer (timer.vhd) Timer module
-- trap (trap.vhd) Bus Trap interrupt
-- ioport (ioport.vhd) Parallel I/O port.
--
-- Author : John E. Kent
-- dilbert57@opencores.org
-- Memory Map :
-- $E000 - ACIA (SWTPc)
-- $E010 - Reserved for FD1771 FDC (SWTPc)
-- $E020 - Keyboard
-- $E030 - VDU
-- $E040 - Compact Flash
-- $E050 - Timer
-- $E060 - Bus trap
-- $E070 - Parallel I/O
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
--
--===========================================================================----
--
-- Revision History:
--===========================================================================--
-- Version 0.1 - 20 March 2003
-- Version 0.2 - 30 March 2003
-- Version 0.3 - 29 April 2003
-- Version 0.4 - 29 June 2003
--
-- Version 0.5 - 19 July 2003
-- prints out "Hello World"
--
-- Version 0.6 - 5 September 2003
-- Runs SBUG
--
-- Version 1.0- 6 Sep 2003 - John Kent
-- Inverted SysClk
-- Initial release to Open Cores
--
-- Version 1.1 - 17 Jan 2004 - John Kent
-- Updated miniUart.
--
-- Version 1.2 - 25 Jan 2004 - John Kent
-- removed signals "test_alu" and "test_cc"
-- Trap hardware re-instated.
--
-- Version 1.3 - 11 Feb 2004 - John Kent
-- Designed forked off to produce System09_VDU
-- Added VDU component
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
-- UART Runs at 57.6 Kbps
--
-- Version 1.4 - 21 Nov 2004 - John Kent
-- Changes to make compatible with Spartan3 starter kit version
-- Designed to run with a 50MHz clock input.
-- the VDU divides 50 MHz to generate a
-- 25 MHz VDU Pixel Clock and a 12.5 MHz CPU clock
-- Changed Monitor ROM signals to make it look like
-- a standard 2K memory block
-- Re-assigned I/O port assignments so it is possible to run KBUG9
-- $E000 - ACIA
-- $E010 - Keyboard
-- $E020 - VDU
-- $E030 - Compact Flash
-- $E040 - Timer
-- $E050 - Bus trap
-- $E060 - Parallel I/O
--
-- Version 1.5 - 3rd February 2007 - John Kent
-- Changed VDU8 to use external clock divider
-- renamed miniUART to ACIA_6850
-- Memory decoding of ROM & IO now uses DAT
--
-- Version 1.6 - 7th Februaury 2007 - John Kent
-- Made ACIA Clock generator an external component
-- Added Generics to VDU and Keyboard
-- Changed decoding
--
-- Version 1.7 - 20th May 2007 - John Kent
-- Added 4 wait states to CF access
-- Removed DAT memory map control of ROM & IO
-- to allow for full use of RAM as a RAM disk.
-- Mapped in all 16 bits of the CF data bus.
--
--===========================================================================
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
 
entity System09 is
port(
SysClk : in Std_Logic; -- System Clock input
Reset_n : in Std_logic; -- Master Reset input (active low)
LED : out std_logic; -- Diagnostic LED Flasher
 
-- Memory Interface signals
ram_csn : out Std_Logic;
ram_wrln : out Std_Logic;
ram_wrun : out Std_Logic;
ram_addr : out Std_Logic_Vector(16 downto 0);
ram_data : inout Std_Logic_Vector(15 downto 0);
 
-- Stuff on the peripheral board
 
-- PS/2 Keyboard
kb_clock : inout Std_logic;
kb_data : inout Std_Logic;
 
-- PS/2 Mouse interface
-- mouse_clock : in Std_Logic;
-- mouse_data : in Std_Logic;
 
-- Uart Interface
rxbit : in Std_Logic;
txbit : out Std_Logic;
rts_n : out Std_Logic;
cts_n : in Std_Logic;
 
-- CRTC output signals
v_drive : out Std_Logic;
h_drive : out Std_Logic;
blue_lo : out std_logic;
blue_hi : out std_logic;
green_lo : out std_logic;
green_hi : out std_logic;
red_lo : out std_logic;
red_hi : out std_logic;
-- buzzer : out std_logic;
 
-- Compact Flash
cf_rst_n : out std_logic;
cf_cs0_n : out std_logic;
cf_cs1_n : out std_logic;
cf_rd_n : out std_logic;
cf_wr_n : out std_logic;
cf_a : out std_logic_vector(2 downto 0);
cf_d : inout std_logic_vector(15 downto 0);
 
-- Parallel I/O port
porta : inout std_logic_vector(7 downto 0);
portb : inout std_logic_vector(7 downto 0);
 
-- CPU bus
bus_clk : out std_logic;
bus_reset : out std_logic;
bus_rw : out std_logic;
bus_cs : out std_logic;
bus_addr : out std_logic_vector(15 downto 0);
bus_data : inout std_logic_vector(7 downto 0);
 
-- timer
timer_out : out std_logic
);
end System09;
 
-------------------------------------------------------------------------------
-- Architecture for System09
-------------------------------------------------------------------------------
architecture rtl of System09 is
-----------------------------------------------------------------------------
-- constants
-----------------------------------------------------------------------------
constant SYS_Clock_Frequency : integer := 50000000; -- FPGA System Clock
constant PIX_Clock_Frequency : integer := 25000000; -- VGA Pixel Clock
constant CPU_Clock_Frequency : integer := 12500000; -- CPU Clock
constant BAUD_Rate : integer := 57600; -- Baud Rate
constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16;
 
type hold_state_type is ( hold_release_state, hold_request_state );
 
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- Monitor ROM
signal rom_data_out : Std_Logic_Vector(7 downto 0);
signal rom_cs : std_logic;
 
-- UART Interface signals
signal uart_data_out : Std_Logic_Vector(7 downto 0);
signal uart_cs : Std_Logic;
signal uart_irq : Std_Logic;
signal uart_clk : Std_Logic;
signal DCD_n : Std_Logic;
 
-- timer
signal timer_data_out : std_logic_vector(7 downto 0);
signal timer_cs : std_logic;
signal timer_irq : std_logic;
 
-- trap
signal trap_cs : std_logic;
signal trap_data_out : std_logic_vector(7 downto 0);
signal trap_irq : std_logic;
 
-- Parallel I/O port
signal ioport_data_out : std_logic_vector(7 downto 0);
signal ioport_cs : std_logic;
 
-- compact flash port
signal cf_data_out : std_logic_vector(7 downto 0);
signal cf_cs : std_logic;
signal cf_rd : std_logic;
signal cf_wr : std_logic;
signal cf_hold : std_logic;
signal cf_release : std_logic;
signal cf_count : std_logic_vector(3 downto 0);
signal cf_hold_state : hold_state_type;
 
-- keyboard port
signal keyboard_data_out : std_logic_vector(7 downto 0);
signal keyboard_cs : std_logic;
signal keyboard_irq : std_logic;
 
-- RAM
signal ram_cs : std_logic; -- memory chip select
signal ram_wrl : std_logic; -- memory write lower
signal ram_wru : std_logic; -- memory write upper
signal ram_data_out : std_logic_vector(7 downto 0);
 
-- CPU Interface signals
signal cpu_reset : Std_Logic;
signal cpu_clk : Std_Logic;
signal cpu_rw : std_logic;
signal cpu_vma : std_logic;
signal cpu_halt : std_logic;
signal cpu_hold : std_logic;
signal cpu_firq : std_logic;
signal cpu_irq : std_logic;
signal cpu_nmi : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_data_in : std_logic_vector(7 downto 0);
signal cpu_data_out : std_logic_vector(7 downto 0);
 
-- Dynamic address translation
signal dat_cs : std_logic;
signal dat_addr : std_logic_vector(7 downto 0);
 
-- Video Display Unit
signal pix_clk : std_logic;
signal vdu_cs : std_logic;
signal vdu_data_out : std_logic_vector(7 downto 0);
signal vga_red : std_logic;
signal vga_green : std_logic;
signal vga_blue : std_logic;
 
-- Flashing Led test signals
signal countL : std_logic_vector(23 downto 0);
signal clock_div : std_logic_vector(1 downto 0);
 
-----------------------------------------------------------------
--
-- CPU09 CPU core
--
-----------------------------------------------------------------
 
component cpu09
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
halt: in std_logic;
hold: in std_logic;
irq: in std_logic;
nmi: in std_logic;
firq: in std_logic
);
end component;
 
 
----------------------------------------
--
-- SBUG Block RAM Monitor ROM
--
----------------------------------------
component mon_rom
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
wdata : in std_logic_vector (7 downto 0);
rdata : out std_logic_vector (7 downto 0)
);
end component;
 
 
----------------------------------------
--
-- Dynamic Address Translation Registers
--
----------------------------------------
component dat_ram
port (
clk: in std_logic;
rst: in std_logic;
cs: in std_logic;
rw: in std_logic;
addr_lo: in std_logic_vector(3 downto 0);
addr_hi: in std_logic_vector(3 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0)
);
end component;
 
-----------------------------------------------------------------
--
-- 6850 ACIA/UART
--
-----------------------------------------------------------------
 
component ACIA_6850
port (
clk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input (active high)
cs : in Std_Logic; -- miniUART Chip Select
rw : in Std_Logic; -- Read / Not Write
irq : out Std_Logic; -- Interrupt
Addr : in Std_Logic; -- Register Select
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
RxC : in Std_Logic; -- Receive Baud Clock
TxC : in Std_Logic; -- Transmit Baud Clock
RxD : in Std_Logic; -- Receive Data
TxD : out Std_Logic; -- Transmit Data
DCD_n : in Std_Logic; -- Data Carrier Detect
CTS_n : in Std_Logic; -- Clear To Send
RTS_n : out Std_Logic ); -- Request To send
end component;
 
-----------------------------------------------------------------
--
-- ACIA Clock divider
--
-----------------------------------------------------------------
 
component ACIA_Clock
generic (
SYS_Clock_Frequency : integer := SYS_Clock_Frequency;
ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
);
port (
clk : in Std_Logic; -- System Clock Input
ACIA_clk : out Std_logic -- ACIA Clock output
);
end component;
 
----------------------------------------
--
-- Timer module
--
----------------------------------------
 
component timer
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic;
timer_in : in std_logic;
timer_out : out std_logic
);
end component;
 
------------------------------------------------------------
--
-- Bus Trap logic
--
------------------------------------------------------------
 
component trap
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
vma : in std_logic;
addr : in std_logic_vector(15 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic
);
end component;
 
----------------------------------------
--
-- Dual 8 bit Parallel I/O module
--
----------------------------------------
component ioport
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(1 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
porta_io : inout std_logic_vector(7 downto 0);
portb_io : inout std_logic_vector(7 downto 0)
);
end component;
 
----------------------------------------
--
-- PS/2 Keyboard
--
----------------------------------------
 
component keyboard
generic(
KBD_Clock_Frequency : integer := CPU_Clock_Frequency
);
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic;
kbd_clk : inout std_logic;
kbd_data : inout std_logic
);
end component;
 
----------------------------------------
--
-- Video Display Unit.
--
----------------------------------------
component vdu8
generic(
VDU_CLOCK_FREQUENCY : integer := CPU_Clock_Frequency; -- HZ
VGA_CLOCK_FREQUENCY : integer := PIX_Clock_Frequency; -- HZ
VGA_HOR_CHARS : integer := 80; -- CHARACTERS
VGA_VER_CHARS : integer := 25; -- CHARACTERS
VGA_PIXELS_PER_CHAR : integer := 8; -- PIXELS
VGA_LINES_PER_CHAR : integer := 16; -- LINES
VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS
VGA_HOR_SYNC : integer := 96; -- PIXELS
VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS
VGA_VER_BACK_PORCH : integer := 13; -- LINES
VGA_VER_SYNC : integer := 1; -- LINES
VGA_VER_FRONT_PORCH : integer := 36 -- LINES
);
port(
-- control register interface
vdu_clk : in std_logic; -- CPU Clock - 12.5MHz
vdu_rst : in std_logic;
vdu_cs : in std_logic;
vdu_rw : in std_logic;
vdu_addr : in std_logic_vector(2 downto 0);
vdu_data_in : in std_logic_vector(7 downto 0);
vdu_data_out : out std_logic_vector(7 downto 0);
 
-- vga port connections
vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
vga_red_o : out std_logic;
vga_green_o : out std_logic;
vga_blue_o : out std_logic;
vga_hsync_o : out std_logic;
vga_vsync_o : out std_logic
);
end component;
 
 
component BUFG
port (
i: in std_logic;
o: out std_logic
);
end component;
 
begin
-----------------------------------------------------------------------------
-- Instantiation of internal components
-----------------------------------------------------------------------------
 
----------------------------------------
--
-- CPU09 CPU Core
--
----------------------------------------
my_cpu : cpu09 port map (
clk => cpu_clk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
halt => cpu_halt,
hold => cpu_hold,
irq => cpu_irq,
nmi => cpu_nmi,
firq => cpu_firq
);
 
----------------------------------------
--
-- SBUG / KBUG / SYS09BUG Monitor ROM
--
----------------------------------------
my_rom : mon_rom port map (
clk => cpu_clk,
rst => cpu_reset,
cs => rom_cs,
rw => '1',
addr => cpu_addr(10 downto 0),
wdata => cpu_data_out,
rdata => rom_data_out
);
 
----------------------------------------
--
-- Dynamic Address Translation Registers
--
----------------------------------------
my_dat : dat_ram port map (
clk => cpu_clk,
rst => cpu_reset,
cs => dat_cs,
rw => cpu_rw,
addr_hi => cpu_addr(15 downto 12),
addr_lo => cpu_addr(3 downto 0),
data_in => cpu_data_out,
data_out => dat_addr(7 downto 0)
);
 
----------------------------------------
--
-- ACIA/UART Serial interface
--
----------------------------------------
my_ACIA : ACIA_6850 port map (
clk => cpu_clk,
rst => cpu_reset,
cs => uart_cs,
rw => cpu_rw,
irq => uart_irq,
Addr => cpu_addr(0),
Datain => cpu_data_out,
DataOut => uart_data_out,
RxC => uart_clk,
TxC => uart_clk,
RxD => rxbit,
TxD => txbit,
DCD_n => dcd_n,
CTS_n => cts_n,
RTS_n => rts_n
);
 
----------------------------------------
--
-- ACIA Clock
--
----------------------------------------
my_ACIA_Clock : ACIA_Clock
generic map(
SYS_Clock_Frequency => SYS_Clock_Frequency,
ACIA_Clock_Frequency => ACIA_Clock_Frequency
)
port map(
clk => SysClk,
acia_clk => uart_clk
);
 
----------------------------------------
--
-- PS/2 Keyboard Interface
--
----------------------------------------
my_keyboard : keyboard
generic map (
KBD_Clock_Frequency => CPU_Clock_frequency
)
port map(
clk => cpu_clk,
rst => cpu_reset,
cs => keyboard_cs,
rw => cpu_rw,
addr => cpu_addr(0),
data_in => cpu_data_out(7 downto 0),
data_out => keyboard_data_out(7 downto 0),
irq => keyboard_irq,
kbd_clk => kb_clock,
kbd_data => kb_data
);
 
----------------------------------------
--
-- Video Display Unit instantiation
--
----------------------------------------
my_vdu : vdu8
generic map(
VDU_CLOCK_FREQUENCY => CPU_Clock_Frequency, -- HZ
VGA_CLOCK_FREQUENCY => PIX_Clock_Frequency, -- HZ
VGA_HOR_CHARS => 80, -- CHARACTERS
VGA_VER_CHARS => 25, -- CHARACTERS
VGA_PIXELS_PER_CHAR => 8, -- PIXELS
VGA_LINES_PER_CHAR => 16, -- LINES
VGA_HOR_BACK_PORCH => 40, -- PIXELS
VGA_HOR_SYNC => 96, -- PIXELS
VGA_HOR_FRONT_PORCH => 24, -- PIXELS
VGA_VER_BACK_PORCH => 13, -- LINES
VGA_VER_SYNC => 1, -- LINES
VGA_VER_FRONT_PORCH => 36 -- LINES
)
port map(
 
-- Control Registers
vdu_clk => cpu_clk, -- 12.5 MHz System Clock in
vdu_rst => cpu_reset,
vdu_cs => vdu_cs,
vdu_rw => cpu_rw,
vdu_addr => cpu_addr(2 downto 0),
vdu_data_in => cpu_data_out,
vdu_data_out => vdu_data_out,
 
-- vga port connections
vga_clk => pix_clk, -- 25 MHz VDU pixel clock
vga_red_o => vga_red,
vga_green_o => vga_green,
vga_blue_o => vga_blue,
vga_hsync_o => h_drive,
vga_vsync_o => v_drive
);
 
----------------------------------------
--
-- Timer Module
--
----------------------------------------
my_timer : timer port map (
clk => cpu_clk,
rst => cpu_reset,
cs => timer_cs,
rw => cpu_rw,
addr => cpu_addr(0),
data_in => cpu_data_out,
data_out => timer_data_out,
irq => timer_irq,
timer_in => CountL(5),
timer_out => timer_out
);
 
----------------------------------------
--
-- Bus Trap Interrupt logic
--
----------------------------------------
my_trap : trap port map (
clk => cpu_clk,
rst => cpu_reset,
cs => trap_cs,
rw => cpu_rw,
vma => cpu_vma,
addr => cpu_addr,
data_in => cpu_data_out,
data_out => trap_data_out,
irq => trap_irq
);
 
----------------------------------------
--
-- Parallel I/O Port
--
----------------------------------------
my_ioport : ioport port map (
clk => cpu_clk,
rst => cpu_reset,
cs => ioport_cs,
rw => cpu_rw,
addr => cpu_addr(1 downto 0),
data_in => cpu_data_out,
data_out => ioport_data_out,
porta_io => porta,
portb_io => portb
);
 
--
-- 12.5 MHz CPU clock
--
cpu_clk_buffer : BUFG port map(
i => clock_div(1),
o => cpu_clk
);
--
-- 25 MHz VGA Pixel clock
--
vga_clk_buffer : BUFG port map(
i => clock_div(0),
o => pix_clk
);
----------------------------------------------------------------------
--
-- Process to decode memory map
--
----------------------------------------------------------------------
 
mem_decode: process( cpu_clk, Reset_n, dat_addr,
cpu_addr, cpu_rw, cpu_vma,
rom_data_out,
ram_data_out,
cf_data_out,
timer_data_out,
trap_data_out,
ioport_data_out,
uart_data_out,
keyboard_data_out,
vdu_data_out,
bus_data )
variable decode_addr : std_logic_vector(4 downto 0);
begin
decode_addr := dat_addr(3 downto 0) & cpu_addr(11);
-- decode_addr := cpu_addr(15 downto 11);
 
if cpu_addr( 15 downto 8 ) = "11111111" then
cpu_data_in <= rom_data_out;
rom_cs <= cpu_vma; -- read ROM
dat_cs <= cpu_vma; -- write DAT
ram_cs <= '0';
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
else
case decode_addr is
--
-- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF
--
when "11111" => -- $F800 - $FFFF
cpu_data_in <= rom_data_out;
rom_cs <= cpu_vma; -- read ROM
dat_cs <= '0';
ram_cs <= '0';
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
 
--
-- IO Devices $E000 - $E7FF
--
when "11100" => -- $E000 - $E7FF
rom_cs <= '0';
dat_cs <= '0';
ram_cs <= '0';
case cpu_addr(7 downto 4) is
--
-- UART / ACIA $E000
--
when "0000" => -- $E000
cpu_data_in <= uart_data_out;
uart_cs <= cpu_vma;
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
 
--
-- WD1771 FDC sites at $E010-$E01F
--
 
--
-- Keyboard port $E020 - $E02F
--
when "0010" => -- $E020
cpu_data_in <= keyboard_data_out;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= cpu_vma;
vdu_cs <= '0';
bus_cs <= '0';
 
--
-- VDU port $E030 - $E03F
--
when "0011" => -- $E030
cpu_data_in <= vdu_data_out;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= cpu_vma;
bus_cs <= '0';
 
--
-- Compact Flash $E040 - $E04F
--
when "0100" => -- $E040
cpu_data_in <= cf_data_out;
uart_cs <= '0';
cf_cs <= cpu_vma;
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
 
--
-- Timer $E050 - $E05F
--
when "0101" => -- $E050
cpu_data_in <= timer_data_out;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= cpu_vma;
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
 
--
-- Bus Trap Logic $E060 - $E06F
--
when "0110" => -- $E060
cpu_data_in <= trap_data_out;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= cpu_vma;
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
 
--
-- I/O port $E070 - $E07F
--
when "0111" => -- $E070
cpu_data_in <= ioport_data_out;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= cpu_vma;
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
 
when others => -- $E080 to $E7FF
cpu_data_in <= bus_data;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= cpu_vma;
end case;
--
-- Everything else is RAM
--
when others =>
cpu_data_in <= ram_data_out;
rom_cs <= '0';
dat_cs <= '0';
ram_cs <= cpu_vma;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
end case;
end if;
end process;
 
 
--
-- B5-SRAM Control
-- Processes to read and write memory based on bus signals
--
ram_process: process( cpu_clk, Reset_n,
cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
dat_addr,
ram_cs, ram_wrl, ram_wru, ram_data_out )
begin
ram_csn <= not( ram_cs and Reset_n );
ram_wrl <= (not cpu_addr(0)) and (not cpu_rw) and cpu_clk;
ram_wrln <= not (ram_wrl);
ram_wru <= cpu_addr(0) and (not cpu_rw) and cpu_clk;
ram_wrun <= not (ram_wru);
ram_addr(16 downto 11) <= dat_addr(5 downto 0);
ram_addr(10 downto 0) <= cpu_addr(11 downto 1);
 
if ram_wrl = '1' then
ram_data(7 downto 0) <= cpu_data_out;
else
ram_data(7 downto 0) <= "ZZZZZZZZ";
end if;
 
if ram_wru = '1' then
ram_data(15 downto 8) <= cpu_data_out;
else
ram_data(15 downto 8) <= "ZZZZZZZZ";
end if;
 
if cpu_addr(0) = '1' then
ram_data_out <= ram_data(15 downto 8);
else
ram_data_out <= ram_data(7 downto 0);
end if;
end process;
 
--
-- Compact Flash Control
--
compact_flash: process( Reset_n,
cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
cf_cs, cf_rd, cf_wr, cf_d )
begin
cf_rst_n <= Reset_n;
cf_cs0_n <= not( cf_cs ) or cpu_addr(3);
cf_cs1_n <= not( cf_cs and cpu_addr(3));
cf_wr <= cf_cs and (not cpu_rw);
cf_rd <= cf_cs and cpu_rw;
cf_wr_n <= not cf_wr;
cf_rd_n <= not cf_rd;
cf_a <= cpu_addr(2 downto 0);
if cf_wr = '1' then
cf_d(7 downto 0) <= cpu_data_out;
cf_d(15 downto 8) <= (others => '0');
else
cf_d(7 downto 0) <= (others => 'Z');
cf_d(15 downto 8) <= (others => 'Z');
end if;
cf_data_out <= cf_d(7 downto 0);
end process;
 
--
-- Hold CF access for a few cycles
--
cf_hold_proc: process( cpu_clk, Reset_n )
begin
if Reset_n = '0' then
cf_release <= '0';
cf_count <= "0000";
cf_hold_state <= hold_release_state;
elsif cpu_clk'event and cpu_clk='0' then
case cf_hold_state is
when hold_release_state =>
cf_release <= '0';
if cf_cs = '1' then
cf_count <= "0011";
cf_hold_state <= hold_request_state;
end if;
 
when hold_request_state =>
cf_count <= cf_count - "0001";
if cf_count = "0000" then
cf_release <= '1';
cf_hold_state <= hold_release_state;
end if;
when others =>
null;
end case;
end if;
end process;
 
--
-- Interrupts and other bus control signals
--
interrupts : process( Reset_n,
cf_cs, cf_hold, cf_release,
uart_irq, trap_irq, timer_irq, keyboard_irq
)
begin
cf_hold <= cf_cs and (not cf_release);
cpu_reset <= not Reset_n; -- CPU reset is active high
cpu_irq <= uart_irq or keyboard_irq;
cpu_nmi <= trap_irq;
cpu_firq <= timer_irq;
cpu_halt <= '0';
cpu_hold <= cf_hold;
end process;
 
--
-- CPU bus signals
--
my_bus : process( cpu_clk, cpu_reset, cpu_rw, cpu_addr, cpu_data_out )
begin
bus_clk <= cpu_clk;
bus_reset <= cpu_reset;
bus_rw <= cpu_rw;
bus_addr <= cpu_addr;
if( cpu_rw = '1' ) then
bus_data <= "ZZZZZZZZ";
else
bus_data <= cpu_data_out;
end if;
end process;
 
--
-- flash led to indicate code is working
--
my_LED_Flasher: process (cpu_clk, CountL )
begin
if(cpu_clk'event and cpu_clk = '0') then
countL <= countL + 1;
end if;
LED <= countL(23);
dcd_n <= '0';
end process;
 
--
-- Clock divider
--
my_clock_divider: process( SysClk )
begin
if SysClk'event and SysClk='0' then
clock_div <= clock_div + "01";
end if;
end process;
--
-- Assign VDU VGA colour output
-- only 8 colours are handled.
--
my_vga_out: process( vga_red, vga_green, vga_blue )
begin
red_lo <= vga_red;
red_hi <= vga_red;
green_lo <= vga_green;
green_hi <= vga_green;
blue_lo <= vga_blue;
blue_hi <= vga_blue;
end process;
 
end rtl; --===================== End of architecture =======================--
 
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