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Index: System09_Digilent_3S500E.vhd
===================================================================
--- System09_Digilent_3S500E.vhd (revision 112)
+++ System09_Digilent_3S500E.vhd (nonexistent)
@@ -1,864 +0,0 @@
--- $Id: System09_Digilent_3S500E.vhd,v 1.4 2008-08-20 06:00:55 davidgb Exp $
---===========================================================================----
---
--- S Y N T H E Z I A B L E System09 - SOC.
---
--- This core adheres to the GNU public license
---
--- File name : System09.vhd
---
--- Purpose : Top level file for 6809 compatible system on a chip
--- Designed with Xilinx XC3S500E Spartan 3E FPGA.
--- Implemented With Digilent Xilinx Starter FPGA board,
---
--- Dependencies : ieee.Std_Logic_1164
--- ieee.std_logic_unsigned
--- ieee.std_logic_arith
--- ieee.numeric_std
---
--- Uses : mon_rom (kbug_rom2k.vhd) Monitor ROM
--- cpu09 (cpu09.vhd) CPU core
--- miniuart (minitUART3.vhd) ACIA / MiniUART
--- (rxunit3.vhd)
--- (tx_unit3.vhd)
---
--- Author : John E. Kent
--- dilbert57@opencores.org
---
---===========================================================================----
---
--- Revision History:
---===========================================================================--
--- Version 0.1 - 20 March 2003
--- Version 0.2 - 30 March 2003
--- Version 0.3 - 29 April 2003
--- Version 0.4 - 29 June 2003
---
--- Version 0.5 - 19 July 2003
--- prints out "Hello World"
---
--- Version 0.6 - 5 September 2003
--- Runs SBUG
---
--- Version 1.0- 6 Sep 2003 - John Kent
--- Inverted CLK_50MHZ
--- Initial release to Open Cores
---
--- Version 1.1 - 17 Jan 2004 - John Kent
--- Updated miniUart.
---
--- Version 1.2 - 25 Jan 2004 - John Kent
--- removed signals "test_alu" and "test_cc"
--- Trap hardware re-instated.
---
--- Version 1.3 - 11 Feb 2004 - John Kent
--- Designed forked off to produce System09_VDU
--- Added VDU component
--- VDU runs at 25MHz and divides the clock by 2 for the CPU
--- UART Runs at 57.6 Kbps
---
--- Version 2.0 - 2 September 2004 - John Kent
--- ported to Digilent Xilinx Spartan3 starter board
--- removed Compaact Flash and Trap Logic.
--- Replaced SBUG with KBug9s
---
--- Version 3.0 - 22 April 2006 - John Kent
--- Port to Digilent Spartan 3E Starter board
--- Removed keyboard, vdu, timer, and trap logic
--- added PIA with counters attached.
--- Uses 32Kbytes of internal Block RAM
---
--- Version 4.0 - 8th April 2007 - John kent
--- Added VDU and PS/2 keyboard
--- Updated miniUART to ACIA6850
--- Reduce monitor ROM to 2KB
--- Re-assigned I/O port assignments so it is possible to run KBUG9
--- $E000 - ACIA
--- $E020 - Keyboard
--- $E030 - VDU
--- $E040 - Compact Flash (not implemented)
--- $E050 - Timer
--- $E060 - Bus trap
--- $E070 - Parallel I/O
---
---===========================================================================--
-library ieee;
- use ieee.std_logic_1164.all;
- use IEEE.STD_LOGIC_ARITH.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
- use ieee.numeric_std.all;
-
-entity my_system09 is
- port(
- CLK_50MHZ : in Std_Logic; -- System Clock input
- BTN_SOUTH : in Std_Logic;
-
- -- PS/2 Keyboard
- PS2_CLK : inout Std_logic;
- PS2_DATA : inout Std_Logic;
-
- -- CRTC output signals
- VGA_VSYNC : out Std_Logic;
- VGA_HSYNC : out Std_Logic;
- VGA_BLUE : out std_logic;
- VGA_GREEN : out std_logic;
- VGA_RED : out std_logic;
-
- -- Uart Interface
- RS232_DCE_RXD : in std_logic;
- RS232_DCE_TXD : out std_logic;
-
- -- LEDS & Switches
- LED : out std_logic_vector(7 downto 0)
- );
-end my_system09;
-
--------------------------------------------------------------------------------
--- Architecture for System09
--------------------------------------------------------------------------------
-architecture my_computer of my_system09 is
- -----------------------------------------------------------------------------
- -- constants
- -----------------------------------------------------------------------------
- constant SYS_Clock_Frequency : integer := 50000000; -- FPGA System Clock
- constant PIX_Clock_Frequency : integer := 25000000; -- VGA Pixel Clock
- constant CPU_Clock_Frequency : integer := 25000000; -- CPU Clock
- constant BAUD_Rate : integer := 57600; -- Baud Rate
- constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16;
-
- -----------------------------------------------------------------------------
- -- Signals
- -----------------------------------------------------------------------------
- -- BOOT ROM
- signal rom_cs : Std_logic;
- signal rom_data_out : Std_Logic_Vector(7 downto 0);
-
- -- UART Interface signals
- signal uart_data_out : Std_Logic_Vector(7 downto 0);
- signal uart_cs : Std_Logic;
- signal uart_irq : Std_Logic;
- signal uart_clk : Std_Logic;
- signal rxbit : Std_Logic;
- signal txbit : Std_Logic;
- signal DCD_n : Std_Logic;
- signal RTS_n : Std_Logic;
- signal CTS_n : Std_Logic;
-
- -- timer
- signal timer_data_out : std_logic_vector(7 downto 0);
- signal timer_cs : std_logic;
- signal timer_irq : std_logic;
-
- -- trap
- signal trap_cs : std_logic;
- signal trap_data_out : std_logic_vector(7 downto 0);
- signal trap_irq : std_logic;
-
- -- PIA Interface signals
- signal pia_data_out : Std_Logic_Vector(7 downto 0);
- signal pia_cs : Std_Logic;
- signal pia_irq_a : Std_Logic;
- signal pia_irq_b : Std_Logic;
-
- -- keyboard port
- signal keyboard_data_out : std_logic_vector(7 downto 0);
- signal keyboard_cs : std_logic;
- signal keyboard_irq : std_logic;
-
- -- Video Display Unit
- signal pix_clk : std_logic;
- signal vdu_cs : std_logic;
- signal vdu_data_out : std_logic_vector(7 downto 0);
-
- -- RAM
- signal ram_cs : std_logic; -- memory chip select
- signal ram_data_out : std_logic_vector(7 downto 0);
-
- -- CPU Interface signals
- signal cpu_reset : Std_Logic;
- signal cpu_clk : Std_Logic;
- signal cpu_rw : std_logic;
- signal cpu_vma : std_logic;
- signal cpu_halt : std_logic;
- signal cpu_hold : std_logic;
- signal cpu_firq : std_logic;
- signal cpu_irq : std_logic;
- signal cpu_nmi : std_logic;
- signal cpu_addr : std_logic_vector(15 downto 0);
- signal cpu_data_in : std_logic_vector(7 downto 0);
- signal cpu_data_out : std_logic_vector(7 downto 0);
-
- -- CLK_50MHZ clock divide by 2
- signal clock_div : std_logic_vector(1 downto 0);
- signal SysClk : std_logic;
- signal Reset_n : std_logic;
- signal CountL : std_logic_vector(23 downto 0);
-
------------------------------------------------------------------
---
--- CPU09 CPU core
---
------------------------------------------------------------------
-
-component cpu09
- port (
- clk: in std_logic;
- rst: in std_logic;
- rw: out std_logic; -- Asynchronous memory interface
- vma: out std_logic;
- address: out std_logic_vector(15 downto 0);
- data_in: in std_logic_vector(7 downto 0);
- data_out: out std_logic_vector(7 downto 0);
- halt: in std_logic;
- hold: in std_logic;
- irq: in std_logic;
- nmi: in std_logic;
- firq: in std_logic
- );
-end component;
-
-
-----------------------------------------
---
--- Block RAM Monitor ROM
---
-----------------------------------------
-component mon_rom
- Port (
- clk : in std_logic;
- rst : in std_logic;
- cs : in std_logic;
- rw : in std_logic;
- addr : in std_logic_vector (10 downto 0);
- rdata : out std_logic_vector (7 downto 0);
- wdata : in std_logic_vector (7 downto 0)
- );
-end component;
-
-----------------------------------------
---
--- Block RAM Monitor
---
-----------------------------------------
-component ram_32k
- Port (
- clk : in std_logic;
- rst : in std_logic;
- cs : in std_logic;
- rw : in std_logic;
- addr : in std_logic_vector (14 downto 0);
- rdata : out std_logic_vector (7 downto 0);
- wdata : in std_logic_vector (7 downto 0)
- );
-end component;
-
------------------------------------------------------------------
---
--- 6822 compatible PIA with counters
---
------------------------------------------------------------------
-
-component pia_timer
- port (
- clk : in std_logic;
- rst : in std_logic;
- cs : in std_logic;
- rw : in std_logic;
- addr : in std_logic_vector(1 downto 0);
- data_in : in std_logic_vector(7 downto 0);
- data_out : out std_logic_vector(7 downto 0);
- irqa : out std_logic;
- irqb : out std_logic
- );
-end component;
-
-
------------------------------------------------------------------
---
--- 6850 ACIA/UART
---
------------------------------------------------------------------
-
-component ACIA_6850
- port (
- clk : in Std_Logic; -- System Clock
- rst : in Std_Logic; -- Reset input (active high)
- cs : in Std_Logic; -- miniUART Chip Select
- rw : in Std_Logic; -- Read / Not Write
- irq : out Std_Logic; -- Interrupt
- Addr : in Std_Logic; -- Register Select
- DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
- DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
- RxC : in Std_Logic; -- Receive Baud Clock
- TxC : in Std_Logic; -- Transmit Baud Clock
- RxD : in Std_Logic; -- Receive Data
- TxD : out Std_Logic; -- Transmit Data
- DCD_n : in Std_Logic; -- Data Carrier Detect
- CTS_n : in Std_Logic; -- Clear To Send
- RTS_n : out Std_Logic ); -- Request To send
-end component;
-
------------------------------------------------------------------
---
--- ACIA Clock divider
---
------------------------------------------------------------------
-
-component ACIA_Clock
- generic (
- SYS_Clock_Frequency : integer := SYS_Clock_Frequency;
- ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
- );
- port (
- clk : in Std_Logic; -- System Clock Input
- ACIA_clk : out Std_logic -- ACIA Clock output
- );
-end component;
-
-----------------------------------------
---
--- Timer module
---
-----------------------------------------
-
-component timer
- port (
- clk : in std_logic;
- rst : in std_logic;
- cs : in std_logic;
- rw : in std_logic;
- addr : in std_logic;
- data_in : in std_logic_vector(7 downto 0);
- data_out : out std_logic_vector(7 downto 0);
- irq : out std_logic
- -- ;
- -- timer_in : in std_logic;
- -- timer_out : out std_logic
- );
-end component;
-
-------------------------------------------------------------
---
--- Bus Trap logic
---
-------------------------------------------------------------
-
-component trap
- port (
- clk : in std_logic;
- rst : in std_logic;
- cs : in std_logic;
- rw : in std_logic;
- vma : in std_logic;
- addr : in std_logic_vector(15 downto 0);
- data_in : in std_logic_vector(7 downto 0);
- data_out : out std_logic_vector(7 downto 0);
- irq : out std_logic
- );
-end component;
-
-----------------------------------------
---
--- PS/2 Keyboard
---
-----------------------------------------
-
-component keyboard
- generic(
- KBD_Clock_Frequency : integer := CPU_Clock_Frequency
- );
- port(
- clk : in std_logic;
- rst : in std_logic;
- cs : in std_logic;
- rw : in std_logic;
- addr : in std_logic;
- data_in : in std_logic_vector(7 downto 0);
- data_out : out std_logic_vector(7 downto 0);
- irq : out std_logic;
- kbd_clk : inout std_logic;
- kbd_data : inout std_logic
- );
-end component;
-
-----------------------------------------
---
--- Video Display Unit.
---
-----------------------------------------
-component vdu8
- generic(
- VDU_CLOCK_FREQUENCY : integer := CPU_Clock_Frequency; -- HZ
- VGA_CLOCK_FREQUENCY : integer := PIX_Clock_Frequency; -- HZ
- VGA_HOR_CHARS : integer := 80; -- CHARACTERS
- VGA_VER_CHARS : integer := 25; -- CHARACTERS
- VGA_PIXELS_PER_CHAR : integer := 8; -- PIXELS
- VGA_LINES_PER_CHAR : integer := 16; -- LINES
- VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS
- VGA_HOR_SYNC : integer := 96; -- PIXELS
- VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS
- VGA_VER_BACK_PORCH : integer := 13; -- LINES
- VGA_VER_SYNC : integer := 1; -- LINES
- VGA_VER_FRONT_PORCH : integer := 36 -- LINES
- );
- port(
- -- control register interface
- vdu_clk : in std_logic; -- CPU Clock - 12.5MHz
- vdu_rst : in std_logic;
- vdu_cs : in std_logic;
- vdu_rw : in std_logic;
- vdu_addr : in std_logic_vector(2 downto 0);
- vdu_data_in : in std_logic_vector(7 downto 0);
- vdu_data_out : out std_logic_vector(7 downto 0);
-
- -- vga port connections
- vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
- vga_red_o : out std_logic;
- vga_green_o : out std_logic;
- vga_blue_o : out std_logic;
- vga_hsync_o : out std_logic;
- vga_vsync_o : out std_logic
- );
-end component;
-
-
-component BUFG
-port (
- i: in std_logic;
- o: out std_logic
- );
-end component;
-
-begin
- -----------------------------------------------------------------------------
- -- Instantiation of internal components
- -----------------------------------------------------------------------------
-
-my_cpu : cpu09 port map (
- clk => cpu_clk,
- rst => cpu_reset,
- rw => cpu_rw,
- vma => cpu_vma,
- address => cpu_addr(15 downto 0),
- data_in => cpu_data_in,
- data_out => cpu_data_out,
- halt => cpu_halt,
- hold => cpu_hold,
- irq => cpu_irq,
- nmi => cpu_nmi,
- firq => cpu_firq
- );
-
-my_rom : mon_rom port map (
- clk => cpu_clk,
- rst => cpu_reset,
- cs => rom_cs,
- rw => '1',
- addr => cpu_addr(10 downto 0),
- rdata => rom_data_out,
- wdata => cpu_data_out
- );
-
-my_ram : ram_32k port map (
- clk => cpu_clk,
- rst => cpu_reset,
- cs => ram_cs,
- rw => cpu_rw,
- addr => cpu_addr(14 downto 0),
- rdata => ram_data_out,
- wdata => cpu_data_out
- );
-
-my_pia : pia_timer port map (
- clk => cpu_clk,
- rst => cpu_reset,
- cs => pia_cs,
- rw => cpu_rw,
- addr => cpu_addr(1 downto 0),
- data_in => cpu_data_out,
- data_out => pia_data_out,
- irqa => pia_irq_a,
- irqb => pia_irq_b
- );
-
-
-----------------------------------------
---
--- ACIA/UART Serial interface
---
-----------------------------------------
-my_ACIA : ACIA_6850 port map (
- clk => cpu_clk,
- rst => cpu_reset,
- cs => uart_cs,
- rw => cpu_rw,
- irq => uart_irq,
- Addr => cpu_addr(0),
- Datain => cpu_data_out,
- DataOut => uart_data_out,
- RxC => uart_clk,
- TxC => uart_clk,
- RxD => rxbit,
- TxD => txbit,
- DCD_n => dcd_n,
- CTS_n => cts_n,
- RTS_n => rts_n
- );
-
-----------------------------------------
---
--- ACIA Clock
---
-----------------------------------------
-my_ACIA_Clock : ACIA_Clock
- generic map(
- SYS_Clock_Frequency => SYS_Clock_Frequency,
- ACIA_Clock_Frequency => ACIA_Clock_Frequency
- )
- port map(
- clk => SysClk,
- acia_clk => uart_clk
- );
-
-
-
-----------------------------------------
---
--- PS/2 Keyboard Interface
---
-----------------------------------------
-my_keyboard : keyboard
- generic map (
- KBD_Clock_Frequency => CPU_Clock_frequency
- )
- port map(
- clk => cpu_clk,
- rst => cpu_reset,
- cs => keyboard_cs,
- rw => cpu_rw,
- addr => cpu_addr(0),
- data_in => cpu_data_out(7 downto 0),
- data_out => keyboard_data_out(7 downto 0),
- irq => keyboard_irq,
- kbd_clk => PS2_CLK,
- kbd_data => PS2_DATA
- );
-
-----------------------------------------
---
--- Video Display Unit instantiation
---
-----------------------------------------
-my_vdu : vdu8
- generic map(
- VDU_CLOCK_FREQUENCY => CPU_Clock_Frequency, -- HZ
- VGA_CLOCK_FREQUENCY => PIX_Clock_Frequency, -- HZ
- VGA_HOR_CHARS => 80, -- CHARACTERS
- VGA_VER_CHARS => 25, -- CHARACTERS
- VGA_PIXELS_PER_CHAR => 8, -- PIXELS
- VGA_LINES_PER_CHAR => 16, -- LINES
- VGA_HOR_BACK_PORCH => 40, -- PIXELS
- VGA_HOR_SYNC => 96, -- PIXELS
- VGA_HOR_FRONT_PORCH => 24, -- PIXELS
- VGA_VER_BACK_PORCH => 13, -- LINES
- VGA_VER_SYNC => 1, -- LINES
- VGA_VER_FRONT_PORCH => 36 -- LINES
- )
- port map(
-
- -- Control Registers
- vdu_clk => cpu_clk, -- 25 MHz System Clock in
- vdu_rst => cpu_reset,
- vdu_cs => vdu_cs,
- vdu_rw => cpu_rw,
- vdu_addr => cpu_addr(2 downto 0),
- vdu_data_in => cpu_data_out,
- vdu_data_out => vdu_data_out,
-
- -- vga port connections
- vga_clk => pix_clk, -- 25 MHz VDU pixel clock
- vga_red_o => vga_red,
- vga_green_o => vga_green,
- vga_blue_o => vga_blue,
- vga_hsync_o => vga_hsync,
- vga_vsync_o => vga_vsync
- );
-
-
-----------------------------------------
---
--- Timer Module
---
-----------------------------------------
-my_timer : timer port map (
- clk => cpu_clk,
- rst => cpu_reset,
- cs => timer_cs,
- rw => cpu_rw,
- addr => cpu_addr(0),
- data_in => cpu_data_out,
- data_out => timer_data_out,
- irq => timer_irq
- -- ,
- -- timer_in => CountL(5)
--- timer_out => timer_out
- );
-
-----------------------------------------
---
--- Bus Trap Interrupt logic
---
-----------------------------------------
-my_trap : trap port map (
- clk => cpu_clk,
- rst => cpu_reset,
- cs => trap_cs,
- rw => cpu_rw,
- vma => cpu_vma,
- addr => cpu_addr,
- data_in => cpu_data_out,
- data_out => trap_data_out,
- irq => trap_irq
- );
-
---
--- 25 MHz CPU clock
---
-cpu_clk_buffer : BUFG port map(
- i => clock_div(0),
- o => cpu_clk
- );
-
---
--- 25 MHz VGA Pixel clock
---
-vga_clk_buffer : BUFG port map(
- i => clock_div(0),
- o => pix_clk
- );
-
-----------------------------------------------------------------------
---
--- Process to decode memory map
---
-----------------------------------------------------------------------
-
-mem_decode: process( cpu_clk, Reset_n,
- cpu_addr, cpu_rw, cpu_vma,
- rom_data_out,
- ram_data_out,
- timer_data_out,
- trap_data_out,
- pia_data_out,
- uart_data_out,
- keyboard_data_out,
- vdu_data_out )
-variable decode_addr : std_logic_vector(3 downto 0);
-begin
--- decode_addr := dat_addr(3 downto 0) & cpu_addr(11);
- decode_addr := cpu_addr(15 downto 12);
-
- case decode_addr is
- --
- -- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF
- --
- when "1111" => -- $F000 - $FFFF
- cpu_data_in <= rom_data_out;
- rom_cs <= cpu_vma; -- read ROM
- ram_cs <= '0';
- uart_cs <= '0';
- timer_cs <= '0';
- trap_cs <= '0';
- pia_cs <= '0';
- keyboard_cs <= '0';
- vdu_cs <= '0';
-
- --
- -- IO Devices $E000 - $EFFF
- --
- when "1110" => -- $E000 - $E7FF
- rom_cs <= '0';
- ram_cs <= '0';
- case cpu_addr(7 downto 4) is
- --
- -- UART / ACIA $E000
- --
- when "0000" => -- $E000
- cpu_data_in <= uart_data_out;
- uart_cs <= cpu_vma;
- timer_cs <= '0';
- trap_cs <= '0';
- pia_cs <= '0';
- keyboard_cs <= '0';
- vdu_cs <= '0';
-
- --
- -- WD1771 FDC sites at $E010-$E01F
- --
- when "0001" => -- $E010
- cpu_data_in <= (others => '0');
- uart_cs <= '0';
- timer_cs <= '0';
- trap_cs <= '0';
- pia_cs <= '0';
- keyboard_cs <= '0';
- vdu_cs <= '0';
-
- --
- -- Keyboard port $E020 - $E02F
- --
- when "0010" => -- $E020
- cpu_data_in <= keyboard_data_out;
- uart_cs <= '0';
- timer_cs <= '0';
- trap_cs <= '0';
- pia_cs <= '0';
- keyboard_cs <= cpu_vma;
- vdu_cs <= '0';
-
- --
- -- VDU port $E030 - $E03F
- --
- when "0011" => -- $E030
- cpu_data_in <= vdu_data_out;
- uart_cs <= '0';
- timer_cs <= '0';
- trap_cs <= '0';
- pia_cs <= '0';
- keyboard_cs <= '0';
- vdu_cs <= cpu_vma;
-
- --
- -- Compact Flash $E040 - $E04F
- --
- when "0100" => -- $E040
- cpu_data_in <= (others => '0');
- uart_cs <= '0';
- timer_cs <= '0';
- trap_cs <= '0';
- pia_cs <= '0';
- keyboard_cs <= '0';
- vdu_cs <= '0';
-
- --
- -- Timer $E050 - $E05F
- --
- when "0101" => -- $E050
- cpu_data_in <= timer_data_out;
- uart_cs <= '0';
- timer_cs <= cpu_vma;
- trap_cs <= '0';
- pia_cs <= '0';
- keyboard_cs <= '0';
- vdu_cs <= '0';
-
- --
- -- Bus Trap Logic $E060 - $E06F
- --
- when "0110" => -- $E060
- cpu_data_in <= trap_data_out;
- uart_cs <= '0';
- timer_cs <= '0';
- trap_cs <= cpu_vma;
- pia_cs <= '0';
- keyboard_cs <= '0';
- vdu_cs <= '0';
-
- --
- -- I/O port $E070 - $E07F
- --
- when "0111" => -- $E070
- cpu_data_in <= pia_data_out;
- uart_cs <= '0';
- timer_cs <= '0';
- trap_cs <= '0';
- pia_cs <= cpu_vma;
- keyboard_cs <= '0';
- vdu_cs <= '0';
-
- when others => -- $E080 to $E7FF
- cpu_data_in <= (others => '0');
- uart_cs <= '0';
- timer_cs <= '0';
- trap_cs <= '0';
- pia_cs <= '0';
- keyboard_cs <= '0';
- vdu_cs <= '0';
- end case;
-
- --
- -- $8000 to $DFFF = null
- --
- when "1101" | "1100" | "1011" | "1010" |
- "1001" | "1000" =>
- cpu_data_in <= (others => '0');
- rom_cs <= '0';
- ram_cs <= '0';
- uart_cs <= '0';
- timer_cs <= '0';
- trap_cs <= '0';
- pia_cs <= '0';
- keyboard_cs <= '0';
- vdu_cs <= '0';
- --
- -- Everything else is RAM
- --
- when others =>
- cpu_data_in <= ram_data_out;
- rom_cs <= '0';
- ram_cs <= cpu_vma;
- uart_cs <= '0';
- timer_cs <= '0';
- trap_cs <= '0';
- pia_cs <= '0';
- keyboard_cs <= '0';
- vdu_cs <= '0';
- end case;
-end process;
-
---
--- Interrupts and other bus control signals
---
-interrupts : process( Reset_n,
- pia_irq_a, pia_irq_b, uart_irq, trap_irq, timer_irq, keyboard_irq
- )
-begin
- cpu_reset <= not Reset_n; -- CPU reset is active high
- cpu_irq <= uart_irq or keyboard_irq;
- cpu_nmi <= pia_irq_a or trap_irq;
- cpu_firq <= pia_irq_b or timer_irq;
- cpu_halt <= '0';
- cpu_hold <= '0';
-end process;
-
---
---
-my_led_flasher: process( SysClk, Reset_n, CountL )
-begin
- if Reset_n = '0' then
- CountL <= "000000000000000000000000";
- elsif(SysClk'event and SysClk = '0') then
- CountL <= CountL + 1;
- end if;
- LED(7 downto 0) <= CountL(23 downto 16);
-end process;
-
---
--- Clock divider
---
-my_clock_divider: process( SysClk )
-begin
- if SysClk'event and SysClk='0' then
- clock_div <= clock_div + "01";
- end if;
-end process;
-
-DCD_n <= '0';
-CTS_n <= '0';
-Reset_n <= not BTN_SOUTH; -- CPU reset is active high
-SysClk <= CLK_50MHZ;
-rxbit <= RS232_DCE_RXD;
-RS232_DCE_TXD <= txbit;
-
-end my_computer; --===================== End of architecture =======================--
-
Index: my_system09.prj
===================================================================
--- my_system09.prj (revision 112)
+++ my_system09.prj (nonexistent)
@@ -1,17 +0,0 @@
-vhdl work "../VHDL/ACIA_Clock.vhd"
-vhdl work "../Spartan3/keymap_rom_slice.vhd"
-vhdl work "../VHDL/ps2_keyboard.vhd"
-vhdl work "../VHDL/ACIA_TX.vhd"
-vhdl work "../VHDL/ACIA_RX.vhd"
-vhdl work "../Spartan3/ram2k_b16.vhd"
-vhdl work "../Spartan3/char_rom2k_b16.vhd"
-vhdl work "../VHDL/vdu8.vhd"
-vhdl work "../VHDL/trap.vhd"
-vhdl work "../VHDL/timer.vhd"
-vhdl work "../VHDL/pia_timer.vhd"
-vhdl work "../VHDL/keyboard.vhd"
-vhdl work "../VHDL/cpu09.vhd"
-vhdl work "../VHDL/ACIA_6850.vhd"
-vhdl work "../Spartan3/sys09bug_s3e_rom2k_b16.vhd"
-vhdl work "../Spartan3/ram32k_b16.vhd"
-vhdl work "System09_Digilent_3S500E.vhd"
Index: Makefile
===================================================================
--- Makefile (revision 112)
+++ Makefile (nonexistent)
@@ -1,108 +0,0 @@
-#===================================================================
-# File: Makefile
-# Author: David Burnette
-# Created: July 5, 2007
-#
-# Description:
-# Makefile to build the System09 by John Kent
-#
-# This makefile will build John Kent's entire System09 project
-# (RTL synthesis and monitor ROMs) and even download the final
-# bitstream to the prototype board.
-#
-# You can use Xilinx ISE interactively to add new RTL source files
-# to this project.
-#
-# Usage:
-# Use 'make help' to get a list of options.
-#
-# Dependencies:
-# Depends on makefile fragments in the 'MKFRAGS' directory.
-#
-# Revision History:
-# dgb 2007-07-05 Original version
-#
-# dgb 2008-04-07 Split out files into fragments. Modified
-# ROM source generation to be per src directory.
-#
-#===================================================================
-
-MKFRAGS := ../../mkfiles
-export MKFRAGS
-
-#===================================================================
-# User-modifiable variables
-#
-# This name must match the name of the design in Xilinx ISE (case
-# sensitive).
-DESIGN_NAME := my_system09
-#
-# Constraint file (unfortunately it cannot be extracted from ISE)
-UCF_FILE := System09_Digilent_3S500E.ucf
-#
-# Technology family (unfortunately it cannot be extracted from ISE)
-FAMILY := spartan3
-
-# List of ROM VHDL files
-.PHONY: roms
-roms:
- @$(MAKE) -C ../../src/sys09bug sys09s3e.vhd
- @$(MAKE) -C ../../src/Flex9 flex9cf8.vhd
-
-#===================================================================
-# You should not need to edit anything below this line
-
-include ../../mkfiles/xilinx_rules.mk
-
-#===================================================================
-# TARGETS
-
-.PHONY: all
-all: bit
-
-.PHONY: bit
-bit: roms $(DESIGN_NAME).bit
-
-.PHONY: impact
-impact: roms bit do_impact
-
-prom: roms $(DESIGN_NAME).mcs
-
-.PHONY: help
-help:
- @$(ECHO) "Use this Makefile to regenerate the entire System09 bitstream"
- @$(ECHO) "after modifying any of the source RTL or 6809 assembler code."
- @$(ECHO) ""
- @$(ECHO) "This makefile uses the following project files from the Xilinx ISE"
- @$(ECHO) " $(XST_FILE)"
- @$(ECHO) ""
- @$(ECHO) "You use Xilinx ISE interactively to add new RTL source files."
- @$(ECHO) ""
- @$(ECHO) " Availiable targets"
- @$(ECHO)
- @$(ECHO) " For building all or part of the system:"
- @$(ECHO) " roms - Run asm09 and then generate the VHDL RTL rom files"
- @$(ECHO) " bit - Rebuild the entire system and generate the bitstream file"
- @$(ECHO) " all - Rebuild everything"
- @$(ECHO) " prom - Rebuild the entire system and generate an MCS prom file"
- @$(ECHO) " exo - Rebuild the entire system and generate an EXO prom file"
- @$(ECHO)
- @$(ECHO) " For downloading the bitstream to the board:"
- @$(ECHO) " impact - Download the bitstream to the FPGA via iMPACT"
- @$(ECHO)
- @$(ECHO) " For project maintenance:"
- @$(ECHO) " help - Print this help text"
- @$(ECHO) " clean - Clean up the ISE files"
- @$(ECHO) ""
-
-.PHONY: clean
-clean:
- -$(MAKE) -C ../../src/sys09bug clean
- -$(MAKE) -C ../../src/Flex9 clean
- -$(RM) *.ncd *.ngc *.ngd *.twr *.bit *.mcs *.stx *.ucf.untf *.mrp
- -$(RM) *.ncl *.ngm *.prm *_pad.txt *.twx *.log *.syr *.par *.exo *.xpi
- -$(RM) *.cmd_log *.ngr *.bld *_summary.html *.nc1 *.pcf *.bgn
- -$(RM) *.pad *.placed_ncd_tracker *.routed_ncd_tracker *_pad.csv *.drc
- -$(RM) *.pad_txt $(DESIGN_NAME)_impact.cmd *.unroutes
- -$(RMDIR) _ngo _xmsgs
-
Index: my_system09.lso
===================================================================
--- my_system09.lso (revision 112)
+++ my_system09.lso (nonexistent)
@@ -1 +0,0 @@
-work
Index: System09_Digilent_3S500E.ucf
===================================================================
--- System09_Digilent_3S500E.ucf (revision 112)
+++ System09_Digilent_3S500E.ucf (nonexistent)
@@ -1,276 +0,0 @@
-#####################################################
-### SPARTAN-3E STARTER KIT BOARD CONSTRAINTS FILE
-#####################################################
-# ==== Analog-to-Digital Converter (ADC) ====
-# some connections shared with SPI Flash, DAC, ADC, and AMP
-#-NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6
-# ==== Programmable Gain Amplifier (AMP) ====
-# some connections shared with SPI Flash, DAC, ADC, and AMP
-#-NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6
-#-NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33
-#-NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6
-# ==== Pushbuttons (BTN) ====
-#-NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN
-#-NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN
-NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
-#-NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN
-# ==== Clock inputs (CLK) ====
-NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
-# Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
-NET "CLK_50MHZ" PERIOD = 20 ns HIGH 40 %;
-#-NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33
-#-NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33
-# ==== Digital-to-Analog Converter (DAC) ====
-# some connections shared with SPI Flash, DAC, ADC, and AMP
-#-NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8
-#-NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8
-# ==== 1-Wire Secure EEPROM (DS)
-#-NET "DS_WIRE" LOC = "U4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8
-# ==== Ethernet PHY (E) ====
-#-NET "E_COL" LOC = "U6" | IOSTANDARD = LVCMOS33
-#-NET "E_CRS" LOC = "U13" | IOSTANDARD = LVCMOS33
-#-NET "E_MDC" LOC = "P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8
-#-NET "E_MDIO" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8
-#-NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33
-#-NET "E_RX_DV" LOC = "V2" | IOSTANDARD = LVCMOS33
-#-NET "E_RXD<0>" LOC = "V8" | IOSTANDARD = LVCMOS33
-#-NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33
-#-NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33
-#-NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33
-#-NET "E_RXD<4>" LOC = "U14" | IOSTANDARD = LVCMOS33
-#-NET "E_TX_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33
-#-NET "E_TX_EN" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8
-#-NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8
-#-NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8
-#-NET "E_TXD<2>" LOC = "R5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8
-#-NET "E_TXD<3>" LOC = "T5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8
-#-NET "E_TXD<4>" LOC = "R6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8
-# ==== FPGA Configuration Mode, INIT_B Pins (FPGA) ====
-#-NET "FPGA_M0" LOC = "M10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8
-#-NET "FPGA_M1" LOC = "V11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8
-#-NET "FPGA_M2" LOC = "T10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8
-#-NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4
-#-NET "FPGA_RDWR_B" LOC = "U10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4
-#-NET "FPGA_HSWAP" LOC = "B3" | IOSTANDARD = LVCMOS33
-# ==== FX2 Connector (FX2) ====
-#-NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33
-#-NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-# These four connections are shared with the J1 6-pin accessory header
-#-NET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<3>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<4>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-# These four connections are shared with the J2 6-pin accessory header
-#-NET "FX2_IO<5>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<6>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<7>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<8>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-# These four connections are shared with the J4 6-pin accessory header
-#-NET "FX2_IO<9>" LOC = "D7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<10>" LOC = "C7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<11>" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<12>" LOC = "E8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-# The discrete LEDs are shared with the following 8 FX2 connections
-#NET "FX2_IO<13>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#NET "FX2_IO<14>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<21>" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<22>" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<23>" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<24>" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<25>" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<26>" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<30>" LOC = "C4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<33>" LOC = "A8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<34>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IP<35>" LOC = "D12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IP<36>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IP<37>" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IP<38>" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IO<39>" LOC = "C3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-#-NET "FX2_IP<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8
-# ==== 6-pin header J1 ====
-# These are shared connections with the FX2 connector
-#NET "J1<0>" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6
-#NET "J1<1>" LOC = "A4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6
-#NET "J1<2>" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6
-#NET "J1<3>" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6
-# ==== 6-pin header J2 ====
-# These are shared connections with the FX2 connector
-#NET "J2<0>" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6
-#NET "J2<1>" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6
-#NET "J2<2>" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6
-#NET "J2<3>" LOC = "F7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6
-# ==== 6-pin header J4 ====
-# These are shared connections with the FX2 connector
-#NET "J4<0>" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6
-#NET "J4<1>" LOC = "C7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6
-#NET "J4<2>" LOC = "F8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6
-#NET "J4<3>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6
-# ==== Character LCD (LCD) ====
-#-NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-# LCD data connections are shared with StrataFlash connections SF_D<11:8>
-#NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-# ==== Discrete LEDs (LED) ====
-# These are shared connections with the FX2 connector
-NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
-NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
-NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
-NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
-NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
-NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
-NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
-NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
-# ==== PS/2 Mouse/Keyboard Port (PS2) ====
-NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
-NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
-# ==== Rotary Pushbutton Switch (ROT) ====
-#-NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP
-#-NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP
-#-NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN
-# ==== RS-232 Serial Ports (RS232) ====
-NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL ;
-NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
-#-NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL
-#-NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW
-# ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)
-#-NET "SD_A<0>" LOC = "T1" | IOSTANDARD = SSTL2_I
-#-NET "SD_A<1>" LOC = "R3" | IOSTANDARD = SSTL2_I
-#-NET "SD_A<2>" LOC = "R2" | IOSTANDARD = SSTL2_I
-#-NET "SD_A<3>" LOC = "P1" | IOSTANDARD = SSTL2_I
-#-NET "SD_A<4>" LOC = "F4" | IOSTANDARD = SSTL2_I
-#-NET "SD_A<5>" LOC = "H4" | IOSTANDARD = SSTL2_I
-#-NET "SD_A<6>" LOC = "H3" | IOSTANDARD = SSTL2_I
-#-NET "SD_A<7>" LOC = "H1" | IOSTANDARD = SSTL2_I
-#-NET "SD_A<8>" LOC = "H2" | IOSTANDARD = SSTL2_I
-#-NET "SD_A<9>" LOC = "N4" | IOSTANDARD = SSTL2_I
-#-NET "SD_A<10>" LOC = "T2" | IOSTANDARD = SSTL2_I
-#-NET "SD_A<11>" LOC = "N5" | IOSTANDARD = SSTL2_I
-#-NET "SD_A<12>" LOC = "P2" | IOSTANDARD = SSTL2_I
-#-NET "SD_BA<0>" LOC = "K5" | IOSTANDARD = SSTL2_I
-#-NET "SD_BA<1>" LOC = "K6" | IOSTANDARD = SSTL2_I
-#-NET "SD_CAS" LOC = "C2" | IOSTANDARD = SSTL2_I
-#-NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I
-#-NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I
-#-NET "SD_CKE" LOC = "K3" | IOSTANDARD = SSTL2_I
-#-NET "SD_CS" LOC = "K4" | IOSTANDARD = SSTL2_I
-#-NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I
-#-NET "SD_DQ<1>" LOC = "L1" | IOSTANDARD = SSTL2_I
-#-NET "SD_DQ<2>" LOC = "L3" | IOSTANDARD = SSTL2_I
-#-NET "SD_DQ<3>" LOC = "L4" | IOSTANDARD = SSTL2_I
-#-NET "SD_DQ<4>" LOC = "M3" | IOSTANDARD = SSTL2_I
-#-NET "SD_DQ<5>" LOC = "M4" | IOSTANDARD = SSTL2_I
-#-NET "SD_DQ<6>" LOC = "M5" | IOSTANDARD = SSTL2_I
-#-NET "SD_DQ<7>" LOC = "M6" | IOSTANDARD = SSTL2_I
-#-NET "SD_DQ<8>" LOC = "E2" | IOSTANDARD = SSTL2_I
-#-NET "SD_DQ<9>" LOC = "E1" | IOSTANDARD = SSTL2_I
-#-NET "SD_DQ<10>" LOC = "F1" | IOSTANDARD = SSTL2_I
-#-NET "SD_DQ<11>" LOC = "F2" | IOSTANDARD = SSTL2_I
-#-NET "SD_DQ<12>" LOC = "G6" | IOSTANDARD = SSTL2_I
-#-NET "SD_DQ<13>" LOC = "G5" | IOSTANDARD = SSTL2_I
-#-NET "SD_DQ<14>" LOC = "H6" | IOSTANDARD = SSTL2_I
-#-NET "SD_DQ<15>" LOC = "H5" | IOSTANDARD = SSTL2_I
-#-NET "SD_LDM" LOC = "J2" | IOSTANDARD = SSTL2_I
-#-NET "SD_LDQS" LOC = "L6" | IOSTANDARD = SSTL2_I
-#-NET "SD_RAS" LOC = "C1" | IOSTANDARD = SSTL2_I
-#-NET "SD_UDM" LOC = "J1" | IOSTANDARD = SSTL2_I
-#-NET "SD_UDQS" LOC = "G3" | IOSTANDARD = SSTL2_I
-#-NET "SD_WE" LOC = "D1" | IOSTANDARD = SSTL2_I
-# Path to allow connection to top DCM connection
-#-NET "SD_CK_FB" LOC = "B9" | IOSTANDARD = LVCMOS33
-# Prohibit VREF pins
-CONFIG PROHIBIT = D2;
-CONFIG PROHIBIT = G4;
-CONFIG PROHIBIT = J6;
-CONFIG PROHIBIT = L5;
-CONFIG PROHIBIT = R4;
-# ==== Intel StrataFlash Parallel NOR Flash (SF) ====
-#-NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33
-#-NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-# ==== STMicro SPI serial Flash (SPI) ====
-# some connections shared with SPI Flash, DAC, ADC, and AMP
-#-NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33
-#-NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6
-#-NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6
-#-NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6
-#-NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6
-# ==== Slide Switches (SW) ====
-#-NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP
-#-NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP
-#-NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP
-#-NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP
-# ==== VGA Port (VGA) ====
-NET "VGA_BLUE" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
-NET "VGA_GREEN" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
-NET "VGA_HSYNC" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
-NET "VGA_RED" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
-NET "VGA_VSYNC" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
-# ==== Xilinx CPLD (XC) ====
-#-NET "XC_CMD<0>" LOC = "P18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW
-#-NET "XC_CMD<1>" LOC = "N18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW
-#-NET "XC_CPLD_EN" LOC = "B10" | IOSTANDARD = LVTTL
-#-NET "XC_D<0>" LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW
-#-NET "XC_D<1>" LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW
-#-NET "XC_D<2>" LOC = "F17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW
-#-NET "XC_TRIG" LOC = "R17" | IOSTANDARD = LVCMOS33
-#-NET "XC_GCK0" LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
-#-NET "GCLK10" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW
Index: system09_digilent_3s500e.mcs
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system09_digilent_3s500e.mcs
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--- . (revision 112)
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## -1,32 +0,0 ##
-*.ngr
-*.ngd
-*.ncd
-*.msk
-*.par
-*.pad
-*.stx
-*.syr
-*.twx
-*.twr
-*.ntrc_log
-*.ngm
-*.mrp
-*.xpi
-*.unroutes
-*.log
-*.bit
-*.bld
-*.bgn
-xst_tmp_dirs
-xst
-*.prm
-*.pcf
-*.ngc
-*.mcs
-*.drc
-*_pad.txt
-*_pad.csv
-_ngo
-*_usage.xml
-tmp.ut
-*_impact.cmd