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    /System09/trunk/rtl/Spartan2
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Rev 22 → Rev 66

/sys09bug_rom2k_b4.vhd
0,0 → 1,218
--
-- sys09bug_rom2k_b4.vhd
--
-- SYS09BUG Monitor ROM for the 6809
-- Using 4 x RAMB4_S8 in the XC2S300e
--
-- John Kent
-- 3rd February 2007
-- Has the same entity name as SBUG so
-- it can be easily exchanged.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.vcomponents.all;
 
entity mon_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
wdata : in std_logic_vector (7 downto 0);
rdata : out std_logic_vector (7 downto 0)
);
end mon_rom;
 
architecture rtl of mon_rom is
 
signal rdata0 : std_logic_vector (7 downto 0);
signal rdata1 : std_logic_vector (7 downto 0);
signal rdata2 : std_logic_vector (7 downto 0);
signal rdata3 : std_logic_vector (7 downto 0);
 
signal ena0 : std_logic;
signal ena1 : std_logic;
signal ena2 : std_logic;
signal ena3 : std_logic;
 
signal we : std_logic;
 
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
);
 
port (
clk, we, en, rst : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component RAMB4_S8;
 
begin
 
ROM0 : RAMB4_S8
generic map (
INIT_00 => x"A780A610C6C0DF8E106DFE8E2EFA1AFB1EFB8FFBCAFCB5FC97FC9DFC61F814F8",
INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC65B0117E0DFBF00E08EF9265AA0",
INIT_02 => x"03179FFE8E0C0417F62A5A19048B0327856D0DC64FD0DF8E4703177DFE8E9B04",
INIT_03 => x"17408B981F4F04175E86092C2081891FF1270D817F84330417B30217A6FE8E2E",
INIT_04 => x"20F00217A8FE8EF5266DFE8C02300F2780E137FE8E20C0022F60C14304174804",
INIT_05 => x"17A4A60B0417A50317211F650217AEFE8E121F2D296B03173B341FBC2094ADC0",
INIT_06 => x"27A4A1A4A7390F260D8117275E81DD271881E127088111285E0317030417A503",
INIT_07 => x"0B031705201F30C0DF8E321FA20217BE203F31C2202131E103173F86E4031708",
INIT_08 => x"279603170527E4AC011FF0C4201F0634F0C41000C3101F390124E1AC20340629",
INIT_09 => x"265A8A03172C031780A610C69203172E0317E4AEEE0117AEFE8E103439623203",
INIT_0a => x"29B70217BC20EE265A7303172E8602237E810425208180A610C6E1AE820317F5",
INIT_0b => x"3984A73F86A4AFA0A709273F8184A60F271035558DFFFF8E10341A24C0DF8C1E",
INIT_0c => x"4AAF0427268D1F304AAE431F39FB265A188D08C6E3DF8E104203163F86450317",
INIT_0d => x"A7A0A7A0A7FF8684A7A4A604263F8184A60A24C0DF8C21AEB9FE16480217068D",
INIT_0e => x"0186398D46E0B7E086408D393D3139F7265A0427A1ACA0A608C6E3DF8E1039A0",
INIT_0f => x"178D47E0B7208645E0B744E0B743E0B74F42E0B701862D8D47E0B7EF8641E0B7"
)
 
port map (
clk => clk,
en => ena0,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => rdata0
);
 
ROM1 : RAMB4_S8
generic map (
INIT_00 => x"E0B6F926808547E0B63B341F4AAF00C08EF42600C28C80A740E0B6218D00C08E",
INIT_01 => x"54545454A6E6D0DF8E104444444462A6363439F927088547E0B639F227408547",
INIT_02 => x"FCBD8435FD265A20C60434B63562E762EA62A70F8462A65858585853A6E6E4E7",
INIT_03 => x"0234A80117F12631813D2739811F0217F9265381260217E2DF7F6402171186DF",
INIT_04 => x"E0EB02340C2904358E01170434E46AE46AE4EBE0EBE0E6103421299101172629",
INIT_05 => x"0117E26F0E02161386E2DF731602173F86BA27FFC102355FEB2080A70527E46A",
INIT_06 => x"2320008310062762A3E4ECF501171286DFFCBDE4AF0130492562AC4D2930344A",
INIT_07 => x"1780A684EB63EB62EB68011762AE750117981F03CB2F0017EFFE8E64E720C602",
INIT_08 => x"10347120028D396532B301171486C326E4AC62AF5B0117981F53F526646A6501",
INIT_09 => x"8D618D394AAF0229F68DF28D910017E50016F800169D01169035690017A0FE8E",
INIT_0a => x"498D3944AF0229D58DD18D5E8D3946AF0229E08DDC8D728D3948AF0229EB8DE7",
INIT_0b => x"8D3941A70229B18DB08D588D3942A70229BC8DBB8D6C8D3943A70229C78DC68D",
INIT_0c => x"BF0016311FF48DB2FE8E39F726048180A63B011739C4A7808A0429A68DA58D5F",
INIT_0d => x"8DC4FE8EE12044AED78DCAFE8EB4001643A6E18DD0FE8EF42048AEEA8DBEFE8E",
INIT_0e => x"D02042A6B38DDBFE8ED92041A6BC8DD6FE8ECF204AAEC58DB8FE8ED82046AECE",
INIT_0f => x"AEFE8EBF8DB88DB08DA98DA18D27FF17AEFE8E900016E7FE8EC4A6AA8DE0FE8E"
)
 
port map (
clk => clk,
en => ena1,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => rdata1
);
 
ROM2 : RAMB4_S8
generic map (
INIT_00 => x"3C29088D011F42290E8DB400172D86121F4D29098DD520CE8DC78DC08D17FF17",
INIT_01 => x"811D253081578D39E0AB04342829078D891F484848483229118D903561A71034",
INIT_02 => x"3439021A39578003226681072561813937800322468112254181393080032239",
INIT_03 => x"C602344D20078B022F3981308B0F840235048D4444444402340235028D023510",
INIT_04 => x"BE10342D207F84048D0627E2DF7D8235F1265A3B8D3F8D2D860225E46880A608",
INIT_05 => x"B605260185E0DF9FA60234903501A6EE27018584A620E08E0926018584A6E0DF",
INIT_06 => x"BE138D903501A70235FA27028584A6E0DFBE1234458D2086008D8235018520E0",
INIT_07 => x"E703E702A7FBDFFD0000CC30E08E39E2DFB7FF86016D84A7118684A70386E0DF",
INIT_08 => x"810D20748D0427FEDF7D30E08E16345986028D1B86FEDF7F01E702C6FDDFFD04",
INIT_09 => x"8E0027101A816C0027101B814100271008819635C5001784A70520098D042420",
INIT_0a => x"5CFBDFFC51260A81110027100B812C0027100C81990027100D81450027101681",
INIT_0b => x"DFB66800164A3327FBDFB67400165A3C0027105DFBDFFC9900168300261019C1",
INIT_0c => x"54816E002710598116273DC1FEDFF65800160000CC5B00162500271050814CFB",
INIT_0d => x"ED224F812080FEDF7F39FDDFB70426FDDF7D39FEDF7F39FEDFB704263D813127",
INIT_0e => x"26508102A74C84E720C6FBDFB6168D0000CC1B20E12218C120C0FDDF7FFDDFF6",
INIT_0f => x"5AEA2619C15C4FF02650814CFBDFFC3903E702A7FBDFFDFCDFF64F39FEDF7FF7"
)
 
port map (
clk => clk,
en => ena2,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => rdata2
);
 
ROM3 : RAMB4_S8
generic map (
INIT_00 => x"FCDFF6F42650C15C84A702E7FBDFF72086FBDFF604E75F012519C15C04E6E78D",
INIT_01 => x"7FFB0369FB0274FB0139FEDFF702E7FBDFF75FE4205F03E7FCDFF7082719C15C",
INIT_02 => x"F84DBCFA505EFA4CA5F847FDF8455CF94248FB1953FB183DFB1531FB105EFB04",
INIT_03 => x"000A0DFFFFFFFF94F9A7F8A7F8A7F8A7F894F9D5F94488F958F1F853EDFB52A8",
INIT_04 => x"4B04202D2020303033582D354220524F4620342E312047554239305359530000",
INIT_05 => x"2020043D43502020043D5053202004202D20043F54414857043E040000000A0D",
INIT_06 => x"043D422020043D412020043D50442020043D58492020043D59492020043D5355",
INIT_07 => x"000000000000000000000000000004315343565A4E4948464504203A43432020",
INIT_08 => x"300B2784AC1084AF1084EEAA558E10A0D08E84A7F086FB264A80A70F86F0FF8E",
INIT_09 => x"2DA7D0DF8E10C0DFCE10FDFFB74444444443101F84EFD620ED26A0F08C00F089",
INIT_0a => x"1084AF10AA558E1084EE2227A0F08C00F08930FB2A4AA66F0C862FA7F0862E6F",
INIT_0b => x"2EA7D0DF8E10F186D520A5A70F88891F44444444101FD0DF8E1084EFE92684AC",
INIT_0c => x"8EF32D0C814C80E7A66F0427A6E6211F4F2CE7A66F1420F92A4A0526A6E60C86",
INIT_0d => x"9F6EC6DF9F6EC4DF9F6EC0DF9F6E62F816E2DFF753F9265A80A7A0A610C6F0FF",
INIT_0e => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
INIT_0f => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
)
 
port map (
clk => clk,
en => ena3,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => rdata3
);
 
my_sys09bug_b4 : process ( cs, rw, addr, rdata0, rdata1, rdata2, rdata3 )
begin
case addr(10 downto 9) is
when "00" =>
ena0 <= cs;
ena1 <= '0';
ena2 <= '0';
ena3 <= '0';
rdata <= rdata0;
when "01" =>
ena0 <= '0';
ena1 <= cs;
ena2 <= '0';
ena3 <= '0';
rdata <= rdata1;
when "10" =>
ena0 <= '0';
ena1 <= '0';
ena2 <= cs;
ena3 <= '0';
rdata <= rdata2;
when "11" =>
ena0 <= '0';
ena1 <= '0';
ena2 <= '0';
ena3 <= cs;
rdata <= rdata3;
when others =>
null;
end case;
 
we <= not rw;
 
end process;
 
end architecture rtl;
 
/sbug_rom2k_b4.vhd
0,0 → 1,213
--
-- sbug_rom.vhd
--
-- SBUG Monitor ROM for the 6809
-- Using 4 x RAMB4_S8 in the XC2S300e
--
-- John Kent
-- 21 November 2004
-- Renamed "sbug_rom" to "mon_rom" so that
-- other monitor ROMs such as KBug9
-- can be substituted
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.vcomponents.all;
 
entity mon_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
wdata : in std_logic_vector (7 downto 0);
rdata : out std_logic_vector (7 downto 0)
);
end mon_rom;
 
architecture rtl of monitor_rom is
 
signal dout0 : std_logic_vector (7 downto 0);
signal dout1 : std_logic_vector (7 downto 0);
signal dout2 : std_logic_vector (7 downto 0);
signal dout3 : std_logic_vector (7 downto 0);
 
signal ena0 : std_logic;
signal ena1 : std_logic;
signal ena2 : std_logic;
signal ena3 : std_logic;
 
signal we : std_logic;
 
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
);
 
port (
clk, we, en, rst : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component RAMB4_S8;
 
begin
 
ROM0 : RAMB4_S8
generic map (
INIT_00 => x"A780A610C6C0DF8E104FFE8E81FBADFDB1FDBDFDEEFDDFFDC9FDCFFD61F814F8",
INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC67A0217E0DFBF04E08EF9265AA0",
INIT_02 => x"051774FE8E260517F62A5A19048B0327856D0DC64FD0DF8E7505175FFE8EBE05",
INIT_03 => x"17408B981F7305175E86092C2081891FF1270D817F846505174605177BFE8E5C",
INIT_04 => x"201E05177DFE8EF5264FFE8C02300F2780E113FE8E20C0022F60C16705176C05",
INIT_05 => x"83FE8E310417290417210417190417110417FF041783FE8E3B341FBC2094ADC0",
INIT_06 => x"ED0317394AAF02295704171705172704174804164104173A0417330417EA0417",
INIT_07 => x"17ED0417E703173946AF02293B0417FB04170004173948AF0229490417090517",
INIT_08 => x"0229220417D10417F503173943A70229300417DF0417CE03173944AF02292D04",
INIT_09 => x"C4A7808A0429060417B50417E303173941A70229140417C30417DD03173942A7",
INIT_0A => x"03178E0417260417A4A6960417260417211F5F041783FE8E121F2D29EB031739",
INIT_0B => x"173F866F04170827A4A1A4A7390F260D8117275E81DD271881E12708811128DF",
INIT_0C => x"24E1AC203406298B031705201F30C0DF8E321F350317BE203F31C22021316C04",
INIT_0D => x"8E103439623203272704170527E4AC011FF0C4201F0634F0C41000C3101F3901",
INIT_0E => x"80A610C6E1AE100417F5265A180417B0031780A610C6AF0317E4AEE8031783FE",
INIT_0F => x"2562AC7B2930342B0317E26FE26FBF20EE265A0104172E8602237E8104252081"
)
 
port map ( clk => clk,
en => ena0,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => dout0(7 downto 0)
);
 
ROM1 : RAMB4_S8
generic map (
INIT_00 => x"A0E8E0EB023464E3201F62AE10F125E4AC10A0A7E0AB043464E3201FE8031777",
INIT_01 => x"3903175003174701171035880317A1FE8E10344C03173F3085031783FE8E3C27",
INIT_02 => x"AC101A268303173E0317A6FE8E981F6C03178FFE8E2E031764AE77031787FE8E",
INIT_03 => x"1E29B102173966328C26646C9026656C62AE100B267403178603172B86B325E4",
INIT_04 => x"173984A73F86A4AFA0A709273F8184A60F271035558DFFFF8E10341A24C0DF8C",
INIT_05 => x"8D4AAF0427268D1F304AAE431F39FB265A188D08C6E3DF8E104703163F864A03",
INIT_06 => x"A0A7A0A7A0A7FF8684A7A4A604263F8184A60A24C0DF8C21AE9AFD16E4FD1706",
INIT_07 => x"F0B714F0B7FF8624F0B7DE86393D3139F7265A0427A1ACA0A608C6E3DF8E1039",
INIT_08 => x"B68A001720F0B70986FB2B20F0B697001720F0B7D88610F07D16F0B715F0B710",
INIT_09 => x"F0BFFFFE8E00F0FD5343101F40F0B7108A528D00C08ECA261085F926018520F0",
INIT_0A => x"0A2A10F07D5F04345F528D20F0B78C8622F0B7018614F0B7FE8610F0B7FF8602",
INIT_0B => x"341F4AAF00C08E24F0F7DEC63901271C8520F0B604358A20F0265A0435F8265A",
INIT_0C => x"0F8462A65858585853A6E6E4E754545454A6E6D0DF8E104444444462A636343B",
INIT_0D => x"013000008E03C614E07F18E07D390435FD265A20C6043439363562E762EA62A7",
INIT_0E => x"B78C86298D1AE0B70186F92601C518E0F6378D18E0B70F86F6265AF92600008C",
INIT_0F => x"C08E3901272CC5F02601C518E0F680A71BE0B6052702C5092000C08E228D18E0"
)
 
port map ( clk => clk,
en => ena1,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => dout1(7 downto 0)
);
 
ROM2 : RAMB4_S8
generic map (
INIT_00 => x"3981A60117F9265381AD0117E2DF7FDD0117118639FD265A20C63B341F4AAF00",
INIT_01 => x"0434E46AE46AE4EBE0EBE0E610342129FF001726290234170117F12631813D27",
INIT_02 => x"738F01173F86B227FFC102355FEB2080A70527E46AE0EB02340C290435FD0017",
INIT_03 => x"A3E4EC7101171286E4AF0130462562AC4A293034B80017E26F8701161386E2DF",
INIT_04 => x"EBDA001762AEE70017981F03CB1A0117EBFE8E64E720C6022320008310062762",
INIT_05 => x"322F01171486C326E4AC62AFCD0017981F53F526646AD7001780A684EB63EB62",
INIT_06 => x"43A6DF0017CCFE8EA1001648AEEA0017BAFE8EAC0016311FF50017AEFE8E3965",
INIT_07 => x"AEBE0017B4FE8E80001646AEC90017C0FE8E8B001644AED40017C6FE8E9E0016",
INIT_08 => x"8EC4A6A00017DCFE8E6A2042A6AA0017D7FE8E742041A6B40017D2FE8E76204A",
INIT_09 => x"39103561A710343D29098D011F43290F8DBF00172D86121F4E29098D7320E3FE",
INIT_0A => x"393080032239811D2530816F8D39E0AB04342829078D891F484848483229118D",
INIT_0B => x"35028D0235103439021A39578003226681072561813937800322468112254181",
INIT_0C => x"25E46880A608C602345720078B022F3981308B0F840235048D44444444023402",
INIT_0D => x"8180A6318D391035058D75FE8E10340C20028D390235F1265A458D498D2D8602",
INIT_0E => x"3439103501A6FA27018584A6E0DFBE10341F207F84048D0627E2DF7D39F82604",
INIT_0F => x"39103501A70235FA27028584A6E0DFBE12342086008D3902350185E0DF9FA602"
)
port map ( clk => clk,
en => ena2,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => dout2(7 downto 0)
);
 
ROM3 : RAMB4_S8
generic map (
INIT_00 => x"1007F90431F90315F90223F90139E2DFB7FF86016D84A7118684A70386E0DFBE",
INIT_01 => x"67FC5041F94D0CFC4CA5F84796F945F4FA447BFA42EBF819F9F818DDF815CFF8",
INIT_02 => x"00FFFFFFFFB3FAA7F8A7F8A7F8A7F8B3FAA7FA58B3FB558AF953A8F852F2F951",
INIT_03 => x"414857043E040000000A0D4B04202D20382E31204755422D530000000A0D0000",
INIT_04 => x"203A524F525245204E492053544942202C042053534150202C04202D20043F54",
INIT_05 => x"043D53552020043D43502020043D50532020303132333435363704203E3D2004",
INIT_06 => x"43432020043D422020043D412020043D50442020043D58492020043D59492020",
INIT_07 => x"000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF04315343565A4E4948464504203A",
INIT_08 => x"300B2784AC1084AF1084EEAA558E10A0D08E84A7F086FB264A80A70F86F0FF8E",
INIT_09 => x"2DA7D0DF8E10C0DFCE10FDFFB74444444443101F84EFD620ED26A0F08C00F089",
INIT_0A => x"1084AF10AA558E1084EE2227A0F08C00F08930FB2A4AA66F0C862FA7F0862E6F",
INIT_0B => x"2EA7D0DF8E10F186D520A5A70F88891F44444444101FD0DF8E1084EFE92684AC",
INIT_0C => x"8EF32D0C814C80E7A66F0427A6E6211F4F2CE7A66F1420F92A4A0526A6E60C86",
INIT_0D => x"9F6EC6DF9F6EC4DF9F6EC0DF9F6E62F816E2DFF753F9265A80A7A0A610C6F0FF",
INIT_0E => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
INIT_0F => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
)
port map ( clk => clk,
en => ena3,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => dout3(7 downto 0)
);
 
my_sbug : process ( cs, rw, addr, dout0, dout1, dout2, dout3 )
begin
case addr(10 downto 9) is
when "00" =>
ena0 <= cs;
ena1 <= '0';
ena2 <= '0';
ena3 <= '0';
rdata <= dout0;
when "01" =>
ena0 <= '0';
ena1 <= cs;
ena2 <= '0';
ena3 <= '0';
rdata <= dout1;
when "10" =>
ena0 <= '0';
ena1 <= '0';
ena2 <= cs;
ena3 <= '0';
rdata <= dout2;
when "11" =>
ena0 <= '0';
ena1 <= '0';
ena2 <= '0';
ena3 <= cs;
rdata <= dout3;
when others =>
null;
end case;
 
we <= cs and (not rw);
 
end process my_sbug;
 
end architecture rtl;
 
/keymap_rom512_b4.vhd
0,0 → 1,93
---------------------------------------------------------
--
-- PS2 Keycode look up table
-- converts 7 bit key code to ASCII
-- Address bit 7 = CAPS Lock
-- Address bit 8 = Shift
--
-- J.E.Kent
-- 18th Oct 2004
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.all;
 
entity key_b4 is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (8 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
);
end key_b4;
 
architecture rtl of key_b4 is
 
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
);
 
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
we : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component RAMB4_S8;
 
signal we : std_logic;
 
begin
 
ROM : RAMB4_S8
generic map (
INIT_00 => x"00327761737a0000003171000000000000600900000000000000000000000000", -- 1F - 00
INIT_01 => x"003837756a6d00000036796768626e0000357274667620000033346564786300", -- 3F - 20
INIT_02 => x"00005c005d0d000000003d5b00270000002d703b6c2f2e000039306f696b2c00", -- 5F - 40
INIT_03 => x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60
 
INIT_04 => x"00325741535a00000031510000000000007e0900000000000000000000000000", -- 9F - 80
INIT_05 => x"003837554a4d00000036594748424e0000355254465620000033344544584300", -- BF - A0
INIT_06 => x"00005c005d0d000000003d5b00270000002d503b4c2f2e000039304f494b2c00", -- DF - C0
INIT_07 => x"0000000000000000001b000000007f0000000000000000000008000000000000", -- FF - E0
 
INIT_08 => x"00405741535a00000021510000000000007e0900000000000000000000000000", -- 1F - 00
INIT_09 => x"002a26554a4d0000005e594748424e0000255254465620000023244544584300", -- 3F - 20
INIT_0A => x"00007c007d0d000000002b7b00220000005f503a4c3f3e000028294f494b3c00", -- 5F - 40
INIT_0B => x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60
 
INIT_0C => x"00407761737a0000002171000000000000600900000000000000000000000000", -- 9F - 80
INIT_0D => x"002a26756a6d0000005e796768626e0000257274667620000023246564786300", -- BF - A0
INIT_0E => x"00007c007d0d000000002b7b00220000005f703a6c3f3e000028296f696b3c00", -- DF - C0
INIT_0F => x"0000000000000000001b000000007f0000000000000000000008000000000000" -- FF - E0
)
 
port map ( clk => clk,
en => cs,
we => we,
rst => rst,
addr => addr,
di => wdata,
do => rdata
);
 
 
my_ram_512 : process ( rw )
begin
we <= not rw;
end process;
 
end architecture rtl;
 
/ram1k_b4.vhd
0,0 → 1,101
--
-- Ram1k_b4.vhd
--
-- 1K Byte RAM made out of 2 x 512 byte Block RAMs.
-- John Kent
-- 3 February 2007
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
 
entity ram1k is
Port (
WB_CLK_I : in std_logic;
WB_RST_I : in std_logic;
WB_ADR_I : in std_logic_vector (9 downto 0);
WB_DAT_O : out std_logic_vector (7 downto 0)
WB_DAT_I : in std_logic_vector (7 downto 0);
WB_WE_I : in std_logic;
WB_STB_I : in std_logic;
);
end ram1k;
 
architecture rtl of ram_2k is
 
signal rdata0 : std_logic_vector (7 downto 0);
signal rdata1 : std_logic_vector (7 downto 0);
signal ena0 : std_logic;
signal ena1 : std_logic;
 
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"
);
 
port (
clk, we, en, rst : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component;
 
begin
 
MY_RAM0 : RAMB4_S8
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000" )
 
port map (
clk => WB_CLK_I,
en => ena0,
we => WB_WE_I,
rst => WB_RST_I,
addr(8 downto 0) => WB_ADR_I(8 downto 0),
di(7 downto 0) => WB_DAT_I(7 downto 0),
do(7 downto 0) => rdata0(7 downto 0)
);
 
MY_RAM1 : RAMB4_S8
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0A => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0B => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0C => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0D => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0E => x"0000000000000000000000000000000000000000000000000000000000000000",INIT_0F => x"0000000000000000000000000000000000000000000000000000000000000000" )
 
port map ( clk => clk,
clk => WB_CLK_I,
en => ena1,
we => WB_WE_I,
rst => WB_RST_I,
addr(8 downto 0) => WB_ADR_I(8 downto 0),
di(7 downto 0) => WB_DAT_I(7 downto 0),
do(7 downto 0) => rdata1(7 downto 0)
);
 
 
my_ram_1k : process (WB_STB_I, WB_ADR_I, rdata0, rdata1 )
begin
case WB_ADR_I(9) is
when "0" =>
ena0 <= WB_STB_I;
ena1 <= '0';
WB_DAT_O <= rdata0;
when "1" =>
ena0 <= '0';
ena1 <= WB_STB_I;
WB_DAT_O <= rdata1;
when others =>
null;
end case;
 
end process;
 
end;
 
/ram2k_b4.vhd
0,0 → 1,214
--
-- Ram2k.vhd
--
-- 2K Byte RAM made out of 4 x 512 byte Block RAMs.
-- John Kent
-- 11 February 2004
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.all;
 
entity ram_2k is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
wdata : in std_logic_vector (7 downto 0);
rdata : out std_logic_vector (7 downto 0)
);
end ram_2k;
 
architecture rtl of ram_2k is
 
signal we : std_logic;
signal reset : std_logic;
signal rdata0 : std_logic_vector (7 downto 0);
signal rdata1 : std_logic_vector (7 downto 0);
signal rdata2 : std_logic_vector (7 downto 0);
signal rdata3 : std_logic_vector (7 downto 0);
signal ena0 : std_logic;
signal ena1 : std_logic;
signal ena2 : std_logic;
signal ena3 : std_logic;
 
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0) :=
x"0000000000000000000000000000000000000000000000000000000000000000"
);
 
port (
clk, we, en, rst : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component;
 
begin
 
MY_RAM0 : RAMB4_S8
generic map (
INIT_00 => x"000000FF0000001010101010101010003E1C7F7F3E1C08000000FF0000000000",
INIT_01 => x"202020202020200000FF0000000000000000000000FF000000000000FF000000",
INIT_02 => x"0000E0100808080000000304080808080810E000000000040404040404040420",
INIT_03 => x"808080808080FF80402010080402010102040810204080FF8080808080808000",
INIT_04 => x"081C3E7F7F7F3600FF000000000000003C7E7E7E7E3C0001010101010101FF80",
INIT_05 => x"3C424242423C0081422418182442810808040300000000404040404040404000",
INIT_06 => x"0808FF0808080800081C3E7F3E1C0802020202020202020008082A772A1C0800",
INIT_07 => x"03070F1F3F7FFF001414543E010000080808080808080850A050A050A050A008",
INIT_08 => x"24247E247E242400000000002424240008000008080808000000000000000000",
INIT_09 => x"00000000100804003A444A30484830004626100864620000083C0A1C281E0800",
INIT_0A => x"0008083E08080000082A1C3E1C2A080020100808081020000408101010080400",
INIT_0B => x"402010080402000018180000000000000000007E000000100808000000000000",
INIT_0C => x"3C42021C02423C007E40300C02423C003E080808281808003C42625A46423C00",
INIT_0D => x"1010100804427E003C42427C40201C003844020478407E0004047E24140C0400",
INIT_0E => x"080800000800000000080000080000003804023E42423C003C42423C42423C00",
INIT_0F => x"1000100C02423C0070180C060C18700000007E007E0000000E18306030180E10"
)
 
port map ( clk => clk,
en => ena0,
we => we,
rst => reset,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata(7 downto 0),
do(7 downto 0) => rdata0(7 downto 0)
);
 
MY_RAM1 : RAMB4_S8
generic map (
 
INIT_00 => x"001C22404040221C007C22223C22227C004242427E422418001E204C564A221C",
INIT_01 => x"001C22424E40221C004040407840407E007E40407840407E0078242222222478",
INIT_02 => x"0042444870484442003844040404040E001C08080808081C004242427E424242",
INIT_03 => x"0018244242422418004242464A526242004242425A5A6642007E404040404040",
INIT_04 => x"003C42023C40423C004244487C42427C001A244A42422418004040407C42427C",
INIT_05 => x"0042665A5A4242420018182424424242003C424242424242000808080808083E",
INIT_06 => x"003C20202020203C007E40201804027E000808081C2222220042422418244242",
INIT_07 => x"0010207F20100000080808082A1C0800003C04040404043C006E70103C10100C",
INIT_08 => x"003C4240423C0000005C6242625C4040003A443C04380000001E204C564A221C",
INIT_09 => x"3C023A46463A0000001010107C10120C003C407E423C0000003A4642463A0202",
INIT_0A => x"004468504844404038440404040C0004001C08080818000800424242625C4040",
INIT_0B => x"003C4242423C000000424242625C00000049494949760000001C080808080818",
INIT_0C => x"007C023C403E000000404040625C000002023A46463A000040405C62625C0000",
INIT_0D => x"00364949494100000018244242420000003A464242420000000C1210107C1010",
INIT_0E => x"003C20202020203C007E2018047E00003C023A46424200000042241824420000",
INIT_0F => x"0010207F20100000080808082A1C0800003C04040404043C006E70103C10100C"
)
 
port map ( clk => clk,
en => ena1,
we => we,
rst => reset,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata(7 downto 0),
do(7 downto 0) => rdata1(7 downto 0)
);
 
MY_RAM2 : RAMB4_S8
generic map (
INIT_00 => x"000000FF0000001010101010101010003E1C7F7F3E1C08000000FF0000000000",
INIT_01 => x"202020202020200000FF0000000000000000000000FF000000000000FF000000",
INIT_02 => x"0000E0100808080000000304080808080810E000000000040404040404040420",
INIT_03 => x"808080808080FF80402010080402010102040810204080FF8080808080808000",
INIT_04 => x"081C3E7F7F7F3600FF000000000000003C7E7E7E7E3C0001010101010101FF80",
INIT_05 => x"3C424242423C0081422418182442810808040300000000404040404040404000",
INIT_06 => x"0808FF0808080800081C3E7F3E1C0802020202020202020008082A772A1C0800",
INIT_07 => x"03070F1F3F7FFF001414543E010000080808080808080850A050A050A050A008",
INIT_08 => x"24247E247E242400000000002424240008000008080808000000000000000000",
INIT_09 => x"00000000100804003A444A30484830004626100864620000083C0A1C281E0800",
INIT_0A => x"0008083E08080000082A1C3E1C2A080020100808081020000408101010080400",
INIT_0B => x"402010080402000018180000000000000000007E000000100808000000000000",
INIT_0C => x"3C42021C02423C007E40300C02423C003E080808281808003C42625A46423C00",
INIT_0D => x"1010100804427E003C42427C40201C003844020478407E0004047E24140C0400",
INIT_0E => x"080800000800000000080000080000003804023E42423C003C42423C42423C00",
INIT_0F => x"1000100C02423C0070180C060C18700000007E007E0000000E18306030180E10"
)
 
port map ( clk => clk,
en => ena2,
we => we,
rst => reset,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata(7 downto 0),
do(7 downto 0) => rdata2(7 downto 0)
);
 
MY_RAM3 : RAMB4_S8
generic map (
 
INIT_00 => x"001C22404040221C007C22223C22227C004242427E422418001E204C564A221C",
INIT_01 => x"001C22424E40221C004040407840407E007E40407840407E0078242222222478",
INIT_02 => x"0042444870484442003844040404040E001C08080808081C004242427E424242",
INIT_03 => x"0018244242422418004242464A526242004242425A5A6642007E404040404040",
INIT_04 => x"003C42023C40423C004244487C42427C001A244A42422418004040407C42427C",
INIT_05 => x"0042665A5A4242420018182424424242003C424242424242000808080808083E",
INIT_06 => x"003C20202020203C007E40201804027E000808081C2222220042422418244242",
INIT_07 => x"0010207F20100000080808082A1C0800003C04040404043C006E70103C10100C",
INIT_08 => x"003C4240423C0000005C6242625C4040003A443C04380000001E204C564A221C",
INIT_09 => x"3C023A46463A0000001010107C10120C003C407E423C0000003A4642463A0202",
INIT_0A => x"004468504844404038440404040C0004001C08080818000800424242625C4040",
INIT_0B => x"003C4242423C000000424242625C00000049494949760000001C080808080818",
INIT_0C => x"007C023C403E000000404040625C000002023A46463A000040405C62625C0000",
INIT_0D => x"00364949494100000018244242420000003A464242420000000C1210107C1010",
INIT_0E => x"003C20202020203C007E2018047E00003C023A46424200000042241824420000",
INIT_0F => x"0010207F20100000080808082A1C0800003C04040404043C006E70103C10100C"
)
 
port map ( clk => clk,
en => ena3,
we => we,
rst => reset,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata(7 downto 0),
do(7 downto 0) => rdata3(7 downto 0)
);
 
my_ram_2k : process ( clk, rst, cs, rw, addr, rdata0, rdata1, rdata2, rdata3 )
begin
case addr(10 downto 9) is
when "00" =>
ena0 <= cs;
ena1 <= '0';
ena2 <= '0';
ena3 <= '0';
rdata <= rdata0;
when "01" =>
ena0 <= '0';
ena1 <= cs;
ena2 <= '0';
ena3 <= '0';
rdata <= rdata1;
when "10" =>
ena0 <= '0';
ena1 <= '0';
ena2 <= cs;
ena3 <= '0';
rdata <= rdata2;
when "11" =>
ena0 <= '0';
ena1 <= '0';
ena2 <= '0';
ena3 <= cs;
rdata <= rdata3;
when others =>
null;
end case;
 
we <= cs and (not rw);
reset <= rst;
 
end process;
 
end;
 
/keymap_rom_slice.vhd
0,0 → 1,65
---------------------------------------------------------
-- keymap_rom_slice.vhd
--
-- PS2 Keycode look up table
-- converts 7 bit key code to ASCII
-- Address bit 7 = CAPS Lock
-- Address bit 8 = Shift
--
-- J.E.Kent
-- 18th Oct 2004
-- 28th Jan 2007 - made entity compatible with block RAM versions.
-- 3rd Feb 2007 - initialized with Bit_vector
--
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity keymap_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (8 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
);
end keymap_rom;
 
architecture rtl of keymap_rom is
constant width : integer := 8;
constant memsize : integer := 512;
signal rvect : std_logic_vector(255 downto 0);
 
type rom_array is array(0 to 15) of std_logic_vector (255 downto 0);
 
constant rom_data : rom_array :=
(
x"00327761737a0000003171000000000000600900000000000000000000000000", -- 1F - 00
x"003837756a6d00000036796768626e0000357274667620000033346564786300", -- 3F - 20
x"00005c005d0d000000003d5b00270000002d703b6c2f2e000039306f696b2c00", -- 5F - 40
x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60
 
x"00325741535a00000031510000000000007e0900000000000000000000000000", -- 9F - 80
x"003837554a4d00000036594748424e0000355254465620000033344544584300", -- BF - A0
x"00005c005d0d000000003d5b00270000002d503b4c2f2e000039304f494b2c00", -- DF - C0
x"0000000000000000001b000000007f0000000000000000000008000000000000", -- FF - E0
 
x"00405741535a00000021510000000000007e0900000000000000000000000000", -- 1F - 00
x"002a26554a4d0000005e594748424e0000255254465620000023244544584300", -- 3F - 20
x"00007c007d0d000000002b7b00220000005f503a4c3f3e000028294f494b3c00", -- 5F - 40
x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60
 
x"00407761737a0000002171000000000000600900000000000000000000000000", -- 9F - 80
x"002a26756a6d0000005e796768626e0000257274667620000023246564786300", -- BF - A0
x"00007c007d0d000000002b7b00220000005f703a6c3f3e000028296f696b3c00", -- DF - C0
x"0000000000000000001b000000007f0000000000000000000008000000000000" -- FF - E0
);
begin
 
rvect <= rom_data(conv_integer(addr(8 downto 5)));
rdata <= rvect( conv_integer(addr(4 downto 0))*8+7 downto conv_integer(addr(4 downto 0))*8);
end architecture rtl;
 
/noice09_rom2k_b4.vhd
0,0 → 1,220
--*******************************************************
--
-- NOICE09 Monitor ROM for the 6809
-- noice09_rom2k_b4.vhd
-- John Kent
-- 4th July 2006
--
--*******************************************************
--
-- Using 4 x RAMB4_S8 found in the XC2S300e
-- NOICE09 assumes an ACIA at $E000
-- and Monitor RAM from $F000 to $F7FF
-- The monitor starts at $FC00
-- The first 1K of ROM is empty and may
-- be used for other purposes
--
-- The Noice monitor has the same entity name
-- as SBUG and KBUG9S so it can be easily exchanged.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.all;
 
entity mon_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
wdata : in std_logic_vector (7 downto 0);
rdata : out std_logic_vector (7 downto 0)
);
end mon_rom;
 
architecture rtl of mon_rom is
 
signal rdata0 : std_logic_vector (7 downto 0);
signal rdata1 : std_logic_vector (7 downto 0);
signal rdata2 : std_logic_vector (7 downto 0);
signal rdata3 : std_logic_vector (7 downto 0);
 
signal ena0 : std_logic;
signal ena1 : std_logic;
signal ena2 : std_logic;
signal ena3 : std_logic;
 
signal we : std_logic;
 
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
);
 
port (
clk, we, en, rst : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component RAMB4_S8;
 
begin
 
ROM0 : RAMB4_S8
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
)
 
port map ( clk => clk,
en => ena0,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => rdata0(7 downto 0)
);
 
ROM1 : RAMB4_S8
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000"
)
 
port map ( clk => clk,
en => ena1,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => rdata1(7 downto 0)
);
 
ROM2 : RAMB4_S8
generic map (
INIT_00 => x"ACFC8E1001E07D00E0B7118600E0B70386FA2612121F3000008E20F6CE10321A",
INIT_01 => x"2AF6B72BF6B72EF6FD0000CC22F6F723F6B710F6CCFA265A81AF1008C600F08E",
INIT_02 => x"34D1FD7E30F6B7FA862DF6B7828621F6B720F6B724F6FD26F6FD28F6FD2CF6B7",
INIT_03 => x"FCBD02349035011A903501E0B64FF227018400E0B60D271F308EFCBD00008E10",
INIT_04 => x"6D20393038363F0100000000008005394C4F3901E0B70235F627028400E0B68E",
INIT_05 => x"02352AF6B702352BF6B702352DF6B7023520F6B700302E315620726F74696E6F",
INIT_06 => x"20F6B6103524F6F725F6B7063526F6F727F6B7063528F6F729F6B706352CF6B7",
INIT_07 => x"25F781F4255FFCBD30F68E20F6CE1037FE7E2EF6F72FF6B7101F1F3002260181",
INIT_08 => x"FCBDF6265A80A7D8255FFCBD891F0C27008180A7E5228081E9255FFCBD80A7F0",
INIT_09 => x"812527FD812627FE814227FF8180E680A630F68EC526E0ABB4FEBD0234CE255F",
INIT_0a => x"FE7E018630F6B7F0861F27F7812027F8812127F9812227FA812327FB812427FC",
INIT_0b => x"31F68E1091FC8E84FE7E79FE7E4BFE7EF8FD7EE6FD7ED1FD7EA5FD7E8EFD7E92",
INIT_0c => x"5A80A7A0A6072731F6F703E6021F01E602A69CFE7EF9265AA0A780A6A0E71BC6",
INIT_0d => x"A63435F9265AA0A780A63434142703C031F6F6021F80A680E680A69CFE7EF926",
INIT_0e => x"80A7A0A680E731F68E10C620F68E1092FE7E018602200086F7265A0726A0A180",
INIT_0f => x"041F22F6F623F6B692FE7E4FF9265AA0A780A620F68E100B275D9CFE7EF9265A"
)
port map ( clk => clk,
en => ena2,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => rdata2(7 downto 0)
);
 
ROM3 : RAMB4_S8
generic map (
INIT_00 => x"063428F6F629F6B6063426F6F627F6B6063424F6F625F6B606342EF6F62FF6B6",
INIT_01 => x"1022F6F723F6B7401F3B0234508A2DF6B602342BF6B602342AF6B602342CF6B6",
INIT_02 => x"A4A6021F01E602A6043420275454C0A7008631F6CED1FD7E21F6B7008620F6CE",
INIT_03 => x"A6021F84E601A69CFE7EE02631F6F1043031F67CC0A70C260435A4E1A4E703E6",
INIT_04 => x"40B4FEBD002031F6B7018632F6B792FE7E4FA4A702A6021F84E601A692FE7EA4",
INIT_05 => x"5A80AB008602CB01E630F68EF1FC7EF8265A7CFCBD80A603CB01E630F68E84A7",
INIT_06 => x"26508502352BF6B7846E04F0BE0586846E02F0BE0686846E00F0BE078639FB26",
INIT_07 => x"6E0CF0BE0286846E08F0BE0386846E06F0BE04860234508A04342BF6F67C3409",
INIT_08 => x"0000000000000000000000000000000000000000000000000000ACFC7E018684",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0f => x"00FCFAFE01FFF3FED8FED1FECAFEC3FE00000000000000000000000000000000"
)
port map ( clk => clk,
en => ena3,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => rdata3(7 downto 0)
);
 
my_noice09_b4 : process ( cs, rw, addr, rdata0, rdata1, rdata2, rdata3 )
begin
case addr(10 downto 9) is
when "00" =>
ena0 <= cs;
ena1 <= '0';
ena2 <= '0';
ena3 <= '0';
rdata <= rdata0;
when "01" =>
ena0 <= '0';
ena1 <= cs;
ena2 <= '0';
ena3 <= '0';
rdata <= rdata1;
when "10" =>
ena0 <= '0';
ena1 <= '0';
ena2 <= cs;
ena3 <= '0';
rdata <= rdata2;
when "11" =>
ena0 <= '0';
ena1 <= '0';
ena2 <= '0';
ena3 <= cs;
rdata <= rdata3;
when others =>
null;
end case;
 
we <= not rw;
 
end process;
 
end architecture rtl;
 
/keymap_rom_b4.vhd
0,0 → 1,73
---------------------------------------------------------
--
-- PS2 Keycode look up table
-- converts 7 bit key code to ASCII
-- Address bit 7 = CAPS Lock
-- Address bit 8 = Shift
--
-- J.E.Kent
-- 18th Oct 2004
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.vcomponents.all;
 
entity keymap_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (8 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
);
end keymap_rom;
 
architecture rtl of keymap_rom is
 
 
signal we : std_logic;
 
begin
 
ROM : RAMB4_S8
generic map (
INIT_00 => x"00327761737a0000003171000000000000600900000000000000000000000000", -- 1F - 00
INIT_01 => x"003837756a6d00000036796768626e0000357274667620000033346564786300", -- 3F - 20
INIT_02 => x"00005c005d0d000000003d5b00270000002d703b6c2f2e000039306f696b2c00", -- 5F - 40
INIT_03 => x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60
INIT_04 => x"00325741535a00000031510000000000007e0900000000000000000000000000", -- 9F - 80
INIT_05 => x"003837554a4d00000036594748424e0000355254465620000033344544584300", -- BF - A0
INIT_06 => x"00005c005d0d000000003d5b00270000002d503b4c2f2e000039304f494b2c00", -- DF - C0
INIT_07 => x"0000000000000000001b000000007f0000000000000000000008000000000000", -- FF - E0
INIT_08 => x"00405741535a00000021510000000000007e0900000000000000000000000000", -- 1F - 00
INIT_09 => x"002a26554a4d0000005e594748424e0000255254465620000023244544584300", -- 3F - 20
INIT_0A => x"00007c007d0d000000002b7b00220000005f503a4c3f3e000028294f494b3c00", -- 5F - 40
INIT_0B => x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60
INIT_0C => x"00407761737a0000002171000000000000600900000000000000000000000000", -- 9F - 80
INIT_0D => x"002a26756a6d0000005e796768626e0000257274667620000023246564786300", -- BF - A0
INIT_0E => x"00007c007d0d000000002b7b00220000005f703a6c3f3e000028296f696b3c00", -- DF - C0
INIT_0F => x"0000000000000000001b000000007f0000000000000000000008000000000000" -- FF - E0
)
 
port map (
clk => clk,
en => cs,
we => we,
rst => rst,
addr => addr,
di => wdata,
do => rdata
);
 
 
my_keymap_rom_b4 : process ( rw )
begin
we <= not rw;
end process;
 
end architecture rtl;
 
/sbug_rom2k_slice.vhd
0,0 → 1,2143
--=========================================================================
 
--
 
-- S Y N T H E Z I A B L E SBUG - Monitor ROM for System09.
 
--
 
--=========================================================================
 
--
-- www.OpenCores.Org - September 2003
 
-- This core adheres to the GNU public license
 
--
 
-- FILE NAME: sbug_rom2k_slice.vhd
 
-- ENTITY NAME: mon_rom
 
-- ARCHITECTURE NAME: rtl
 
-- VERSION: 1.0
 
-- AUTHOR: John E. Kent
 
-- DATE: 15 December 2002
 
-- DEPENDENCIES: ieee.Std_Logic_1164
 
-- ieee.std_logic_unsigned
 
-- ieee.std_logic_arith
 
-- DESCRIPTION: 2048 byte x 8 bit ROM Monitor program
 
-- for the System09 using slices
 
-- Sits at $F800
 
-- ACIA at $E004
 
-- DAT at $FFF0
 
--
 
--
 
library ieee;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_arith.all;
 
use ieee.std_logic_unsigned.all;
 
 
 
entity mon_rom is
 
port (
 
addr : in std_logic_vector(10 downto 0);
 
data : out std_logic_vector(7 downto 0)
);
 
end entity;
 
 
 
architecture rtl of mon_rom is
 
 
constant width : integer := 8;
 
constant memsize : integer := 2048;
 
 
type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
 
 
 
constant rom_data : rom_array :=
(
 
"11111000",
"00010100",
"11111000",
"01100001",
"11111101",
"11001111",
"11111101",
"11001001",
"11111101",
"11011111",
"11111101",
"11101110",
"11111101",
"10111101",
"11111101",
"10110001",
"11111101",
"10101101",
"11111011",
"10000001",
"10001110",
"11111110",
"01001111",
"00010000",
"10001110",
"11011111",
"11000000",
"11000110",
"00010000",
"10100110",
"10000000",
"10100111",
"10100000",
"01011010",
"00100110",
"11111001",
"10001110",
"11100000",
"00000100",
"10111111",
"11011111",
"11100000",
"00010111",
"00000010",
"01111010",
"11000110",
"00001100",
"01101111",
"11100010",
"01011010",
"00100110",
"11111011",
"00110000",
"10001100",
"11011101",
"10101111",
"01101010",
"10000110",
"11010000",
"10100111",
"11100100",
"00011111",
"01000011",
"00010111",
"00000101",
"10111110",
"10001110",
"11111110",
"01011111",
"00010111",
"00000101",
"01110101",
"10001110",
"11011111",
"11010000",
"01001111",
"11000110",
"00001101",
"01101101",
"10000101",
"00100111",
"00000011",
"10001011",
"00000100",
"00011001",
"01011010",
"00101010",
"11110110",
"00010111",
"00000101",
"00100110",
"10001110",
"11111110",
"01110100",
"00010111",
"00000101",
"01011100",
"10001110",
"11111110",
"01111011",
"00010111",
"00000101",
"01000110",
"00010111",
"00000101",
"01100101",
"10000100",
"01111111",
"10000001",
"00001101",
"00100111",
"11110001",
"00011111",
"10001001",
"10000001",
"00100000",
"00101100",
"00001001",
"10000110",
"01011110",
"00010111",
"00000101",
"01110011",
"00011111",
"10011000",
"10001011",
"01000000",
"00010111",
"00000101",
"01101100",
"00010111",
"00000101",
"01100111",
"11000001",
"01100000",
"00101111",
"00000010",
"11000000",
"00100000",
"10001110",
"11111110",
"00010011",
"11100001",
"10000000",
"00100111",
"00001111",
"00110000",
"00000010",
"10001100",
"11111110",
"01001111",
"00100110",
"11110101",
"10001110",
"11111110",
"01111101",
"00010111",
"00000101",
"00011110",
"00100000",
"11000000",
"10101101",
"10010100",
"00100000",
"10111100",
"00011111",
"00110100",
"00111011",
"10001110",
"11111110",
"10000011",
"00010111",
"00000100",
"11111111",
"00010111",
"00000100",
"00010001",
"00010111",
"00000100",
"00011001",
"00010111",
"00000100",
"00100001",
"00010111",
"00000100",
"00101001",
"00010111",
"00000100",
"00110001",
"10001110",
"11111110",
"10000011",
"00010111",
"00000100",
"11101010",
"00010111",
"00000100",
"00110011",
"00010111",
"00000100",
"00111010",
"00010111",
"00000100",
"01000001",
"00010110",
"00000100",
"01001000",
"00010111",
"00000100",
"00100111",
"00010111",
"00000101",
"00010111",
"00010111",
"00000100",
"01010111",
"00101001",
"00000010",
"10101111",
"01001010",
"00111001",
"00010111",
"00000011",
"11101101",
"00010111",
"00000101",
"00001001",
"00010111",
"00000100",
"01001001",
"00101001",
"00000010",
"10101111",
"01001000",
"00111001",
"00010111",
"00000100",
"00000000",
"00010111",
"00000100",
"11111011",
"00010111",
"00000100",
"00111011",
"00101001",
"00000010",
"10101111",
"01000110",
"00111001",
"00010111",
"00000011",
"11100111",
"00010111",
"00000100",
"11101101",
"00010111",
"00000100",
"00101101",
"00101001",
"00000010",
"10101111",
"01000100",
"00111001",
"00010111",
"00000011",
"11001110",
"00010111",
"00000100",
"11011111",
"00010111",
"00000100",
"00110000",
"00101001",
"00000010",
"10100111",
"01000011",
"00111001",
"00010111",
"00000011",
"11110101",
"00010111",
"00000100",
"11010001",
"00010111",
"00000100",
"00100010",
"00101001",
"00000010",
"10100111",
"01000010",
"00111001",
"00010111",
"00000011",
"11011101",
"00010111",
"00000100",
"11000011",
"00010111",
"00000100",
"00010100",
"00101001",
"00000010",
"10100111",
"01000001",
"00111001",
"00010111",
"00000011",
"11100011",
"00010111",
"00000100",
"10110101",
"00010111",
"00000100",
"00000110",
"00101001",
"00000100",
"10001010",
"10000000",
"10100111",
"11000100",
"00111001",
"00010111",
"00000011",
"11101011",
"00101001",
"00101101",
"00011111",
"00010010",
"10001110",
"11111110",
"10000011",
"00010111",
"00000100",
"01011111",
"00011111",
"00100001",
"00010111",
"00000100",
"00100110",
"00010111",
"00000100",
"10010110",
"10100110",
"10100100",
"00010111",
"00000100",
"00100110",
"00010111",
"00000100",
"10001110",
"00010111",
"00000011",
"11011111",
"00101000",
"00010001",
"10000001",
"00001000",
"00100111",
"11100001",
"10000001",
"00011000",
"00100111",
"11011101",
"10000001",
"01011110",
"00100111",
"00010111",
"10000001",
"00001101",
"00100110",
"00001111",
"00111001",
"10100111",
"10100100",
"10100001",
"10100100",
"00100111",
"00001000",
"00010111",
"00000100",
"01101111",
"10000110",
"00111111",
"00010111",
"00000100",
"01101100",
"00110001",
"00100001",
"00100000",
"11000010",
"00110001",
"00111111",
"00100000",
"10111110",
"00010111",
"00000011",
"00110101",
"00011111",
"00110010",
"10001110",
"11011111",
"11000000",
"00110000",
"00011111",
"00100000",
"00000101",
"00010111",
"00000011",
"10001011",
"00101001",
"00000110",
"00110100",
"00100000",
"10101100",
"11100001",
"00100100",
"00000001",
"00111001",
"00011111",
"00010000",
"11000011",
"00000000",
"00010000",
"11000100",
"11110000",
"00110100",
"00000110",
"00011111",
"00100000",
"11000100",
"11110000",
"00011111",
"00000001",
"10101100",
"11100100",
"00100111",
"00000101",
"00010111",
"00000100",
"00100111",
"00100111",
"00000011",
"00110010",
"01100010",
"00111001",
"00110100",
"00010000",
"10001110",
"11111110",
"10000011",
"00010111",
"00000011",
"11101000",
"10101110",
"11100100",
"00010111",
"00000011",
"10101111",
"11000110",
"00010000",
"10100110",
"10000000",
"00010111",
"00000011",
"10110000",
"00010111",
"00000100",
"00011000",
"01011010",
"00100110",
"11110101",
"00010111",
"00000100",
"00010000",
"10101110",
"11100001",
"11000110",
"00010000",
"10100110",
"10000000",
"10000001",
"00100000",
"00100101",
"00000100",
"10000001",
"01111110",
"00100011",
"00000010",
"10000110",
"00101110",
"00010111",
"00000100",
"00000001",
"01011010",
"00100110",
"11101110",
"00100000",
"10111111",
"01101111",
"11100010",
"01101111",
"11100010",
"00010111",
"00000011",
"00101011",
"00110100",
"00110000",
"00101001",
"01111011",
"10101100",
"01100010",
"00100101",
"01110111",
"00010111",
"00000011",
"11101000",
"00011111",
"00100000",
"11100011",
"01100100",
"00110100",
"00000100",
"10101011",
"11100000",
"10100111",
"10100000",
"00010000",
"10101100",
"11100100",
"00100101",
"11110001",
"00010000",
"10101110",
"01100010",
"00011111",
"00100000",
"11100011",
"01100100",
"00110100",
"00000010",
"11101011",
"11100000",
"11101000",
"10100000",
"00100111",
"00111100",
"10001110",
"11111110",
"10000011",
"00010111",
"00000011",
"10000101",
"00110000",
"00111111",
"00010111",
"00000011",
"01001100",
"00110100",
"00010000",
"10001110",
"11111110",
"10100001",
"00010111",
"00000011",
"10001000",
"00110101",
"00010000",
"00010111",
"00000001",
"01000111",
"00010111",
"00000011",
"01010000",
"00010111",
"00000011",
"00111001",
"10001110",
"11111110",
"10000111",
"00010111",
"00000011",
"01110111",
"10101110",
"01100100",
"00010111",
"00000011",
"00101110",
"10001110",
"11111110",
"10001111",
"00010111",
"00000011",
"01101100",
"00011111",
"10011000",
"10001110",
"11111110",
"10100110",
"00010111",
"00000011",
"00111110",
"00010111",
"00000011",
"10000011",
"00100110",
"00011010",
"00010000",
"10101100",
"11100100",
"00100101",
"10110011",
"10000110",
"00101011",
"00010111",
"00000011",
"10000110",
"00010111",
"00000011",
"01110100",
"00100110",
"00001011",
"00010000",
"10101110",
"01100010",
"01101100",
"01100101",
"00100110",
"10010000",
"01101100",
"01100100",
"00100110",
"10001100",
"00110010",
"01100110",
"00111001",
"00010111",
"00000010",
"10110001",
"00101001",
"00011110",
"10001100",
"11011111",
"11000000",
"00100100",
"00011010",
"00110100",
"00010000",
"10001110",
"11111111",
"11111111",
"10001101",
"01010101",
"00110101",
"00010000",
"00100111",
"00001111",
"10100110",
"10000100",
"10000001",
"00111111",
"00100111",
"00001001",
"10100111",
"10100000",
"10101111",
"10100100",
"10000110",
"00111111",
"10100111",
"10000100",
"00111001",
"00010111",
"00000011",
"01001010",
"10000110",
"00111111",
"00010110",
"00000011",
"01000111",
"00010000",
"10001110",
"11011111",
"11100011",
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"01010011",
"11110111",
"11011111",
"11100010",
"00010110",
"11111000",
"01100010",
"01101110",
"10011111",
"11011111",
"11000000",
"01101110",
"10011111",
"11011111",
"11000100",
"01101110",
"10011111",
"11011111",
"11000110",
"01101110",
"10011111",
"11011111",
"11001000",
"01101110",
"10011111",
"11011111",
"11001010",
"00011111",
"01000011",
"10101110",
"01001010",
"11100110",
"10000000",
"10101111",
"01001010",
"01001111",
"01011000",
"01001001",
"10111110",
"11011111",
"11001100",
"10001100",
"11111111",
"11111111",
"00100111",
"00001111",
"00110000",
"10001011",
"10111100",
"11011111",
"11001110",
"00100010",
"00001000",
"00110100",
"00010000",
"11101100",
"11000100",
"10101110",
"01000100",
"01101110",
"11110001",
"00110111",
"00011111",
"11101110",
"01000010",
"01101110",
"10011111",
"11011111",
"11000010",
"11111111",
"10110010",
"11111111",
"11000110",
"11111111",
"10110110",
"11111111",
"10111010",
"11111111",
"10111110",
"11111111",
"11000010",
"11111111",
"10110010",
"11111111",
"00000000"
);
begin
 
data <= rom_data(conv_integer(addr));
 
 
end architecture;
 
/kbugs_rom2k_b4.vhd
0,0 → 1,212
--
-- Kbugs_rom2k_b4.vhd
--
-- KBUG9S Monitor ROM for the 6809
-- Using 4 x RAMB4_S8 in the XC2S300e
--
-- John Kent
-- 21 November 2004
-- Has the same entity name as SBUG so
-- it can be easily exchanged.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.all;
 
entity mon_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
wdata : in std_logic_vector (7 downto 0);
rdata : out std_logic_vector (7 downto 0)
);
end mon_rom;
 
architecture rtl of mon_rom is
 
signal rdata0 : std_logic_vector (7 downto 0);
signal rdata1 : std_logic_vector (7 downto 0);
signal rdata2 : std_logic_vector (7 downto 0);
signal rdata3 : std_logic_vector (7 downto 0);
 
signal ena0 : std_logic;
signal ena1 : std_logic;
signal ena2 : std_logic;
signal ena3 : std_logic;
 
signal we : std_logic;
 
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0)
);
 
port (
clk, we, en, rst : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component RAMB4_S8;
 
begin
 
ROM0 : RAMB4_S8
generic map (
INIT_00 => x"FBFC1BFD18FA18FA18FA18FA18FA4FFC53FC5EFCABFC65FCA9FC80FC7CF838F8",
INIT_01 => x"C6C0F08E10B9FE8EC0F0CE100CFD04FDFBFCFAFCEBFCDCFCD2FCBFFC3AFD04FD",
INIT_02 => x"A7D0866AAFDD8C30FB265AE26F0CC68E0117D0F0BF00E08EF9265AA0A780A610",
INIT_03 => x"17E5FE8EE20317C9FE8EA504178704174F0417D8F0B70A86D7F0B70386431FE4",
INIT_04 => x"A302170E0417408B981F1504175E86092C2081891FF1270D817F84FB0317CD03",
INIT_05 => x"1F2D29450217C22094ADC620AA0317E7FE8EF526B9FE8C02300F2780E17AFE8E",
INIT_06 => x"E127088111283802176C0217650317A4A6740217650317211F880317EDFE8E12",
INIT_07 => x"31C2202131B003173F864D02170827A4A1A4A7390F260D8117275E81DD271881",
INIT_08 => x"1000C3101F390124E1AC20340629E6011705201F30C0F08E321FC00217BE203F",
INIT_09 => x"E4AE110317EDFE8E103439623203273403170527E4AC011FF0C4201F0634F0C4",
INIT_0a => x"0425208180A610C6E1AEEB0117F5265AF30117EC021780A610C6FB0117EE0217",
INIT_0b => x"17072653810503175F3B341F390128FD0117BC20EE265A4203172E8602237E81",
INIT_0c => x"1F031707265381E702175F39D7F0F7E72001C88E031707265681F22002D83D03",
INIT_0d => x"8E10341A24C0F08C1E294C011739D8F0F7E72008C84F031707264B81F22002D8",
INIT_0e => x"10CC02163F866901173984A73F86A4AFA0A709273F8184A60F271035558DFFFF",
INIT_0f => x"AE7DFE16AC0117068D4AAF0427268D1F304AAE431F39FB265A188D08C6D9F08E"
)
 
port map ( clk => clk,
en => ena0,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => rdata0(7 downto 0)
);
 
ROM1 : RAMB4_S8
generic map (
INIT_00 => x"A608C6D9F08E1039A0A7A0A7A0A7FF8684A7A4A604263F8184A60A24C0F08C21",
INIT_01 => x"273981670217F92653816E0217D2F07F528D1186393D3139F7265A0427A1ACA0",
INIT_02 => x"170434E46AE46AE4EBE0EBE0E610342129B3001726290234CA0017F12631813C",
INIT_03 => x"D2F073058D3F86B327FFC102355FEB2080A70527E46AE0EB02340C290435B000",
INIT_04 => x"062762A3E4EC1102171286E4AF0130462562AC4A2930346F8DE26F2602161386",
INIT_05 => x"63EB62EB75011762AE820117981F03CB9F01172EFF8E64E720C6022320008310",
INIT_06 => x"188D3965326A8D1486C326E4AC62AF680117981F53F526646A72011780A684EB",
INIT_07 => x"2D86121F4229088D391035F726E4AC1080A7A0A60929188D5D8D3E8610341529",
INIT_08 => x"1E29078D891F484848482829118D903561A710343229088D011F38290E8D438D",
INIT_09 => x"021A393780032246810725418139308003223981122530817C011739E0AB0434",
INIT_0a => x"3941A70229B78DEA8D8300173944AF0229B38DF68D8500176301162086008D39",
INIT_0b => x"AF0229858DC88D7C8D394AAF0229908DD38D7E8D3943A70229AB8DDE8D800017",
INIT_0c => x"FF17A58D748D3942A702297DFF17B18D778D3946AF022979FF17BD8D7A8D3948",
INIT_0d => x"358D910017EDFE8E348D2D8D268D1E8D168DA10017EDFE8E39C4A7808A042971",
INIT_0e => x"A67F8D15FF8E572044AE88001709FF8E6120311F920017F1FE8E4A20438D3C8D",
INIT_0f => x"FF8E332048AE648DFDFE8E3C204AAE6D8DF7FE8E4D2043A6768D0FFF8E562041"
)
 
port map ( clk => clk,
en => ena1,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => rdata1(7 downto 0)
);
 
ROM2 : RAMB4_S8
generic map (
INIT_00 => x"80A608C6023426FF8EC4A6498D1FFF8E292042A6528D1AFF8E2A2046AE5B8D03",
INIT_01 => x"8D4444444402340235028D023510348235EF265A17FF178200172D860225E468",
INIT_02 => x"80A64D8D9035048DDFFE8E10340B20028D5C20078B022F3981308B0F84023504",
INIT_03 => x"86354F0126800017052708C54F0B26618D042702C54FD8F0F6063439F8260481",
INIT_04 => x"022066001705276200170A2708C510204C00170527478D092702C5D8F0F60434",
INIT_05 => x"BE84357D0017032701C5358D022702C5D7F0F60434D58DD727D2F07D8435E020",
INIT_06 => x"F0BE103482350185D0F09FA6023439D2F0B7FF86016D84A7118684A70386D0F0",
INIT_07 => x"10E0B6023439943501A7FA2702C584E6D0F0BE1434903501A6FA27018584A6D0",
INIT_08 => x"00CC20E08E943501A7FA2702C584E610E08E14343911E0B6FC27F58D82350185",
INIT_09 => x"7D20E08E16345986028D1B86D6F07F01E702C6D5F0FD04E703E702A7D3F0FD00",
INIT_0a => x"101B814100271008819635C5001784A70520098D042420810D20748D0427D6F0",
INIT_0b => x"0027100B812C0027100C81990027100D814500271016818E0027101A816C0027",
INIT_0c => x"F0B67400165A3C0027105DD3F0FC9900168300261019C15CD3F0FC51260A8111",
INIT_0d => x"273DC1D6F0F65800160000CC5B00162500271050814CD3F0B66800164A3327D3",
INIT_0e => x"39D5F0B70426D5F07D39D6F07F39D6F0B704263D81312754816E002710598116",
INIT_0f => x"C6D3F0B6168D0000CC1B20E12218C120C0D5F07FD5F0F6ED224F812080D6F07F"
)
port map ( clk => clk,
en => ena2,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => rdata2(7 downto 0)
);
 
ROM3 : RAMB4_S8
generic map (
INIT_00 => x"50814CD3F0FC3903E702A7D3F0FDD4F0F64F39D6F07FF726508102A74C84E720",
INIT_01 => x"A702E7D3F0F72086D3F0F604E75F012519C15C04E6E78D5AEA2619C15C4FF026",
INIT_02 => x"39D6F0F702E7D3F0F75FE4205F03E7D4F0F7082719C15CD4F0F6F42650C15C84",
INIT_03 => x"8EFB0254FB01E62073FE178FFE17EE20CAFE176FFE17F6276AFE170D2698FE17",
INIT_04 => x"F9496EF9470FF945B3F94260FE4182FB1948FB1877FB156CFB1060FB049AFB03",
INIT_05 => x"F976F976F976F9DEFA5ADFF95803F953A8FB5285FA5077F94FBAF84D2CFA4C95",
INIT_06 => x"0D0420302E31562053394755422D4B0000000A0D000000FFFFFFFFEBF976F976",
INIT_07 => x"552020043D43502020043D5053202004202D20043F54414857043E040000000A",
INIT_08 => x"20043D422020043D412020043D50442020043D58492020043D59492020043D50",
INIT_09 => x"00000000000000000000000000000004315343565A4E4948464504203A434320",
INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0d => x"9F6EC6F09F6EC4F09F6EC0F09F6E000000000000000000000000000000000000",
INIT_0e => x"0822CEF0BC8B300F27FFFF8CCCF0BE49584F4AAF80E64AAE431FCAF09F6EC8F0",
INIT_0f => x"34F834F8C2FFBEFFBAFFB6FFC6FFB2FFC2F09F6E42EE1F37F16E44AEC4EC1034"
)
port map ( clk => clk,
en => ena3,
we => we,
rst => rst,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata,
do(7 downto 0) => rdata3(7 downto 0)
);
 
my_kbug_b4 : process ( cs, rw, addr, rdata0, rdata1, rdata2, rdata3 )
begin
case addr(10 downto 9) is
when "00" =>
ena0 <= cs;
ena1 <= '0';
ena2 <= '0';
ena3 <= '0';
rdata <= rdata0;
when "01" =>
ena0 <= '0';
ena1 <= cs;
ena2 <= '0';
ena3 <= '0';
rdata <= rdata1;
when "10" =>
ena0 <= '0';
ena1 <= '0';
ena2 <= cs;
ena3 <= '0';
rdata <= rdata2;
when "11" =>
ena0 <= '0';
ena1 <= '0';
ena2 <= '0';
ena3 <= cs;
rdata <= rdata3;
when others =>
null;
end case;
 
we <= not rw;
 
end process my_kbug_b4;
 
end architecture rtl;
 
/char_rom1k_b4.vhd
0,0 → 1,118
--
-- 1KB Character Generator ROM
-- Using 2 x RAMB4_S8 Block RAMs.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
 
entity char_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (9 downto 0);
wdata : in std_logic_vector (7 downto 0);
rdata : out std_logic_vector (7 downto 0)
);
end char_rom;
 
architecture rtl of char_rom is
 
signal we : std_logic;
signal reset : std_logic;
signal rdata0 : std_logic_vector (7 downto 0);
signal rdata1 : std_logic_vector (7 downto 0);
signal ena0 : std_logic;
signal ena1 : std_logic;
 
 
begin
 
CH_ROM0 : RAMB4_S8
generic map (
INIT_00 => x"000000FF0000001010101010101010003E1C7F7F3E1C08000000FF0000000000",
INIT_01 => x"202020202020200000FF0000000000000000000000FF000000000000FF000000",
INIT_02 => x"0000E0100808080000000304080808080810E000000000040404040404040420",
INIT_03 => x"808080808080FF80402010080402010102040810204080FF8080808080808000",
INIT_04 => x"081C3E7F7F7F3600FF000000000000003C7E7E7E7E3C0001010101010101FF80",
INIT_05 => x"3C424242423C0081422418182442810808040300000000404040404040404000",
INIT_06 => x"0808FF0808080800081C3E7F3E1C0802020202020202020008082A772A1C0800",
INIT_07 => x"03070F1F3F7FFF001414543E010000080808080808080850A050A050A050A008",
INIT_08 => x"24247E247E242400000000002424240008000008080808000000000000000000",
INIT_09 => x"00000000100804003A444A30484830004626100864620000083C0A1C281E0800",
INIT_0A => x"0008083E08080000082A1C3E1C2A080020100808081020000408101010080400",
INIT_0B => x"402010080402000018180000000000000000007E000000100808000000000000",
INIT_0C => x"3C42021C02423C007E40300C02423C003E080808281808003C42625A46423C00",
INIT_0D => x"1010100804427E003C42427C40201C003844020478407E0004047E24140C0400",
INIT_0E => x"080800000800000000080000080000003804023E42423C003C42423C42423C00",
INIT_0F => x"1000100C02423C0070180C060C18700000007E007E0000000E18306030180E10"
)
 
port map (
clk => clk,
en => ena0,
we => we,
rst => reset,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata(7 downto 0),
do(7 downto 0) => rdata0(7 downto 0)
);
 
CH_ROM1 : RAMB4_S8
generic map (
 
INIT_00 => x"001C22404040221C007C22223C22227C004242427E422418001E204C564A221C",
INIT_01 => x"001C22424E40221C004040407840407E007E40407840407E0078242222222478",
INIT_02 => x"0042444870484442003844040404040E001C08080808081C004242427E424242",
INIT_03 => x"0018244242422418004242464A526242004242425A5A6642007E404040404040",
INIT_04 => x"003C42023C40423C004244487C42427C001A244A42422418004040407C42427C",
INIT_05 => x"0042665A5A4242420018182424424242003C424242424242000808080808083E",
INIT_06 => x"003C20202020203C007E40201804027E000808081C2222220042422418244242",
INIT_07 => x"0010207F20100000080808082A1C0800003C04040404043C006E70103C10100C",
INIT_08 => x"003C4240423C0000005C6242625C4040003A443C04380000001E204C564A221C",
INIT_09 => x"3C023A46463A0000001010107C10120C003C407E423C0000003A4642463A0202",
INIT_0A => x"004468504844404038440404040C0004001C08080818000800424242625C4040",
INIT_0B => x"003C4242423C000000424242625C00000049494949760000001C080808080818",
INIT_0C => x"007C023C403E000000404040625C000002023A46463A000040405C62625C0000",
INIT_0D => x"00364949494100000018244242420000003A464242420000000C1210107C1010",
INIT_0E => x"003C20202020203C007E2018047E00003C023A46424200000042241824420000",
INIT_0F => x"0010207F20100000080808082A1C0800003C04040404043C006E70103C10100C"
)
 
port map (
clk => clk,
en => ena1,
we => we,
rst => reset,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata(7 downto 0),
do(7 downto 0) => rdata1(7 downto 0)
);
 
my_chargen : process ( clk, rst, cs, rw, rdata0, rdata1 )
begin
case addr(9) is
when '0' =>
ena0 <= cs;
ena1 <= '0';
rdata <= rdata0;
when '1' =>
ena0 <= '0';
ena1 <= cs;
rdata <= rdata1;
when others =>
null;
end case;
 
we <= not rw;
reset <= rst;
 
end process;
 
end;
 
/char_rom2k_b4.vhd
0,0 → 1,213
--
-- char_rom2k_b4.vhd
--
-- 2K Byte Character Generator ROM
-- made out of 4 x 512 byte Block RAMs.
-- John Kent
-- 3 February 2007
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
 
entity char_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
wdata : in std_logic_vector (7 downto 0);
rdata : out std_logic_vector (7 downto 0)
);
end char_rom;
 
architecture rtl of char_rom is
 
signal we : std_logic;
signal reset : std_logic;
signal rdata0 : std_logic_vector (7 downto 0);
signal rdata1 : std_logic_vector (7 downto 0);
signal rdata2 : std_logic_vector (7 downto 0);
signal rdata3 : std_logic_vector (7 downto 0);
signal ena0 : std_logic;
signal ena1 : std_logic;
signal ena2 : std_logic;
signal ena3 : std_logic;
 
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0) :=
x"0000000000000000000000000000000000000000000000000000000000000000"
);
 
port (
clk, we, en, rst : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component;
 
begin
 
MY_RAM0 : RAMB4_S8
generic map (
INIT_00 => x"0000000009090F09090038043840380000000000070404040400444C54644400",
INIT_01 => x"00000000110A040A110078407040780000000000110A040A1100380438403800",
INIT_02 => x"000000000D1215110E0078407040780000000000040404041F00784070407800",
INIT_03 => x"000000000F080808080070487048700000000000090A0C0A0900487848483000",
INIT_04 => x"00000000040404041F0044447C444400000000000E010E100E00704870487000",
INIT_05 => x"00000000040404041F001028444444000000000010101E101F007C4040404000",
INIT_06 => x"0000000011111E111E003C4040403C000000000008080E080F00404070407800",
INIT_07 => x"00000000070202020700380438403800000000000E1111110E00380438403800",
INIT_08 => x"00000000070202060200704848487000000000000F080E080F00704848487000",
INIT_09 => x"000000000E0107020F00704848487000000000000F0806090700704848487000",
INIT_0a => x"00000000090A0C0A0900444C546444000000000001010F090900704848487000",
INIT_0b => x"000000000E090E090E0078407040780000000000111315191100380438403800",
INIT_0c => x"000000001111151B110078407040780000000000111315191100384040403800",
INIT_0d => x"000000000E1010100E00784070407800000000000E090E090E00380438403800",
INIT_0e => x"000000000E010E100E00384858403800000000000E010E100E00404070407800",
INIT_0f => x"000000000E010E100E00304848484800000000000E010E100E00485070487000"
)
 
port map ( clk => clk,
en => ena0,
we => we,
rst => reset,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata(7 downto 0),
do(7 downto 0) => rdata0(7 downto 0)
);
 
MY_RAM1 : RAMB4_S8
generic map (
INIT_00 => x"0000000008080000080808080808080000000000000000000000000000000000",
INIT_01 => x"000000002424247E2424247E2424240000000000000000000000001212121200",
INIT_02 => x"0000000043434020100804020161610000000000083E4909093E4848493E0800",
INIT_03 => x"00000000000000000000002010080C00000000003D4244444438444444443800",
INIT_04 => x"0000000020100804040404040810200000000000020408101010101008040200",
INIT_05 => x"0000000000000808087F0808080000000000000000004122147F142241000000",
INIT_06 => x"0000000000000000007F00000000000000402010181800000000000000000000",
INIT_07 => x"0000000040404020100804020101010000000000181800000000000000000000",
INIT_08 => x"000000003E080808080808082818080000000000081422414141414122140800",
INIT_09 => x"000000003E410101010E010101413E00000000007F4020100804020141423C00",
INIT_0a => x"000000003E410101615E404040407F000000000002020202027F22120A060200",
INIT_0b => x"00000000404020100804020101017F00000000001E214141615E404040211E00",
INIT_0c => x"000000003C420101013D434141423C00000000003E414141413E414141413E00",
INIT_0d => x"0000402010181818000000181818000000000000001818180000001818180000",
INIT_0e => x"00000000000000007F00007F0000000000000000010204081020100804020100",
INIT_0f => x"00000000080800080808060101413E0000000000402010080402040810204000"
)
 
port map ( clk => clk,
en => ena1,
we => we,
rst => reset,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata(7 downto 0),
do(7 downto 0) => rdata1(7 downto 0)
);
 
MY_RAM2 : RAMB4_S8
generic map (
INIT_00 => x"0000000041414141417F414122140800000000001C224140404E494541221C00",
INIT_01 => x"000000001E2141404040404041211E00000000007E212121213E212121217E00",
INIT_02 => x"000000007F404040407C404040407F00000000007C2221212121212121227C00",
INIT_03 => x"000000001E2141414147404040211E000000000040404040407C404040407F00",
INIT_04 => x"000000003E0808080808080808083E000000000041414141417F414141414100",
INIT_05 => x"00000000414244485060504844424100000000003C4202020202020202020700",
INIT_06 => x"00000000414141414141494955634100000000007F4040404040404040404000",
INIT_07 => x"000000003E4141414141414141413E0000000000414141434549495161414100",
INIT_08 => x"000000003D4245494141414141413E000000000040404040407E414141417E00",
INIT_09 => x"000000003E410101013E404040413E000000000041424448507E414141417E00",
INIT_0a => x"000000003E414141414141414141410000000000080808080808080808087F00",
INIT_0b => x"0000000022225555494941414141410000000000080814141422222241414100",
INIT_0c => x"0000000008080808080814224141410000000000414141221408142241414100",
INIT_0d => x"000000001E1010101010101010101E00000000007F4040201008040201017F00",
INIT_0e => x"000000003C0404040404040404043C0000000000010101020408102040404000",
INIT_0f => x"000000007F000000000000000000000000000000000000000000004122140800"
)
 
port map ( clk => clk,
en => ena2,
we => we,
rst => reset,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata(7 downto 0),
do(7 downto 0) => rdata2(7 downto 0)
);
 
MY_RAM3 : RAMB4_S8
generic map (
INIT_00 => x"000000003F41413F01013E000000000000000000000000000000000204081800",
INIT_01 => x"000000001E21404040211E0000000000000000005E61616141615E4040404000",
INIT_02 => x"000000003E40407F41413E0000000000000000003D43414141433D0101010100",
INIT_03 => x"003C4202023E424242423D0100000000000000001010101010107C1010110E00",
INIT_04 => x"000000003E0808080808180000080800000000004141414141615E4040404000",
INIT_05 => x"00000000414448704844414040404000003C4202020202020202020000020200",
INIT_06 => x"00000000414141494955220000000000000000001C0808080808080808081800",
INIT_07 => x"000000003E41414141413E0000000000000000004141414141615E0000000000",
INIT_08 => x"00010101013D434343433D000000000000404040405E616161615E0000000000",
INIT_09 => x"000000003E01013E40403E0000000000000000002020202020314E0000000000",
INIT_0a => x"000000003D4242424242420000000000000000000C12101010107C1010101000",
INIT_0b => x"0000000022554949414141000000000000000000081414222241410000000000",
INIT_0c => x"003C4202023A4642424242000000000000000000412214081422410000000000",
INIT_0d => x"00000000070808081020100808080700000000007F20100804027F0000000000",
INIT_0e => x"0000000070080808040204080808700000000000080808080800080808080800",
INIT_0f => x"0000000049224922492249224922490000000000000000000000000046493100"
)
 
port map ( clk => clk,
en => ena3,
we => we,
rst => reset,
addr(8 downto 0) => addr(8 downto 0),
di(7 downto 0) => wdata(7 downto 0),
do(7 downto 0) => rdata3(7 downto 0)
);
 
my_char_rom2k_b4 : process ( clk, rst, cs, rw, addr, rdata0, rdata1, rdata2, rdata3 )
begin
case addr(10 downto 9) is
when "00" =>
ena0 <= cs;
ena1 <= '0';
ena2 <= '0';
ena3 <= '0';
rdata <= rdata0;
when "01" =>
ena0 <= '0';
ena1 <= cs;
ena2 <= '0';
ena3 <= '0';
rdata <= rdata1;
when "10" =>
ena0 <= '0';
ena1 <= '0';
ena2 <= cs;
ena3 <= '0';
rdata <= rdata2;
when "11" =>
ena0 <= '0';
ena1 <= '0';
ena2 <= '0';
ena3 <= cs;
rdata <= rdata3;
when others =>
null;
end case;
 
we <= cs and (not rw);
reset <= rst;
 
end process;
 
end;
 

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