URL
https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
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- This comparison shows the changes necessary to convert path
/System09/trunk/rtl/Spartan2
- from Rev 66 to Rev 99
- ↔ Reverse comparison
Rev 66 → Rev 99
/keymap_rom512_b4.vhd
1,13 → 1,59
--------------------------------------------------------- |
--===========================================================================-- |
-- -- |
-- Synthesizable PS/2 Keyboard Key map ROM For Spartan 2 -- |
-- -- |
--===========================================================================-- |
-- |
-- PS2 Keycode look up table |
-- converts 7 bit key code to ASCII |
-- Address bit 7 = CAPS Lock |
-- Address bit 8 = Shift |
-- File name : keymap_rom512_b4.vhd |
-- |
-- Entity name : keymap_rom |
-- |
-- J.E.Kent |
-- 18th Oct 2004 |
-- Purpose : PS/2 key code look up table |
-- Converts 7 bit key code to ASCII |
-- Address bit 8 = Shift |
-- Address bit 7 = CAPS Lock |
-- Address bits 6 - 0 = Key code |
-- Data bits 6 - 0 = ASCII code |
-- Designed for Spartan 2 FPGAs |
-- |
-- Dependencies : ieee.std_logic_1164 |
-- ieee.std_logic_arith |
-- ieee.std_logic_unsigned |
-- |
-- Uses : RAMB4_S8 |
-- |
-- Author : John E. Kent |
-- |
-- Email : dilbert57@opencores.org |
-- |
-- Web : http://opencores.org/project,system09 |
-- |
-- Copyright (C) 2004 - 2010 John Kent |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
--===========================================================================-- |
-- -- |
-- Revision History -- |
-- -- |
--===========================================================================-- |
-- |
-- Version Date Author Changes |
-- |
-- 0.1 2004-10-18 John Kent Initial Version |
-- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
14,19 → 60,19
library unisim; |
use unisim.all; |
|
entity key_b4 is |
entity keymap_rom is |
Port ( |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector (8 downto 0); |
rdata : out std_logic_vector (7 downto 0); |
wdata : in std_logic_vector (7 downto 0) |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector (8 downto 0); |
data_in : in std_logic_vector (7 downto 0); |
data_out : out std_logic_vector (7 downto 0) |
); |
end key_b4; |
end keymap_rom; |
|
architecture rtl of key_b4 is |
architecture rtl of keymap_rom is |
|
component RAMB4_S8 |
generic ( |
79,8 → 125,8
we => we, |
rst => rst, |
addr => addr, |
di => wdata, |
do => rdata |
di => data_in, |
do => data_out |
); |
|
|
/ram2k_b4.vhd
1,10 → 1,50
--===========================================================================-- |
-- -- |
-- 2K Byte RAM Block using 4KBit Block RAMs found in the Spartan 2 -- |
-- -- |
--===========================================================================-- |
-- |
-- File name : ram2k_b4.vhd |
-- |
-- Entity name : ram_2k |
-- |
-- Purpose : 2KB RAM block used for a character text buffer for vdu8 |
-- using 4 x 4KBit Block RAMs |
-- |
-- Dependencies : ieee.Std_Logic_1164 |
-- ieee.std_logic_arith |
-- ieee.std_logic_unsigned |
-- unisim.vcomponents |
-- |
-- Author : John E. Kent |
-- dilbert57@opencores.org |
-- |
-- |
-- Copyright (C) 2004 - 2010 John Kent |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
--===========================================================================-- |
-- Revision History: -- |
--===========================================================================-- |
-- |
-- Version Date Author Comments |
-- |
-- 0.1 2004-02-11 John Kent Initial Version |
-- 0.2 2010-08-27 John Kent Added header |
-- Changed data input & output signals |
-- |
-- Ram2k.vhd |
-- |
-- 2K Byte RAM made out of 4 x 512 byte Block RAMs. |
-- John Kent |
-- 11 February 2004 |
-- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
14,28 → 54,27
|
entity ram_2k is |
Port ( |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector (10 downto 0); |
wdata : in std_logic_vector (7 downto 0); |
rdata : out std_logic_vector (7 downto 0) |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector (10 downto 0); |
data_in : in std_logic_vector (7 downto 0); |
data_out : out std_logic_vector (7 downto 0) |
); |
end ram_2k; |
|
architecture rtl of ram_2k is |
|
signal we : std_logic; |
signal reset : std_logic; |
signal rdata0 : std_logic_vector (7 downto 0); |
signal rdata1 : std_logic_vector (7 downto 0); |
signal rdata2 : std_logic_vector (7 downto 0); |
signal rdata3 : std_logic_vector (7 downto 0); |
signal ena0 : std_logic; |
signal ena1 : std_logic; |
signal ena2 : std_logic; |
signal ena3 : std_logic; |
signal we : std_logic; |
signal data_out0 : std_logic_vector (7 downto 0); |
signal data_out1 : std_logic_vector (7 downto 0); |
signal data_out2 : std_logic_vector (7 downto 0); |
signal data_out3 : std_logic_vector (7 downto 0); |
signal ena0 : std_logic; |
signal ena1 : std_logic; |
signal ena2 : std_logic; |
signal ena3 : std_logic; |
|
component RAMB4_S8 |
generic ( |
79,10 → 118,10
port map ( clk => clk, |
en => ena0, |
we => we, |
rst => reset, |
rst => rst, |
addr(8 downto 0) => addr(8 downto 0), |
di(7 downto 0) => wdata(7 downto 0), |
do(7 downto 0) => rdata0(7 downto 0) |
di(7 downto 0) => data_in(7 downto 0), |
do(7 downto 0) => data_out0(7 downto 0) |
); |
|
MY_RAM1 : RAMB4_S8 |
109,10 → 148,10
port map ( clk => clk, |
en => ena1, |
we => we, |
rst => reset, |
rst => rst, |
addr(8 downto 0) => addr(8 downto 0), |
di(7 downto 0) => wdata(7 downto 0), |
do(7 downto 0) => rdata1(7 downto 0) |
di(7 downto 0) => data_in(7 downto 0), |
do(7 downto 0) => data_out1(7 downto 0) |
); |
|
MY_RAM2 : RAMB4_S8 |
138,10 → 177,10
port map ( clk => clk, |
en => ena2, |
we => we, |
rst => reset, |
rst => rst, |
addr(8 downto 0) => addr(8 downto 0), |
di(7 downto 0) => wdata(7 downto 0), |
do(7 downto 0) => rdata2(7 downto 0) |
di(7 downto 0) => data_in(7 downto 0), |
do(7 downto 0) => data_out2(7 downto 0) |
); |
|
MY_RAM3 : RAMB4_S8 |
168,45 → 207,36
port map ( clk => clk, |
en => ena3, |
we => we, |
rst => reset, |
rst => rst, |
addr(8 downto 0) => addr(8 downto 0), |
di(7 downto 0) => wdata(7 downto 0), |
do(7 downto 0) => rdata3(7 downto 0) |
di(7 downto 0) => data_in(7 downto 0), |
do(7 downto 0) => data_out3(7 downto 0) |
); |
|
my_ram_2k : process ( clk, rst, cs, rw, addr, rdata0, rdata1, rdata2, rdata3 ) |
my_ram_2k : process ( cs, rw, addr, data_out0, data_out1, data_out2, data_out3 ) |
begin |
ena0 <= '0'; |
ena1 <= '0'; |
ena2 <= '0'; |
ena3 <= '0'; |
case addr(10 downto 9) is |
when "00" => |
ena0 <= cs; |
ena1 <= '0'; |
ena2 <= '0'; |
ena3 <= '0'; |
rdata <= rdata0; |
ena0 <= cs; |
data_out <= data_out0; |
when "01" => |
ena0 <= '0'; |
ena1 <= cs; |
ena2 <= '0'; |
ena3 <= '0'; |
rdata <= rdata1; |
ena1 <= cs; |
data_out <= data_out1; |
when "10" => |
ena0 <= '0'; |
ena1 <= '0'; |
ena2 <= cs; |
ena3 <= '0'; |
rdata <= rdata2; |
ena2 <= cs; |
data_out <= data_out2; |
when "11" => |
ena0 <= '0'; |
ena1 <= '0'; |
ena2 <= '0'; |
ena3 <= cs; |
rdata <= rdata3; |
ena3 <= cs; |
data_out <= data_out3; |
when others => |
null; |
end case; |
|
we <= cs and (not rw); |
reset <= rst; |
we <= not rw; |
|
end process; |
|
/keymap_rom_slice.vhd
1,38 → 1,81
--------------------------------------------------------- |
-- keymap_rom_slice.vhd |
--===========================================================================-- |
-- -- |
-- Synthesizable PS/2 Keyboard Key map ROM -- |
-- -- |
--===========================================================================-- |
-- |
-- PS2 Keycode look up table |
-- converts 7 bit key code to ASCII |
-- Address bit 7 = CAPS Lock |
-- Address bit 8 = Shift |
-- File name : keymap_rom_slice.vhd |
-- |
-- Entity name : keymap_rom |
-- |
-- J.E.Kent |
-- 18th Oct 2004 |
-- 28th Jan 2007 - made entity compatible with block RAM versions. |
-- 3rd Feb 2007 - initialized with Bit_vector |
-- Purpose : PS/2 key code look up table for PS/2 Keyboard |
-- Converts 7 bit key code to ASCII |
-- Address bit 8 = Shift |
-- Address bit 7 = CAPS Lock |
-- Address bits 6 - 0 = Key code |
-- Data bits 6 - 0 = ASCII code |
-- Using constant array look up. |
-- |
-- Dependencies : ieee.std_logic_1164 |
-- ieee.std_logic_arith |
-- ieee.std_logic_unsigned |
-- |
-- Uses : None |
-- |
-- Author : John E. Kent |
-- |
-- Email : dilbert57@opencores.org |
-- |
-- Web : http://opencores.org/project,system09 |
-- |
-- Copyright (C) 2004 - 2010 John Kent |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
--===========================================================================-- |
-- -- |
-- Revision History -- |
-- -- |
--===========================================================================-- |
-- |
-- Version Date Author Changes |
-- |
-- 0.1 2004-10-18 John Kent Initial version |
-- 0.2 2007-01-28 John Kent Made entity compatible with block RAM versions. |
-- 0.3 2007-02-01 John Kent Initialized with bit_vector |
-- 0.4 2010-06-17 John Kent Revised Header, renamed data pins, added process |
-- |
|
library IEEE; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
|
entity keymap_rom is |
Port ( |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector (8 downto 0); |
rdata : out std_logic_vector (7 downto 0); |
wdata : in std_logic_vector (7 downto 0) |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector (8 downto 0); |
data_in : in std_logic_vector (7 downto 0); |
data_out : out std_logic_vector (7 downto 0) |
); |
end keymap_rom; |
|
architecture rtl of keymap_rom is |
constant width : integer := 8; |
constant memsize : integer := 512; |
signal rvect : std_logic_vector(255 downto 0); |
|
|
type rom_array is array(0 to 15) of std_logic_vector (255 downto 0); |
|
constant rom_data : rom_array := |
57,9 → 100,16
x"00007c007d0d000000002b7b00220000005f703a6c3f3e000028296f696b3c00", -- DF - C0 |
x"0000000000000000001b000000007f0000000000000000000008000000000000" -- FF - E0 |
); |
|
signal rom_out : std_logic_vector(255 downto 0); |
|
begin |
|
process( addr, rom_out ) |
begin |
rom_out <= rom_data(conv_integer(addr(8 downto 5))); |
data_out <= rom_out( conv_integer(addr(4 downto 0))*8+7 downto conv_integer(addr(4 downto 0))*8); |
end process; |
|
rvect <= rom_data(conv_integer(addr(8 downto 5))); |
rdata <= rvect( conv_integer(addr(4 downto 0))*8+7 downto conv_integer(addr(4 downto 0))*8); |
end architecture rtl; |
|
/keymap_rom_b4.vhd
1,13 → 1,59
--------------------------------------------------------- |
--===========================================================================-- |
-- -- |
-- Synthesizable PS/2 Keyboard Key map ROM for the Spartan 2 -- |
-- -- |
--===========================================================================-- |
-- |
-- PS2 Keycode look up table |
-- converts 7 bit key code to ASCII |
-- Address bit 7 = CAPS Lock |
-- Address bit 8 = Shift |
-- File name : keymap_rom_b4.vhd |
-- |
-- Entity name : keymap_rom |
-- |
-- J.E.Kent |
-- 18th Oct 2004 |
-- Purpose : PS/2 key code look up table for PS/2 Keyboard |
-- Converts 7 bit key code to ASCII |
-- Address bit 8 = Shift |
-- Address bit 7 = CAPS Lock |
-- Address bits 6 - 0 = Key code |
-- Data bits 6 - 0 = ASCII code |
-- Designed for the Spartan 2 |
-- |
-- Dependencies : ieee.std_logic_1164 |
-- ieee.std_logic_arith |
-- ieee.std_logic_unsigned |
-- |
-- Uses : RAMB4_S8 |
-- |
-- Author : John E. Kent |
-- |
-- Email : dilbert57@opencores.org |
-- |
-- Web : http://opencores.org/project,system09 |
-- |
-- Copyright (C) 2004 - 2010 John Kent |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
--===========================================================================-- |
-- -- |
-- Revision History -- |
-- -- |
--===========================================================================-- |
-- |
-- Version Date Author Changes |
-- 0.1 2004-10-18 John Kent Initial Version |
-- 0.2 2010-06-17 John Kent Added header, Rename data signals |
-- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
16,13 → 62,13
|
entity keymap_rom is |
Port ( |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector (8 downto 0); |
rdata : out std_logic_vector (7 downto 0); |
wdata : in std_logic_vector (7 downto 0) |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector (8 downto 0); |
data_in : in std_logic_vector (7 downto 0); |
data_out : out std_logic_vector (7 downto 0) |
); |
end keymap_rom; |
|
59,8 → 105,8
we => we, |
rst => rst, |
addr => addr, |
di => wdata, |
do => rdata |
di => data_in, |
do => data_out |
); |
|
|
/char_rom2k_b4.vhd
1,11 → 1,53
--===========================================================================-- |
-- -- |
-- Character generator ROM using 4KBit Block RAMs found in the Spartan 2 -- |
-- -- |
--===========================================================================-- |
-- |
-- File name : char_rom2k_b4.vhd |
-- |
-- Entity name : char_rom |
-- |
-- Purpose : 2KB Character Generator ROM for vdu8 |
-- using 4 x 4KBit Block RAMs |
-- 8 dots across [data( 7 dwonto 0)] |
-- 16 lines down [addr( 3 downto 0)] |
-- 127 character [addr(10 downto 4)] |
-- |
-- Dependencies : ieee.Std_Logic_1164 |
-- ieee.std_logic_arith |
-- ieee.std_logic_unsigned |
-- unisim.vcomponents |
-- |
-- Author : John E. Kent |
-- dilbert57@opencores.org |
-- |
-- |
-- Copyright (C) 2003 - 2010 John Kent |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
--===========================================================================-- |
-- Revision History: -- |
--===========================================================================-- |
-- |
-- Version Date Author Comments |
-- |
-- 0.1 2007-02-03 John Kent Initial Version |
-- 0.2 2010-08-27 John Kent Added header |
-- |
-- char_rom2k_b4.vhd |
-- |
-- 2K Byte Character Generator ROM |
-- made out of 4 x 512 byte Block RAMs. |
-- John Kent |
-- 3 February 2007 |
-- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
15,28 → 57,27
|
entity char_rom is |
Port ( |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector (10 downto 0); |
wdata : in std_logic_vector (7 downto 0); |
rdata : out std_logic_vector (7 downto 0) |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
addr : in std_logic_vector (10 downto 0); |
rw : in std_logic; |
data_in : in std_logic_vector (7 downto 0); |
data_out : out std_logic_vector (7 downto 0) |
); |
end char_rom; |
|
architecture rtl of char_rom is |
|
signal we : std_logic; |
signal reset : std_logic; |
signal rdata0 : std_logic_vector (7 downto 0); |
signal rdata1 : std_logic_vector (7 downto 0); |
signal rdata2 : std_logic_vector (7 downto 0); |
signal rdata3 : std_logic_vector (7 downto 0); |
signal ena0 : std_logic; |
signal ena1 : std_logic; |
signal ena2 : std_logic; |
signal ena3 : std_logic; |
signal we : std_logic; |
signal data_out0 : std_logic_vector (7 downto 0); |
signal data_out1 : std_logic_vector (7 downto 0); |
signal data_out2 : std_logic_vector (7 downto 0); |
signal data_out3 : std_logic_vector (7 downto 0); |
signal ena0 : std_logic; |
signal ena1 : std_logic; |
signal ena2 : std_logic; |
signal ena3 : std_logic; |
|
component RAMB4_S8 |
generic ( |
80,10 → 121,10
port map ( clk => clk, |
en => ena0, |
we => we, |
rst => reset, |
rst => rst, |
addr(8 downto 0) => addr(8 downto 0), |
di(7 downto 0) => wdata(7 downto 0), |
do(7 downto 0) => rdata0(7 downto 0) |
di(7 downto 0) => data_in(7 downto 0), |
do(7 downto 0) => data_out0(7 downto 0) |
); |
|
MY_RAM1 : RAMB4_S8 |
109,10 → 150,10
port map ( clk => clk, |
en => ena1, |
we => we, |
rst => reset, |
rst => rst, |
addr(8 downto 0) => addr(8 downto 0), |
di(7 downto 0) => wdata(7 downto 0), |
do(7 downto 0) => rdata1(7 downto 0) |
di(7 downto 0) => data_in(7 downto 0), |
do(7 downto 0) => data_out1(7 downto 0) |
); |
|
MY_RAM2 : RAMB4_S8 |
138,10 → 179,10
port map ( clk => clk, |
en => ena2, |
we => we, |
rst => reset, |
rst => rst, |
addr(8 downto 0) => addr(8 downto 0), |
di(7 downto 0) => wdata(7 downto 0), |
do(7 downto 0) => rdata2(7 downto 0) |
di(7 downto 0) => data_in(7 downto 0), |
do(7 downto 0) => data_out2(7 downto 0) |
); |
|
MY_RAM3 : RAMB4_S8 |
167,45 → 208,36
port map ( clk => clk, |
en => ena3, |
we => we, |
rst => reset, |
rst => rst, |
addr(8 downto 0) => addr(8 downto 0), |
di(7 downto 0) => wdata(7 downto 0), |
do(7 downto 0) => rdata3(7 downto 0) |
di(7 downto 0) => data_in(7 downto 0), |
do(7 downto 0) => data_out3(7 downto 0) |
); |
|
my_char_rom2k_b4 : process ( clk, rst, cs, rw, addr, rdata0, rdata1, rdata2, rdata3 ) |
my_char_rom2k_b4 : process ( cs, rw, addr, data_out0, data_out1, data_out2, data_out3 ) |
begin |
ena0 <= '0'; |
ena1 <= '0'; |
ena2 <= '0'; |
ena3 <= '0'; |
case addr(10 downto 9) is |
when "00" => |
ena0 <= cs; |
ena1 <= '0'; |
ena2 <= '0'; |
ena3 <= '0'; |
rdata <= rdata0; |
ena0 <= cs; |
data_out <= data_out0; |
when "01" => |
ena0 <= '0'; |
ena1 <= cs; |
ena2 <= '0'; |
ena3 <= '0'; |
rdata <= rdata1; |
ena1 <= cs; |
data_out <= data_out1; |
when "10" => |
ena0 <= '0'; |
ena1 <= '0'; |
ena2 <= cs; |
ena3 <= '0'; |
rdata <= rdata2; |
ena2 <= cs; |
data_out <= data_out2; |
when "11" => |
ena0 <= '0'; |
ena1 <= '0'; |
ena2 <= '0'; |
ena3 <= cs; |
rdata <= rdata3; |
ena3 <= cs; |
data_out <= data_out3; |
when others => |
null; |
end case; |
|
we <= cs and (not rw); |
reset <= rst; |
we <= not rw; |
|
end process; |
|