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URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /System09/trunk/rtl/Spartan3
    from Rev 99 to Rev 118
    ↔ Reverse comparison
  •

Rev 99 → Rev 118

/ram32k_b16.vhd
1,21 → 1,60
-- $Id: ram32k_b16.vhd,v 1.2 2008/03/14 15:52:43 dilbert57 Exp $
--===================================================================
--===========================================================================--
-- --
-- ram32k_b16.vhd - 32KByte Block RAM Component for Spartan 3/3E --
-- --
--===========================================================================--
--
-- File name : ram32k_b16.vhd
--
-- Entity name : ram_32k
--
-- Purpose : Implements 32K of Synchronous Static RAM
-- using 16 x Spartan 3/3E RAMB16_S9 block rams
-- Used in the Digilent Spartan 3E500 System09 design
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_arith
-- unisim.vcomponents
--
-- Uses : RAMB16_S9
--
-- Author : John E. Kent
--
-- Email : dilbert57@opencores.org
--
-- Web : http://opencores.org/project,system09
--
--
-- Copyright (C) 2005 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Author Date Changes
--
-- 0.1 John Kent 2006-04-24 Initial release
-- 0.2 John Kent 2005-06-29 Added CS term to CE decodes. (date ???)
-- 0.3 John Kent 2010-09-14 Renamed "rdata" to "data_out"
-- Renamed "wdata" to "data_in"
-- Added header description
--
-- 32K Block RAM
--
--===================================================================
--
-- Date: 24th April 2006
-- Author: John Kent
--
-- Revision History:
-- 24 April 2006 John Kent
-- Initial release
--
-- 29th June 2005 John Kent
-- Added CS term to CE decodes.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
24,13 → 63,13
 
entity ram_32k is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (14 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector (14 downto 0);
rw : in std_logic;
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end ram_32k;
 
37,25 → 76,25
architecture rtl of ram_32k is
 
 
signal we : std_logic;
signal dp : std_logic_vector(15 downto 0);
signal ce : std_logic_vector(15 downto 0);
signal rdata_0 : std_logic_vector(7 downto 0);
signal rdata_1 : std_logic_vector(7 downto 0);
signal rdata_2 : std_logic_vector(7 downto 0);
signal rdata_3 : std_logic_vector(7 downto 0);
signal rdata_4 : std_logic_vector(7 downto 0);
signal rdata_5 : std_logic_vector(7 downto 0);
signal rdata_6 : std_logic_vector(7 downto 0);
signal rdata_7 : std_logic_vector(7 downto 0);
signal rdata_8 : std_logic_vector(7 downto 0);
signal rdata_9 : std_logic_vector(7 downto 0);
signal rdata_a : std_logic_vector(7 downto 0);
signal rdata_b : std_logic_vector(7 downto 0);
signal rdata_c : std_logic_vector(7 downto 0);
signal rdata_d : std_logic_vector(7 downto 0);
signal rdata_e : std_logic_vector(7 downto 0);
signal rdata_f : std_logic_vector(7 downto 0);
signal we : std_logic;
signal dp : std_logic_vector(15 downto 0);
signal ce : std_logic_vector(15 downto 0);
signal data_out_0 : std_logic_vector(7 downto 0);
signal data_out_1 : std_logic_vector(7 downto 0);
signal data_out_2 : std_logic_vector(7 downto 0);
signal data_out_3 : std_logic_vector(7 downto 0);
signal data_out_4 : std_logic_vector(7 downto 0);
signal data_out_5 : std_logic_vector(7 downto 0);
signal data_out_6 : std_logic_vector(7 downto 0);
signal data_out_7 : std_logic_vector(7 downto 0);
signal data_out_8 : std_logic_vector(7 downto 0);
signal data_out_9 : std_logic_vector(7 downto 0);
signal data_out_a : std_logic_vector(7 downto 0);
signal data_out_b : std_logic_vector(7 downto 0);
signal data_out_c : std_logic_vector(7 downto 0);
signal data_out_d : std_logic_vector(7 downto 0);
signal data_out_e : std_logic_vector(7 downto 0);
signal data_out_f : std_logic_vector(7 downto 0);
 
begin
 
128,11 → 167,11
)
 
port map (
do => rdata_0,
do => data_out_0,
dop(0) => dp(0),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(0),
en => ce(0),
ssr => rst,
208,11 → 247,11
)
 
port map (
do => rdata_1,
do => data_out_1,
dop(0) => dp(1),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(1),
en => ce(1),
ssr => rst,
288,11 → 327,11
)
 
port map (
do => rdata_2,
do => data_out_2,
dop(0) => dp(2),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(2),
en => ce(2),
ssr => rst,
368,11 → 407,11
)
 
port map (
do => rdata_3,
do => data_out_3,
dop(0) => dp(3),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(3),
en => ce(3),
ssr => rst,
448,11 → 487,11
)
 
port map (
do => rdata_4,
do => data_out_4,
dop(0) => dp(4),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(4),
en => ce(4),
ssr => rst,
528,11 → 567,11
)
 
port map (
do => rdata_5,
do => data_out_5,
dop(0) => dp(5),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(5),
en => ce(5),
ssr => rst,
608,11 → 647,11
)
 
port map (
do => rdata_6,
do => data_out_6,
dop(0) => dp(6),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(6),
en => ce(6),
ssr => rst,
688,11 → 727,11
)
 
port map (
do => rdata_7,
do => data_out_7,
dop(0) => dp(7),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(7),
en => ce(7),
ssr => rst,
768,11 → 807,11
)
 
port map (
do => rdata_8,
do => data_out_8,
dop(0) => dp(8),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(8),
en => ce(8),
ssr => rst,
848,11 → 887,11
)
 
port map (
do => rdata_9,
do => data_out_9,
dop(0) => dp(9),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(9),
en => ce(9),
ssr => rst,
928,11 → 967,11
)
 
port map (
do => rdata_a,
do => data_out_a,
dop(0) => dp(10),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(10),
en => ce(10),
ssr => rst,
1008,11 → 1047,11
)
 
port map (
do => rdata_b,
do => data_out_b,
dop(0) => dp(11),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(11),
en => ce(11),
ssr => rst,
1088,11 → 1127,11
)
 
port map (
do => rdata_c,
do => data_out_c,
dop(0) => dp(12),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(12),
en => ce(12),
ssr => rst,
1168,11 → 1207,11
)
 
port map (
do => rdata_d,
do => data_out_d,
dop(0) => dp(13),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(13),
en => ce(13),
ssr => rst,
1248,11 → 1287,11
)
 
port map (
do => rdata_e,
do => data_out_e,
dop(0) => dp(14),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(14),
en => ce(14),
ssr => rst,
1328,11 → 1367,11
)
 
port map (
do => rdata_f,
do => data_out_f,
dop(0) => dp(15),
addr => addr(10 downto 0),
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp(15),
en => ce(15),
ssr => rst,
1340,46 → 1379,46
);
 
my_ram_32k : process ( cs, rw, addr,
rdata_0, rdata_1, rdata_2, rdata_3,
rdata_4, rdata_5, rdata_6, rdata_7,
rdata_8, rdata_9, rdata_a, rdata_b,
rdata_c, rdata_d, rdata_e, rdata_f )
data_out_0, data_out_1, data_out_2, data_out_3,
data_out_4, data_out_5, data_out_6, data_out_7,
data_out_8, data_out_9, data_out_a, data_out_b,
data_out_c, data_out_d, data_out_e, data_out_f )
begin
we <= not rw;
case addr(14 downto 11) is
when "0000" =>
rdata <= rdata_0;
data_out <= data_out_0;
when "0001" =>
rdata <= rdata_1;
data_out <= data_out_1;
when "0010" =>
rdata <= rdata_2;
data_out <= data_out_2;
when "0011" =>
rdata <= rdata_3;
data_out <= data_out_3;
when "0100" =>
rdata <= rdata_4;
data_out <= data_out_4;
when "0101" =>
rdata <= rdata_5;
data_out <= data_out_5;
when "0110" =>
rdata <= rdata_6;
data_out <= data_out_6;
when "0111" =>
rdata <= rdata_7;
data_out <= data_out_7;
when "1000" =>
rdata <= rdata_8;
data_out <= data_out_8;
when "1001" =>
rdata <= rdata_9;
data_out <= data_out_9;
when "1010" =>
rdata <= rdata_a;
data_out <= data_out_a;
when "1011" =>
rdata <= rdata_b;
data_out <= data_out_b;
when "1100" =>
rdata <= rdata_c;
data_out <= data_out_c;
when "1101" =>
rdata <= rdata_d;
data_out <= data_out_d;
when "1110" =>
rdata <= rdata_e;
data_out <= data_out_e;
when "1111" =>
rdata <= rdata_f;
data_out <= data_out_f;
when others =>
null;
end case;
/sys09s3e_b16.vhd
0,0 → 1,348
--===========================================================================--
-- --
-- sys09s3e_b16.vhd - System09 Bug monitor ROM for the Spartan 3E500 --
-- --
--===========================================================================--
--
-- File name : sys09s3e_b16.vhd
--
-- Entity name : SYS09BUG_F000
-- SYS09BUG_F800
--
-- Purpose : Implements 4K Monitor ROM for System09
-- using 2 x Spartan 3E RAMB16_S9 block rams
-- Used in the Digilent Spartan 3E500 System09 design
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_arith
-- unisim.vcomponents
--
-- Uses : RAMB16_S9
--
-- Author : John E. Kent
--
-- Email : dilbert57@opencores.org
--
-- Web : http://opencores.org/project,system09
--
--
-- Copyright (C) 2005 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Author Date Changes
-- 0.1 John Kent unknown Initial Version
-- 0.2 John Kent 2010-09-14 Added Header
-- renamed rdata & wdata to data_out & data_in
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
 
entity SYS09BUG_F000 is
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector(10 downto 0);
rw : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end SYS09BUG_F000;
 
architecture rtl of SYS09BUG_F000 is
 
type data_array is array(0 to 0) of std_logic_vector(7 downto 0);
signal xdata : data_array;
signal en : std_logic_vector(0 downto 0);
signal dp : std_logic_vector(0 downto 0);
signal we : std_logic;
 
component RAMB16_S9
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F,
INIT_10, INIT_11, INIT_12, INIT_13,
INIT_14, INIT_15, INIT_16, INIT_17,
INIT_18, INIT_19, INIT_1A, INIT_1B,
INIT_1C, INIT_1D, INIT_1E, INIT_1F,
INIT_20, INIT_21, INIT_22, INIT_23,
INIT_24, INIT_25, INIT_26, INIT_27,
INIT_28, INIT_29, INIT_2A, INIT_2B,
INIT_2C, INIT_2D, INIT_2E, INIT_2F,
INIT_30, INIT_31, INIT_32, INIT_33,
INIT_34, INIT_35, INIT_36, INIT_37,
INIT_38, INIT_39, INIT_3A, INIT_3B,
INIT_3C, INIT_3D, INIT_3E, INIT_3F : bit_vector (255 downto 0)
);
 
port (
clk : in std_logic;
ssr : in std_logic;
en : in std_logic;
we : in std_logic;
addr : in std_logic_vector(10 downto 0);
di : in std_logic_vector( 7 downto 0);
dip : in std_logic_vector( 0 downto 0);
do : out std_logic_vector( 7 downto 0);
dop : out std_logic_vector( 0 downto 0)
);
end component RAMB16_S9;
 
begin
 
ROM00: RAMB16_S9
generic map (
INIT_00 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0f => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1f => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2f => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3f => x"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
clk => clk,
ssr => rst,
en => en(0),
we => we,
addr => addr(10 downto 0),
di => data_in,
dip(0) => dp(0),
do => xdata(0),
dop(0) => dp(0)
);
rom_glue: process (cs, rw, addr, xdata)
begin
en(0) <= cs;
data_out <= xdata(0);
we <= not rw;
end process;
end architecture rtl;
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
 
entity SYS09BUG_F800 is
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector(10 downto 0);
rw : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end SYS09BUG_F800;
 
architecture rtl of SYS09BUG_F800 is
 
type data_array is array(0 to 0) of std_logic_vector(7 downto 0);
signal xdata : data_array;
signal en : std_logic_vector(0 downto 0);
signal dp : std_logic_vector(0 downto 0);
signal we : std_logic;
 
component RAMB16_S9
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F,
INIT_10, INIT_11, INIT_12, INIT_13,
INIT_14, INIT_15, INIT_16, INIT_17,
INIT_18, INIT_19, INIT_1A, INIT_1B,
INIT_1C, INIT_1D, INIT_1E, INIT_1F,
INIT_20, INIT_21, INIT_22, INIT_23,
INIT_24, INIT_25, INIT_26, INIT_27,
INIT_28, INIT_29, INIT_2A, INIT_2B,
INIT_2C, INIT_2D, INIT_2E, INIT_2F,
INIT_30, INIT_31, INIT_32, INIT_33,
INIT_34, INIT_35, INIT_36, INIT_37,
INIT_38, INIT_39, INIT_3A, INIT_3B,
INIT_3C, INIT_3D, INIT_3E, INIT_3F : bit_vector (255 downto 0)
);
 
port (
clk : in std_logic;
ssr : in std_logic;
en : in std_logic;
we : in std_logic;
addr : in std_logic_vector(10 downto 0);
di : in std_logic_vector( 7 downto 0);
dip : in std_logic_vector( 0 downto 0);
do : out std_logic_vector( 7 downto 0);
dop : out std_logic_vector( 0 downto 0)
);
end component RAMB16_S9;
 
begin
 
ROM00: RAMB16_S9
generic map (
INIT_00 => x"A780A610C6C07F8E104EFE8ECFFE0DFB11FB82FBBDFCA8FC8AFC90FC4BF814F8",
INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC6450117D07FBF00E08EF9265AA0",
INIT_02 => x"092C2081891FF1270D817F843C0417BC021783FE8EDE01173A03175EFE8E9204",
INIT_03 => x"FE8C02300F2780E118FE8E20C0022F60C14C0417510417408B981F5804175E86",
INIT_04 => x"1F6E02178BFE8E121F2D297403173B341FBC2094ADC020F9021785FE8EF5264E",
INIT_05 => x"17275E81DD271881E127088111286703170C0417AE0317A4A6140417AE031721",
INIT_06 => x"321FAB0217BE203F31C2202131EA03173F86ED03170827A4A1A4A7390F260D81",
INIT_07 => x"F0C4201F0634F0C41000C3101F390124E1AC2034062914031705201F30C07F8E",
INIT_08 => x"10C69B0317370317E4AEF701178BFE8E103439623203279F03170527E4AC011F",
INIT_09 => x"03172E8602237E810425208180A610C6E1AE8B0317F5265A93031735031780A6",
INIT_0a => x"273F8184A60F2710355B8DFFFF8E10341A24C07F8C1E29C00217BC20EE265A7C",
INIT_0b => x"431F39FB265A1E8D08C6D37F8E104B03163F864E03173984A73F86A4AFA0A709",
INIT_0c => x"A60A24C07F8C21AEB3FE16ED7FBF00008E5102170C8D4AAF04272C8D1F304AAE",
INIT_0d => x"265A0427A1ACA0A608C6D37F8E1039A0A7A0A7A0A7FF8684A7A4A604263F8184",
INIT_0e => x"7FBFE7F98EEB7FBFC07FBEED7FBF1429390217EE02171C295F0117393D3139F7",
INIT_0f => x"27ED7FBE24273F8184A64AAEEC011770E0B671E0B73686431F392020450017C0",
INIT_10 => x"3B71E0B73F8673E0B7368670E0B671E0B7368670E0B70D86341FED7FBF1F301F",
INIT_11 => x"B7368672E0B7008670E0B7FF8673E0B73A8671E0B7328622FE16C07FBFEB7FBE",
INIT_12 => x"81260217D27F7F6402171186D6FCBD8435FD265A20C604343973E0B73E8671E0",
INIT_13 => x"E0EBE0E61034212991011726290234A80117F12631813D2739811F0217F92653",
INIT_14 => x"FFC102355FEB2080A70527E46AE0EB02340C2904358E01170434E46AE46AE4EB",
INIT_15 => x"E4AF0130492562AC4D2930344A0117E26F0E02161386D27F731602173F86BA27",
INIT_16 => x"03CB2F0017CCFE8E64E720C6022320008310062762A3E4ECF501171286D6FCBD",
INIT_17 => x"AF5B0117981F53F526646A65011780A684EB63EB62EB68011762AE750117981F",
INIT_18 => x"00169D011690356900177DFE8E10347120028D396532B301171486C326E4AC62",
INIT_19 => x"8DDC8D728D3948AF0229EB8DE78D618D394AAF0229F68DF28D910017E50016F8",
INIT_1a => x"BB8D6C8D3943A70229C78DC68D498D3944AF0229D58DD18D5E8D3946AF0229E0",
INIT_1b => x"1739C4A7808A0429A68DA58D5F8D3941A70229B18DB08D588D3942A70229BC8D",
INIT_1c => x"8DADFE8EF42048AEEA8D9BFE8EBF0016311FF48D8FFE8E39F726048180A63B01",
INIT_1d => x"204AAEC58D95FE8ED82046AECE8DA1FE8EE12044AED78DA7FE8EB4001643A6E1",
INIT_1e => x"900016C4FE8EC4A6AA8DBDFE8ED02042A6B38DB8FE8ED92041A6BC8DB3FE8ECF",
INIT_1f => x"098DD520CE8DC78DC08D17FF178BFE8EBF8DB88DB08DA98DA18D27FF178BFE8E",
INIT_20 => x"4848483229118D903561A710343C29088D011F42290E8DB400172D86121F4D29",
INIT_21 => x"22468112254181393080032239811D253081578D39E0AB04342829078D891F48",
INIT_22 => x"4444444402340235028D0235103439021A395780032266810725618139378003",
INIT_23 => x"3B8D3F8D2D860225E46880A608C602344D20078B022F3981308B0F840235048D",
INIT_24 => x"84A620E08E0926018584A6D07FBE10342D207F84048D0627D27F7D8235F1265A",
INIT_25 => x"34498D2086008D8235018520E0B605260185D07F9FA60234903501A6EE270185",
INIT_26 => x"A7518684A70386D07FBE138D903501A70235F6260885FA27028584A6D07FBE12",
INIT_27 => x"7F01E702C6F17FFD04E703E702A7EF7FFD0000CC30E08E39D27FB7FF86016D84",
INIT_28 => x"84A70520098D042420810D20608D0427F27F7D30E08E16345986028D1B86F27F",
INIT_29 => x"270C81890027100D81382716817C0027101A815A271B81342708819635AF0017",
INIT_2a => x"EF7FB66D205A34275DEF7FFC8F0016792619C15CEF7FFC45260A810F270B8124",
INIT_2b => x"816E27598114273DC1F27FF656200000CC5820212750814CEF7FB662204A2C27",
INIT_2c => x"224F812080F27F7F39F17FB70426F17F7D39F27F7F39F27FB704263D81312754",
INIT_2d => x"508102A74C84E720C6EF7FB6168D0000CC1B20E12218C120C0F17F7FF17FF6ED",
INIT_2e => x"EA2619C15C4FF02650814CEF7FFC3903E702A7EF7FFDF07FF64F39F27F7FF726",
INIT_2f => x"7FF6F42650C15C84A702E7EF7FF72086EF7FF604E75F012519C15C04E6E78D5A",
INIT_30 => x"FB035CFB0267FB0139F27FF702E7EF7FF75FE4205F03E7F07FF7082719C15CF0",
INIT_31 => x"4DAFFA5051FA4C8FF847E7F84546F9423BFB1946FB1830FB1524FB1051FB0472",
INIT_32 => x"0A0DFFFFFFFF7EF991F891F891F891F87EF9C5F95472F958DBF853E0FB5292F8",
INIT_33 => x"000A0D4B04202D202045335320524F4620362E31204755423930535953000000",
INIT_34 => x"3D53552020043D43502020043D5053202004202D20043F54414857043E040000",
INIT_35 => x"432020043D422020043D412020043D50442020043D58492020043D5949202004",
INIT_36 => x"C07F9F6E38F916D27FF7535FC07FCE103904315343565A4E4948464504203A43",
INIT_37 => x"FF8CCC7FBE49584F4AAF80E64AAE431FCA7F9F6EC87F9F6EC67F9F6EC47F9F6E",
INIT_38 => x"000000000000C27F9F6E42EE1F37F16E44AEC4EC10340822CE7FBC8B300F27FF",
INIT_39 => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3a => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3b => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3c => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3d => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3e => x"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3f => x"D0FEDCFEECFEE8FEE4FEE0FEF0FEDCFE00000000000000000000000000000000"
)
port map (
clk => clk,
ssr => rst,
en => en(0),
we => we,
addr => addr(10 downto 0),
di => data_in,
dip(0) => dp(0),
do => xdata(0),
dop(0) => dp(0)
);
rom_glue: process (cs, rw, addr, xdata)
begin
en(0) <= cs;
data_out <= xdata(0);
we <= not rw;
end process;
end architecture rtl;
 
/sys09bug_s3e_rom2k_b16.vhd
1,8 → 1,56
--===========================================================================--
-- --
-- sys09bug_s3e_rom2k_b16.vhd - Sys09bug monitor ROM for the Spartan 3E500 --
-- --
--===========================================================================--
--
-- File name : sys09bug_s3e_rom2k_b16.vhd
--
-- Entity name : mon_rom
--
-- Purpose : Implements 2K Monitor ROM for System09
-- using 1 x Spartan 3E RAMB16_S9 block ram
-- Used in the Digilent Spartan 3E500 System09 design
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_arith
-- unisim.vcomponents
--
-- Uses : RAMB16_S9
--
-- Author : John E. Kent
--
-- Email : dilbert57@opencores.org
--
-- Web : http://opencores.org/project,system09
--
--
-- Copyright (C) 2008 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Author Date Changes
-- 0.1 John Kent 2008-01-08 Initial Version
-- 0.2 John Kent 2010-09-14 Added Header
-- renamed rdata & wdata to data_out & data_in
--
-- SYS09BUG MONITOR ROM FOR SYSTEM09 SPARTAN3E
-- John Kent
-- 8th January 2008
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
11,13 → 59,13
 
entity mon_rom is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector (10 downto 0);
rw : in std_logic;
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end mon_rom;
 
97,11 → 145,11
)
 
port map (
do => rdata,
do => data_out,
dop(0) => dp,
addr => addr,
clk => clk,
di => wdata,
di => data_in,
dip(0) => dp,
en => cs,
ssr => rst,
/keymap_rom_slice.vhd
109,11 → 109,11
 
begin
 
process( addr, rom_data, rom_out )
process( addr, rom_out )
begin
rom_out <= rom_data(conv_integer(addr(8 downto 5)));
data_out <= rom_out( conv_integer(addr(4 downto 0))*8+7 downto conv_integer(addr(4 downto 0))*8);
end;
end process;
 
end architecture rtl;
 
/sys09s3s_b16.vhd
0,0 → 1,198
--===========================================================================--
-- --
-- Synthesizable Sys09_bug RAM using 2 x Xilinx RAMB16_S9 Block RAM --
-- --
--===========================================================================--
--
-- File name : sys09s3s_b16.vhd
--
-- Entity name : sys09bug_f800
--
-- Purpose : Implements 2KByte Sys09_bug ROM
-- for the 200K gate Digilent spartan 3 starter board
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_arith
-- unisim.vcomponents
--
-- Uses : RAMB16_S9
--
-- Author : John E. Kent
--
-- Email : dilbert57@opencores.org
--
-- Web : http://opencores.org/project,system09
--
-- Description : Block RAM instatiation
--
-- Copyright (C) 2006 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Date Author Changes
--
-- 1.1 2006-12-22 John Kent Made into 4K ROM/RAM.
-- 1.2 2010-06-17 John Kent Added GPL and header
-- Renamed data input and output signals
-- Removed ROM at $F000 to $F7FF
--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
 
entity SYS09BUG_F800 is
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector(10 downto 0);
rw : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end SYS09BUG_F800;
 
architecture rtl of SYS09BUG_F800 is
 
signal dp : std_logic_vector(0 downto 0);
signal we : std_logic;
 
component RAMB16_S9
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F,
INIT_10, INIT_11, INIT_12, INIT_13,
INIT_14, INIT_15, INIT_16, INIT_17,
INIT_18, INIT_19, INIT_1A, INIT_1B,
INIT_1C, INIT_1D, INIT_1E, INIT_1F,
INIT_20, INIT_21, INIT_22, INIT_23,
INIT_24, INIT_25, INIT_26, INIT_27,
INIT_28, INIT_29, INIT_2A, INIT_2B,
INIT_2C, INIT_2D, INIT_2E, INIT_2F,
INIT_30, INIT_31, INIT_32, INIT_33,
INIT_34, INIT_35, INIT_36, INIT_37,
INIT_38, INIT_39, INIT_3A, INIT_3B,
INIT_3C, INIT_3D, INIT_3E, INIT_3F : bit_vector (255 downto 0)
);
 
port (
clk : in std_logic;
ssr : in std_logic;
en : in std_logic;
we : in std_logic;
addr : in std_logic_vector(10 downto 0);
di : in std_logic_vector( 7 downto 0);
dip : in std_logic_vector( 0 downto 0);
do : out std_logic_vector( 7 downto 0);
dop : out std_logic_vector( 0 downto 0)
);
end component RAMB16_S9;
 
begin
 
ROM00: RAMB16_S9
generic map (
INIT_00 => x"A780A610C6C0DF8E1062FE8E2EFA1AFB1EFB8FFBCEFCB9FC9BFCA1FC61F814F8",
INIT_01 => x"17431FE4A7D0866AAFDD8C30FB265AE26F0CC65B0117E0DFBF00E08EF9265AA0",
INIT_02 => x"031796FE8E0C0417F62A5A19048B0327856D0DC64FD0DF8E47031772FE8EA304",
INIT_03 => x"17408B981F5304175E86092C2081891FF1270D817F84370417B302179DFE8E2E",
INIT_04 => x"20F002179FFE8EF52662FE8C02300F2780E129FE8E20C0022F60C14704174C04",
INIT_05 => x"17A4A60F0417A50317211F650217A5FE8E121F2D296B03173B341FBC2094ADC0",
INIT_06 => x"27A4A1A4A7390F260D8117275E81DD271881E127088111285E0317070417A503",
INIT_07 => x"0B031705201F30C0DF8E321FA20217BE203F31C2202131E503173F86E8031708",
INIT_08 => x"279A03170527E4AC011FF0C4201F0634F0C41000C3101F390124E1AC20340629",
INIT_09 => x"265A8E03172C031780A610C69603172E0317E4AEEE0117A5FE8E103439623203",
INIT_0a => x"29B70217BC20EE265A7703172E8602237E810425208180A610C6E1AE860317F5",
INIT_0b => x"3984A73F86A4AFA0A709273F8184A60F271035558DFFFF8E10341A24C0DF8C1E",
INIT_0c => x"4AAF0427268D1F304AAE431F39FB265A188D08C6E3DF8E104603163F86490317",
INIT_0d => x"A7A0A7A0A7FF8684A7A4A604263F8184A60A24C0DF8C21AEB9FE16480217068D",
INIT_0e => x"0186398D46E0B7E086408D393D3139F7265A0427A1ACA0A608C6E3DF8E1039A0",
INIT_0f => x"178D47E0B7208645E0B744E0B743E0B74F42E0B701862D8D47E0B7EF8641E0B7",
INIT_10 => x"E0B6F926808547E0B63B341F4AAF00C08EF42600C28C80A740E0B6218D00C08E",
INIT_11 => x"54545454A6E6D0DF8E104444444462A6363439F927088547E0B639F227408547",
INIT_12 => x"FCBD8435FD265A20C60434B63562E762EA62A70F8462A65858585853A6E6E4E7",
INIT_13 => x"0234A80117F12631813D273981230217F92653812A0217E2DF7F6802171186E7",
INIT_14 => x"E0EB02340C2904358E01170434E46AE46AE4EBE0EBE0E6103421299101172629",
INIT_15 => x"0117E26F1202161386E2DF731A02173F86BA27FFC102355FEB2080A70527E46A",
INIT_16 => x"2320008310062762A3E4ECF901171286E7FCBDE4AF0130492562AC4D2930344A",
INIT_17 => x"1780A684EB63EB62EB68011762AE750117981F03CB2F0017E6FE8E64E720C602",
INIT_18 => x"10347120028D396532B701171486C326E4AC62AF5B0117981F53F526646A6501",
INIT_19 => x"8D618D394AAF0229F68DF28D910017E50016F80016A10116903569001797FE8E",
INIT_1a => x"498D3944AF0229D58DD18D5E8D3946AF0229E08DDC8D728D3948AF0229EB8DE7",
INIT_1b => x"8D3941A70229B18DB08D588D3942A70229BC8DBB8D6C8D3943A70229C78DC68D",
INIT_1c => x"BF0016311FF48DA9FE8E39F726048180A63F011739C4A7808A0429A68DA58D5F",
INIT_1d => x"8DBBFE8EE12044AED78DC1FE8EB4001643A6E18DC7FE8EF42048AEEA8DB5FE8E",
INIT_1e => x"D02042A6B38DD2FE8ED92041A6BC8DCDFE8ECF204AAEC58DAFFE8ED82046AECE",
INIT_1f => x"A5FE8EBF8DB88DB08DA98DA18D27FF17A5FE8E900016DEFE8EC4A6AA8DD7FE8E",
INIT_20 => x"3C29088D011F42290E8DB800172D86121F4D29098DD520CE8DC78DC08D17FF17",
INIT_21 => x"811D2530815B8D39E0AB04342829078D891F484848483229118D903561A71034",
INIT_22 => x"3439021A39578003226681072561813937800322468112254181393080032239",
INIT_23 => x"C602345120078B022F3981308B0F840235048D4444444402340235028D023510",
INIT_24 => x"207F84048D0627E2DF7D00F09F6E8235F1265A3F8D438D2D860225E46880A608",
INIT_25 => x"85E0DF9FA60234903501A6EE27018584A620E08E0926018584A6E0DFBE10342D",
INIT_26 => x"35F6260885FA27028584A6E0DFBE1234498D2086008D8235018520E0B6052601",
INIT_27 => x"0000CC30E08E39E2DFB7FF86016D84A7518684A70386E0DFBE138D903501A702",
INIT_28 => x"DF7D30E08E16345986028D1B86FEDF7F01E702C6FDDFFD04E703E702A7FBDFFD",
INIT_29 => x"1A815A271B81342708819635AF001784A70520098D042420810D20608D0427FE",
INIT_2a => x"19C15CFBDFFC45260A810F270B8124270C81890027100D81382716817C002710",
INIT_2b => x"5820212750814CFBDFB662204A2C27FBDFB66D205A34275DFBDFFC8F00167926",
INIT_2c => x"39FEDF7F39FEDFB704263D81312754816E27598114273DC1FEDFF656200000CC",
INIT_2d => x"1B20E12218C120C0FDDF7FFDDFF6ED224F812080FEDF7F39FDDFB70426FDDF7D",
INIT_2e => x"02A7FBDFFDFCDFF64F39FEDF7FF726508102A74C84E720C6FBDFB6168D0000CC",
INIT_2f => x"DFF604E75F012519C15C04E6E78D5AEA2619C15C4FF02650814CFBDFFC3903E7",
INIT_30 => x"5FE4205F03E7FCDFF7082719C15CFCDFF6F42650C15C84A702E7FBDFF72086FB",
INIT_31 => x"FB1953FB183DFB1531FB105EFB047FFB0369FB0274FB0139FEDFF702E7FBDFF7",
INIT_32 => x"55D5F94488F958F1F853EDFB52A8F84DBCFA505EFA4CA5F847FDF8455CF94248",
INIT_33 => x"2047554239305359530000000A0DFFFFFFFF94F9A7F8A7F8A7F8A7F894F992FC",
INIT_34 => x"57043E040000000A0D4B04202D202052455452415453335320524F4620362E31",
INIT_35 => x"3D59492020043D53552020043D43502020043D5053202004202D20043F544148",
INIT_36 => x"464504203A43432020043D422020043D412020043D50442020043D5849202004",
INIT_37 => x"000000000000000000000000000000000000000000000004315343565A4E4948",
INIT_38 => x"300B2784AC1084AF1084EEAA558E10A0D08E84A7F086FB264A80A70F86F0FF8E",
INIT_39 => x"2DA7D0DF8E10C0DFCE10FDFFB74444444443101F84EFD620ED26A0F08C00F089",
INIT_3a => x"1084AF10AA558E1084EE2227A0F08C00F08930FB2A4AA66F0C862FA7F0862E6F",
INIT_3b => x"2EA7D0DF8E10F186D520A5A70F88891F44444444101FD0DF8E1084EFE92684AC",
INIT_3c => x"8EF32D0C814C80E7A66F0427A6E6211F4F2CE7A66F1420F92A4A0526A6E60C86",
INIT_3d => x"9F6EC6DF9F6EC4DF9F6EC0DF9F6E62F816E2DFF753F9265A80A7A0A610C6F0FF",
INIT_3e => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
INIT_3f => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
)
port map (
clk => clk,
ssr => rst,
en => cs,
we => we,
addr => addr(10 downto 0),
di => data_in,
dip(0) => dp(0),
do => data_out,
dop(0) => dp(0)
);
rom_glue: process ( rw )
begin
we <= not rw;
end process;
end architecture rtl;
 

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