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    /System09/trunk/rtl/System09_BurchED_B3
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Rev 107 → Rev 66

/System09_BurchED_B3.ucf
4,53 → 4,51
# XC2S200.
#
# B3 Connector J3
# IDE / CF Interface
# Note that this pin out is NOT consistant with the B5-IDE
# B5-X300 Connector C
#
#NET "ide_gclk1" LOC = "p185"; #pin 2 (Global clock input)
#NET "ide_spare1" LOC = "p181"; #pin 3
NET "ide_rst_n" LOC = "p187"; #pin 4 - ide pin 1
NET "ide_dmarq" LOC = "p188"; #pin 5 - ide pin 21
NET "pb_iowr_n" LOC = "p189"; #pin 6 - ide pin 23
NET "pb_iord_n" LOC = "p191"; #pin 7 - ide pin 25
NET "ide_iordy" LOC = "p192"; #pin 8 - ide pin 27
NET "ide_con_csel" LOC = "p193"; #pin 9 - ide pin 28
NET "ide_dmack_n" LOC = "p194"; #pin 10 - ide pin 29
NET "ide_intrq" LOC = "p195"; #pin 11 - ide pin 31
NET "ide_iocs16_n" LOC = "p199"; #pin 12 - ide pin 32
NET "pb_addr<1>" LOC = "p200"; #pin 13 - ide pin 33
NET "ide_pdiag_n" LOC = "p201"; #pin 14 - ide pin 34
NET "pb_addr<0>" LOC = "p202"; #pin 15 - ide pin 35
NET "pb_addr<2>" LOC = "p203"; #pin 16 - ide pin 36
NET "ide_cs0_n" LOC = "p204"; #pin 17 - ide pin 37
NET "ide_cs1_n" LOC = "p205"; #pin 18 - ide pin 38
NET "ide_dasp_n" LOC = "p206"; #pin 19 - ide pin 39
#NET "b5_clk" LOC = "p185"; #pin 2 (Global clock input)
NET "bus_addr<0>" LOC = "p181"; #pin 3
NET "bus_addr<1>" LOC = "p187"; #pin 4
NET "bus_addr<2>" LOC = "p188"; #pin 5
NET "bus_addr<3>" LOC = "p189"; #pin 6
NET "bus_addr<4>" LOC = "p191"; #pin 7
NET "bus_addr<5>" LOC = "p192"; #pin 8
NET "bus_addr<6>" LOC = "p193"; #pin 9
NET "bus_addr<7>" LOC = "p194"; #pin 10
NET "bus_addr<8>" LOC = "p195"; #pin 11
NET "bus_addr<9>" LOC = "p199"; #pin 12
NET "bus_addr<10>" LOC = "p200"; #pin 13
NET "bus_addr<11>" LOC = "p201"; #pin 14
NET "bus_addr<12>" LOC = "p202"; #pin 15
NET "bus_addr<13>" LOC = "p203"; #pin 16
NET "bus_addr<14>" LOC = "p204"; #pin 17
NET "bus_addr<15>" LOC = "p205"; #pin 18
NET "bus_csn" LOC = "p206"; #pin 19
#
# B3 Connector J4
# IDE / CF Interface
# Note that this pin out is NOT consistant with the B5-IDE
# It's called the peripheral bus for consistance with the XESS board
# B5-X300 Connector D
#
#NET "pb_gclk2" LOC = "p182"; #pin 2 (Global clock input)
#NET "pb_spare2" LOC = "p160"; #pin 3
NET "pb_data<7>" LOC = "p161"; #pin 4 - ide pin 3
NET "pb_data<8>" LOC = "p162"; #pin 5 - ide pin 4
NET "pb_data<6>" LOC = "p163"; #pin 6 - ide pin 5
NET "pb_data<9>" LOC = "p164"; #pin 7 - ide pin 6
NET "pb_data<5>" LOC = "p165"; #pin 8 - ide pin 7
NET "pb_data<10>" LOC = "p166"; #pin 9 - ide pin 8
NET "pb_data<4>" LOC = "p167"; #pin 10 - ide pin 9
NET "pb_data<11>" LOC = "p168"; #pin 11 - ide pin 10
NET "pb_data<3>" LOC = "p172"; #pin 12 - ide pin 11
NET "pb_data<12>" LOC = "p173"; #pin 13 - ide pin 12
NET "pb_data<2>" LOC = "p174"; #pin 14 - ide pin 13
NET "pb_data<13>" LOC = "p175"; #pin 15 - ide pin 14
NET "pb_data<1>" LOC = "p176"; #pin 16 - ide pin 15
NET "pb_data<14>" LOC = "p178"; #pin 17 - ide pin 16
NET "pb_data<0>" LOC = "p179"; #pin 18 - ide pin 17
NET "pb_data<15>" LOC = "p180"; #pin 19 - ide pin 18
#NET "GCK2" LOC = "p182"; #pin 2 (Global clock input)
NET "bus_clk" LOC = "p160"; #pin 3
NET "bus_reset" LOC = "p161"; #pin 4
#NET "bus_hold" LOC = "p162"; #pin 5
#NET "bus_irq" LOC = "p163"; #pin 6
NET "bus_addr<16>" LOC = "p164"; #pin 7
NET "bus_addr<17>" LOC = "p165"; #pin 8
NET "bus_addr<18>" LOC = "p166"; #pin 9
NET "bus_addr<19>" LOC = "p167"; #pin 10
NET "bus_data<0>" LOC = "p168"; #pin 11
NET "bus_data<1>" LOC = "p172"; #pin 12
NET "bus_data<2>" LOC = "p173"; #pin 13
NET "bus_data<3>" LOC = "p174"; #pin 14
NET "bus_data<4>" LOC = "p175"; #pin 15
NET "bus_data<5>" LOC = "p176"; #pin 16
NET "bus_data<6>" LOC = "p178"; #pin 17
NET "bus_data<7>" LOC = "p179"; #pin 18
NET "bus_rw" LOC = "p180"; #pin 19
#
# Connector J3
#
# For B5-Compact-Flash:
#
#NET "GCK3" LOC = "P185"; #J2-2 (Global Clock input)
73,6 → 71,7
#NET "cf_rst_n" LOC = "P206"; #J2-19
#
# Connector J4
#
# For B5-Compact-Flash:
#
#NET "GCK2" LOC = "P182"; #J1-2 (Global Clock Input)
143,48 → 142,45
NET "ram_addr<16>" LOC = "p132"; #J1-19
#
# Connector J10
# B5-X300 Interface to Dual Port RAM
#
NET "clk_in" LOC = "p77"; #pin 2 (GCK1 - global clock input)
NET "led" LOC = "p49"; #pin 3 (LED output)
NET "bus_cs_n" LOC = "p57"; #pin 4
NET "bus_rw" LOC = "p58"; #pin 5
NET "bus_addr<12>" LOC = "p59"; #pin 6
NET "bus_addr<11>" LOC = "p60"; #pin 7
NET "rst_n" LOC = "p61"; #pin 8 (Test Input button)
NET "bus_addr<10>" LOC = "p62"; #pin 9
NET "bus_addr<9>" LOC = "p63"; #pin 10
NET "bus_addr<8>" LOC = "p67"; #pin 11
NET "bus_addr<7>" LOC = "p68"; #pin 12
NET "bus_addr<6>" LOC = "p69"; #pin 13
NET "bus_addr<5>" LOC = "p70"; #pin 14
NET "bus_addr<4>" LOC = "p71"; #pin 15
NET "bus_addr<3>" LOC = "p73"; #pin 16
NET "bus_addr<2>" LOC = "p74"; #pin 17
NET "bus_addr<1>" LOC = "p75"; #pin 18
NET "bus_addr<0>" LOC = "p81"; #pin 19
#
# Connector J11
# B5-X300 Interface to Dual Port RAM
NET "SysClk" LOC = "p77"; #pin 2 (GCK1 - global clock input)
NET "led" LOC = "p49"; #pin 3 (LED output)
#NET "uart_csn" LOC = "p57"; #pin 4
#NET "test_rw" LOC = "p58"; #pin 5
#NET "test_d0" LOC = "p59"; #pin 6
#NET "test_d1" LOC = "p60"; #pin 7
NET "reset_n" LOC = "p61"; #pin 8 (Test Input button)
#NET "test_cc<0>" LOC = "p67"; #pin 11
#NET "test_cc<1>" LOC = "p68"; #pin 12
#NET "test_cc<2>" LOC = "p69"; #pin 13
#NET "test_cc<3>" LOC = "p70"; #pin 14
#NET "test_cc<4>" LOC = "p71"; #pin 15
#NET "test_cc<5>" LOC = "p73"; #pin 16
#NET "test_cc<6>" LOC = "p74"; #pin 17
#NET "test_cc<7>" LOC = "p75"; #pin 18
#NET "IO" LOC = "p81"; #pin 19
#
# Connector J11
#
#NET "GCK0" LOC = "p80"; #pin 2 (Global Clock input)
NET "bus_data_in<7>" LOC = "p82"; #pin 3
NET "bus_data_in<6>" LOC = "p83"; #pin 4
NET "bus_data_in<5>" LOC = "p84"; #pin 5
NET "bus_data_in<4>" LOC = "p86"; #pin 6
NET "bus_data_in<3>" LOC = "p87"; #pin 7
NET "bus_data_in<2>" LOC = "p88"; #pin 8
NET "bus_data_in<1>" LOC = "p89"; #pin 9
NET "bus_data_in<0>" LOC = "p90"; #pin 10
NET "bus_data_out<7>" LOC = "p94"; #pin 11
NET "bus_data_out<6>" LOC = "p95"; #pin 12
NET "bus_data_out<5>" LOC = "p96"; #pin 13
NET "bus_data_out<4>" LOC = "p97"; #pin 14
NET "bus_data_out<3>" LOC = "p98"; #pin 15
NET "bus_data_out<2>" LOC = "p99"; #pin 16
NET "bus_data_out<1>" LOC = "p100"; #pin 17
NET "bus_data_out<0>" LOC = "p101"; #pin 18
NET "bus_clk" LOC = "p102"; #pin 19
NET "porta<0>" LOC = "p82"; #pin 3
NET "porta<1>" LOC = "p83"; #pin 4
NET "porta<2>" LOC = "p84"; #pin 5
NET "porta<3>" LOC = "p86"; #pin 6
NET "porta<4>" LOC = "p87"; #pin 7
NET "porta<5>" LOC = "p88"; #pin 8
NET "porta<6>" LOC = "p89"; #pin 9
NET "porta<7>" LOC = "p90"; #pin 10
NET "portb<0>" LOC = "p94"; #pin 11
NET "portb<1>" LOC = "p95"; #pin 12
NET "portb<2>" LOC = "p96"; #pin 13
NET "portb<3>" LOC = "p97"; #pin 14
NET "portb<4>" LOC = "p98"; #pin 15
NET "portb<5>" LOC = "p99"; #pin 16
NET "portb<6>" LOC = "p100"; #pin 17
NET "portb<7>" LOC = "p101"; #pin 18
NET "timer_out" LOC = "p102"; #pin 19
#
# Connector J8
#
194,85 → 190,43
#NET "buzzer" LOC = "p27"; #J1-3
#NET "mouse_clock" LOC = "p29"; #J1-4
#NET "mouse_data" LOC = "p30"; #J1-5
NET "acia_cts_n" LOC = "p31"; #J1-6
NET "acia_rts_n" LOC = "p33"; #J1-7
NET "acia_txd" LOC = "p34"; #J1-8
NET "acia_rxd" LOC = "p35"; #J1-9
NET "cts_n" LOC = "p31"; #J1-6
NET "rts_n" LOC = "p33"; #J1-7
NET "txbit" LOC = "p34"; #J1-8
NET "rxbit" LOC = "p35"; #J1-9
NET "kb_clock" LOC = "p36"; #J1-10
NET "kb_data" LOC = "p37"; #J1-11
NET "vga_vsync" LOC = "p41"; #J1-12
NET "vga_hsync" LOC = "p42"; #J1-13
NET "vga_blue<0>" LOC = "p43"; #J1-14
NET "vga_blue<1>" LOC = "p44"; #J1-15
NET "vga_green<0>" LOC = "p45"; #J1-16
NET "vga_green<1>" LOC = "p46"; #J1-17
NET "vga_red<0>" LOC = "p47"; #J1-18
NET "vga_red<1>" LOC = "p48"; #J1-19
NET "v_drive" LOC = "p41"; #J1-12
NET "h_drive" LOC = "p42"; #J1-13
NET "blue_lo" LOC = "p43"; #J1-14
NET "blue_hi" LOC = "p44"; #J1-15
NET "green_lo" LOC = "p45"; #J1-16
NET "green_hi" LOC = "p46"; #J1-17
NET "red_lo" LOC = "p47"; #J1-18
NET "red_hi" LOC = "p48"; #J1-19
#
# Connector J5
#
# Printer port
#
NET "pp_ctrl<0>" LOC = "p3"; #J5-1 DB25 - 1 strobe_n
NET "pp_ctrl<1>" LOC = "p4"; #J5-2 DB25 - 14 auto Linefeed
NET "pp_data<0>" LOC = "p5"; #J5-3 DB25 - 2 data<0>
NET "pp_stat<3>" LOC = "p6"; #J5-4 DB25 - 15 error_n
NET "pp_data<1>" LOC = "p7"; #J5-5 DB25 - 3 data<1>
NET "pp_ctrl<2>" LOC = "p8"; #J5-6 DB25 - 16 initialize_n
NET "pp_data<2>" LOC = "p9"; #J5-7 DB25 - 4 data<2>
NET "pp_ctrl<3>" LOC = "p10"; #J5-8 DB25 - 17 select_printer_n
NET "pp_data<3>" LOC = "p14"; #J5-9 DB25 - 5 data<3>
# #J5-10 DB25 - 18 ground
NET "pp_data<4>" LOC = "p15"; #J5-11 DB25 - 6 data<4>
# #J5-12 DB25 - 19 ground
NET "pp_data<5>" LOC = "p16"; #J5-13 DB25 - 7 data<5>
# #J5-14 DB25 - 20 ground
NET "pp_data<6>" LOC = "p17"; #J5-15 DB25 - 8 data<6>
# #J5-16 DB25 - 21 ground
NET "pp_data<7>" LOC = "p18"; #J5-17 DB25 - 9 data<7>
# #J5-18 DB25 - 22 ground
NET "pp_stat<6>" LOC = "p20"; #J5-19 DB25 - 10 ack_n
# #J5-20 DB25 - 23 ground
NET "pp_stat<7>" LOC = "p21"; #J5-21 DB25 - 11 busy
# #J5-22 DB25 - 24 ground
NET "pp_stat<5>" LOC = "p22"; #J5-23 DB25 - 12 paper_out
# #J5-24 DB25 - 25 ground
NET "pp_stat<4>" LOC = "p23"; #J5-25 DB25 - 13 select
# #J5-26 +3.3V
# Parallel printer port pin assignment
#
# Pin No (DB25) SPP Signal EPP Signal Direction Register Bit Inverted
# 1 nStrobe Write_n Out Control-0 Yes
# 2 Data0 Data0 In/Out Data-0 No
# 3 Data1 Data1 In/Out Data-1 No
# 4 Data2 Data2 In/Out Data-2 No
# 5 Data3 Data3 In/Out Data-3 No
# 6 Data4 Data4 In/Out Data-4 No
# 7 Data5 Data5 In/Out Data-5 No
# 8 Data6 Data6 In/Out Data-6 No
# 9 Data7 Data7 In/Out Data-7 No
# 10 nAck Interrupt In Status-6 No
# 11 Busy Wait In Status-7 Yes
# 12 Paper-Out Spare In Status-5 No
# 13 Select Spare In Status-4 No
#
# 14 Linefeed Data_Strobe_n Out Control-1 Yes
# 15 nError Spare In Status-3 No
# 16 nInitialize Reset Out Control-2 No
# 17 nSelect-Printer Addr_Strobe_n Out Control-3 Yes
# 18-25 Ground Ground - - -
#
# Address MSB LSB
# Bit: 7 6 5 4 3 2 1 0
#Base (SPP Data port) Write Pin: 9 8 7 6 5 4 3 2
#Base+1 (SPP Status port) Read Pin: ~11 10 12 13 15
#Base+2 (SPP Control port) Write Pin: ~17 16 ~14 ~1
#Base+3 (EPP Address port) R/W
#Base+4 (EPP Data port) R/W
#
# ~ indicates a hardware inversion of the bit.
#
#
#NET "strobe_n" LOC = "p3"; #J5-1
#NET "autofd_n" LOC = "p4"; #J5-2
#NET "pd<0>" LOC = "p5"; #J5-3
#NET "fault_n" LOC = "p6"; #J5-4
#NET "pd<1>" LOC = "p7"; #J5-5
#NET "init_n" LOC = "p8"; #J5-6
#NET "pd<2>" LOC = "p9"; #J5-7
#NET "selin" LOC = "p10"; #J5-8
#NET "pd<3>" LOC = "p14"; #J5-9
#NET "pd<4>" LOC = "p15"; #J5-11
#NET "pd<5>" LOC = "p16"; #J5-13
#NET "pd<6>" LOC = "p17"; #J5-15
#NET "pd<7>" LOC = "p18"; #J5-17
#NET "ack" LOC = "p20"; #J5-19
#NET "busy" LOC = "p21"; #J5-21
#NET "pe" LOC = "p22"; #J5-23
#NET "sel" LOC = "p23"; #J5-25
#
# Timing Groups
#
INST "ram_addr<0>" TNM = "ram_addr";
314,15 → 268,16
INST "ram_wrun" TNM = "ram_wr";
#INST "ram_csn" TNM = "ram_cs";
#
#
# Timing Constraints
#
NET "clk_in" TNM_NET = "clk_in";
TIMESPEC "TS_clk_in" = PERIOD "clk_in" 20 ns HIGH 50 %;
#TIMEGRP "ram_cs" OFFSET = OUT 55 ns AFTER "clk_in";
#TIMEGRP "ram_wr" OFFSET = OUT 55 ns AFTER "clk_in";
#TIMEGRP "ram_addr" OFFSET = OUT 55 ns AFTER "clk_in";
#TIMEGRP "ram_data" OFFSET = OUT 55 ns AFTER "clk_in";
#TIMEGRP "ram_data" OFFSET = IN 15 ns BEFORE "clk_in";
NET "SysClk" TNM_NET = "SysClk";
TIMESPEC "TS_SysClk" = PERIOD "SysClk" 20 ns HIGH 50 %;
#TIMEGRP "ram_cs" OFFSET = OUT 40 ns AFTER "SysClk";
TIMEGRP "ram_wr" OFFSET = OUT 40 ns AFTER "SysClk";
TIMEGRP "ram_addr" OFFSET = OUT 40 ns AFTER "SysClk";
TIMEGRP "ram_data" OFFSET = OUT 40 ns AFTER "SysClk";
TIMEGRP "ram_data" OFFSET = IN 15 ns BEFORE "SysClk";
#
# Fast I/O Pins
#
/System09_BurchED_B3.ise Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/System09_BurchED_B3.vhd
1,1313 → 1,1191
--=============================================================================--
-- --
-- System09 - Synthesizable System On a Chip - VHDL FPGA core top level file. --
-- --
--=============================================================================--
--
-- File name : System09_BurchED_B3.vhd
--
-- Purpose : This is the top level file for a 6809 instruction compatible system on a chip
-- It has been designed for the BurchED B3 Spartan2+ FPGA board
-- using the Xilinx XC2S200 Spartan 2 FPGA and Xilinx ISE 7.1 software.
-- It has been implemented with the BurchED B3 FPGA board,
-- modified B3-SRAM module and B3-FPGA-CPU-IO module.
-- It also supports an IDE CF card interface using a CF to IDE interface adapter.
-- It uses a monochrome version of the VDU due to limitted Block RAM of XC2S200
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- ieee.numeric_std
--
-- Uses :
-- clk_div (..\Spartan2\clk_div.vhd) System Clock Divider
-- cpu09 (..\VHDL\cpu09.vhd) CPU core
-- B3_SRAM (..\VHDL\B3_SRAM.vhd) BurchED B3 SRAM module interface
-- acia6850 (..\VHDL\acia6850.vhd) RS232 Serial Interface
-- ACIA_Clock (..\VHDL\ACIA_Clock.vhd) ACIA Baud Rate Clock Divider
-- keyboard (..\VHDL\keyboard.vhd) PS/2 Keyboard register interface
-- ps2_keyboard (..\VHDL\ps2_keyboard.vhd) PS/2 Keyboard interface logic
-- keymap_rom (..\Spartan2\keymap_rom_b4.vhd) PS/2 Keyboard key code look up table
-- vdu8_mono (..\VHDL\vdu8_mono.vhd) 80 x 25 Monochrome Visual Display Unit.
-- char_rom (..\Spartan2\char_rom2k_b4.vhd) Character Generator ROM
-- ram_2k (..\Spartan2\ram2k_b4.vhd) Text buffer RAM
-- timer (..\VHDL\timer.vhd) Timer module
-- trap (..\VHDL\trap.vhd) Bus Trap interrupt
-- spp (..\VHDL\spp.vhd) Simple Parallel Port
-- peripheral_bus (..\VHDL\peripheral_bus.vhd) 16 bit IDE Peripheral Bus interface
-- sys09bug_F800 (..\Spartan2\sys09b3s_b4.vhd) Sysbug09 Monitor ROM
-- dat_ram (..\VHDL\datram.vhd) Dynamic Address Translation (DAT)
--
-- Author : John E. Kent
-- dilbert57@opencores.org
--
-- Memory Map :
--
-- $0000 - $DFFF System RAM (256K Mapped via DAT)
-- $E000 - ACIA (SWTPc)
-- $E010 - Reserved for SWTPc FD-01 FD1771 FDC
-- $E020 - Keyboard
-- $E030 - VDU
-- $E040 - Reserved for SWTPc MP-T (was Compact Flash)
-- $E050 - Timer
-- $E060 - Bus Trap (Hardware Breakpoint Interrupt Logic)
-- $E070 - Reserved for Trace Buffer
-- $E080 - Reserved for SWTPc MP-ID 6821 PIA (?)
-- $E090 - Reserved for SWTPc MP-ID 6840 PTM (?)
-- $E0A0 - SPP Printer Port
-- $E0B0 - Reserved
-- $E0C0 - Reserved
-- $E100 - $E13F IDE / Compact Flash Card
-- $E140 - $E17F Reserved for Ethernet MAC (XESS)
-- $E180 - $E1BF Reserved for Expansion Slot 0 (XESS)
-- $E1C0 - $E1FF Reserved for Expansion Slot 1 (XESS)
-- $E200 - $EFFF Dual Port RAM interface
-- $F000 - $F7FF Reserved SWTPc DMAF-2
-- $F800 - $FFFF Sys09bug ROM (Read only)
-- $FFF0 - $FFFF DAT - Dynamic Address Translation (Write Only)
--
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
--
-- Revision History:
--
--===========================================================================--
-- Version 0.1 - 20 March 2003
-- Version 0.2 - 30 March 2003
-- Version 0.3 - 29 April 2003
-- Version 0.4 - 29 June 2003
--
-- Version 0.5 - 19 July 2003
-- prints out "Hello World"
--
-- Version 0.6 - 5 September 2003
-- Runs SBUG
--
-- Version 1.0- 6 Sep 2003 - John Kent
-- Inverted SysClk
-- Initial release to Open Cores
--
-- Version 1.1 - 17 Jan 2004 - John Kent
-- Updated miniUart.
--
-- Version 1.2 - 25 Jan 2004 - John Kent
-- removed signals "test_alu" and "test_cc"
-- Trap hardware re-instated.
--
-- Version 1.3 - 11 Feb 2004 - John Kent
-- Designed forked off to produce System09_VDU
-- Added VDU component
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
-- UART Runs at 57.6 Kbps
--
-- Version 1.4 - 21 Nov 2004 - John Kent
-- Changes to make compatible with Spartan3 starter kit version
-- Designed to run with a 50MHz clock input.
-- the VDU divides 50 MHz to generate a
-- 25 MHz VDU Pixel Clock and a 12.5 MHz CPU clock
-- Changed Monitor ROM signals to make it look like
-- a standard 2K memory block
-- Re-assigned I/O port assignments so it is possible to run KBUG9
--
-- Version 1.5 - 3rd February 2007 - John Kent
-- Changed VDU8 to use external clock divider
-- renamed miniUART to ACIA_6850
-- Memory decoding of ROM & IO now uses DAT
--
-- Version 1.6 - 7th Februaury 2007 - John Kent
-- Made ACIA Clock generator an external component
-- Added Generics to VDU and Keyboard
-- Changed decoding
--
-- Version 1.7 - 20th May 2007 - John Kent
-- Added 4 wait states to CF access
-- Removed DAT memory map control of ROM & IO
-- to allow for full use of RAM as a RAM disk.
-- Mapped in all 16 bits of the CF data bus.
--
-- Version 1.8 - 1st July 2007 - John Kent
-- Copied B5-X300 top level to B3 version.
--
-- Version 2.0 - 6th September 2008 - John Kent
-- added IDE interface for a CF card.
-- Used separate Clock DLL for generating clocks
--
-- Version 2.1 - 23rd Februaury 2008 - John Kent
-- Renamed Monitor ROM
--
-- Version 2.2 - 28th August 2010 - John Kent
-- Renamed ACIA_6850 to acia6850
-- Updated CPU & VDU component signal names & generics
-- Made peripheral bus interface a separate component
-- Made BED_SRAM a separate component
-- Made the LED flasher a separate component
-- Updated Header
--
--===========================================================================
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
 
entity System09 is
port(
clk_in : in Std_Logic; -- System Clock input
rst_n : in Std_logic; -- Master Reset input (active low)
LED : out Std_logic; -- Diagnostic LED Flasher
 
-- B3-SRAM Memory Interface signals
 
ram_csn : out Std_Logic;
ram_wrln : out Std_Logic;
ram_wrun : out Std_Logic;
ram_addr : out Std_Logic_Vector(16 downto 0);
ram_data : inout Std_Logic_Vector(15 downto 0);
 
-- End of B3-SRAM Memory Interface signals
 
-- B3-FPGA-CPU-IO Module signals
 
-- Asychronous Communications Interface Adapater signals (RS232 Serial Port) ($E00X)
acia_rxd : in Std_Logic;
acia_txd : out Std_Logic;
acia_rts_n : out Std_Logic;
acia_cts_n : in Std_Logic;
 
-- PS/2 Keyboard Interface ($E02X)
kb_clock : inout Std_logic;
kb_data : inout Std_Logic;
 
-- PS/2 Mouse interface
-- mouse_clock : in Std_Logic;
-- mouse_data : in Std_Logic;
 
-- Visual Display Unit output signals ($E03X)
vga_vsync : out Std_Logic;
vga_hsync : out Std_Logic;
vga_blue : out std_logic_vector(1 downto 0);
vga_green : out std_logic_vector(1 downto 0);
vga_red : out std_logic_vector(1 downto 0);
 
-- Buzzer
-- buzzer : out std_logic;
 
-- End of B3-FPGA-CPU-IO Module signals
 
-- Parallel Printer Port ($E0AX)
pp_data : out std_logic_vector(7 downto 0);
pp_stat : in std_logic_vector(7 downto 3);
pp_ctrl : out std_logic_vector(3 downto 0);
 
-- Peripheral Bus ($E100 - $E1FF)
pb_iord_n : out std_logic;
pb_iowr_n : out std_logic;
pb_addr : out std_logic_vector(2 downto 0);
pb_data : inout std_logic_vector(15 downto 0);
 
-- IDE Compact Flash ($E100 - $E13F)
ide_rst_n : out std_logic; -- ide pin 1
ide_cs0_n : out std_logic; -- ide pin 37
ide_cs1_n : out std_logic; -- ide pin 38
ide_dmarq : in std_logic; -- ide pin 21
ide_dmack_n : out std_logic; -- ide pin 29
ide_iordy : in std_logic; -- ide pin 27
ide_con_csel : out std_logic; -- ide pin 28
ide_intrq : in std_logic; -- ide pin 31
ide_iocs16_n : in std_logic; -- ide pin 32
ide_pdiag_n : in std_logic; -- ide pin 34
ide_dasp_n : out std_logic; -- ide pin 39
 
-- Dual port RAM interface bus
bus_clk : in std_logic;
bus_cs_n : in std_logic;
bus_rw : in std_logic;
bus_addr : in std_logic_vector(12 downto 0);
bus_data_in : in std_logic_vector(7 downto 0);
bus_data_out : out std_logic_vector(7 downto 0)
);
end System09;
 
-------------------------------------------------------------------------------
-- Architecture for System09
-------------------------------------------------------------------------------
architecture rtl of System09 is
-----------------------------------------------------------------------------
-- constants
-----------------------------------------------------------------------------
constant SYS_CLK_FREQ : integer := 50000000; -- FPGA System Clock
constant VGA_CLK_FREQ : integer := 25000000; -- VGA Pixel Clock
constant CPU_CLK_FREQ : integer := 12500000; -- CPU Clock
constant BAUD_RATE : integer := 57600; -- Baud Rate
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
 
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
 
-- System Clock
signal sys_clk : std_logic;
 
-- CPU Interface signals
signal cpu_rst : Std_Logic;
signal cpu_clk : Std_Logic;
signal cpu_rw : std_logic;
signal cpu_vma : std_logic;
signal cpu_halt : std_logic;
signal cpu_hold : std_logic;
signal cpu_firq : std_logic;
signal cpu_irq : std_logic;
signal cpu_nmi : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_data_in : std_logic_vector(7 downto 0);
signal cpu_data_out : std_logic_vector(7 downto 0);
 
-- B3 Static RAM ($0000 - $DFFF)
signal ram_cs : std_logic; -- memory chip select
signal ram_data_out : std_logic_vector(7 downto 0);
 
-- ACIA Console serial port ($E000 - $E00F)
signal acia_data_out : Std_Logic_Vector(7 downto 0);
signal acia_cs : Std_Logic;
signal acia_irq : Std_Logic;
signal acia_clk : Std_Logic;
 
-- PS/2 Keyboard interface ($E02X)
signal kbd_data_out : std_logic_vector(7 downto 0);
signal kbd_cs : std_logic;
signal kbd_irq : std_logic;
 
-- Visual Display Unit ($E03X)
signal vga_clk : std_logic;
signal vdu_cs : std_logic;
signal vdu_data_out : std_logic_vector(7 downto 0);
signal vga_red_o : std_logic;
signal vga_green_o : std_logic;
signal vga_blue_o : std_logic;
 
-- Timer ($E05X)
signal timer_data_out : std_logic_vector(7 downto 0);
signal timer_cs : std_logic;
signal timer_irq : std_logic;
 
-- Bus trap ($E06X)
signal trap_cs : std_logic;
signal trap_data_out : std_logic_vector(7 downto 0);
signal trap_irq : std_logic;
 
-- Trace ($E07X)
-- signal trace_cs : std_logic;
-- signal trace_data_out : std_logic_vector(7 downto 0);
-- signal trace_irq : std_logic;
 
-- Simple Parallel I/O port ($E0AX)
signal spp_data_out : std_logic_vector(7 downto 0);
signal spp_cs : std_logic;
 
-- Peripheral Bus ($E1XX)
signal pb_cs : std_logic;
signal pb_data_out : std_logic_vector(7 downto 0);
signal pb_hold : std_logic;
 
-- Peripheral Bus Chip Selects ($E1XX)
signal ide_cs : std_logic; -- IDE CF interface ($E100 - $E13F)
signal ether_cs : std_logic; -- Ethernet interface ($E140 - $E17F)
signal slot1_cs : std_logic; -- Expansion slot1 ($E180 - $E1BF)
signal slot2_cs : std_logic; -- Expansion slot 2 ($E1C0 - $E1FF)
 
-- Dual Port RAM for Bus Interfacing ($E200 - $E7FF)
signal dpr_data_out : std_logic_vector(7 downto 0);
signal dpr_cs : std_logic;
signal dpr_wr : std_logic;
 
-- External Bus Interface
signal bus_iclk : std_logic;
signal bus_gclk : std_logic;
signal bus_cs : std_logic;
signal bus_wr : std_logic;
 
-- Monitor ROM ($F800 - $FFFF)
signal rom_data_out : Std_Logic_Vector(7 downto 0);
signal rom_cs : std_logic;
 
-- Dynamic Address Translation ($FFF0 - $FFFF)
signal dat_cs : std_logic;
signal dat_addr : std_logic_vector(7 downto 0);
 
-----------------------------------------------------------------
--
-- Clock generator
--
-----------------------------------------------------------------
 
component clock_div
port(
clk_in : in std_Logic; -- System Clock input
sys_clk : out std_logic; -- System Clock Out (1/1)
vga_clk : out std_logic; -- VGA Pixel Clock Out (1/2)
cpu_clk : out std_logic -- CPU Clock Out (1/4)
);
end component;
 
-----------------------------------------------------------------
--
-- LED Flasher
--
-----------------------------------------------------------------
--===========================================================================----
--
-- S Y N T H E Z I A B L E System09 - SOC.
--
-- www.OpenCores.Org - September 2003
-- This core adheres to the GNU public license
--
-- File name : System09.vhd
--
-- Purpose : Top level file for 6809 compatible system on a chip
-- Designed with Xilinx XC2S200 Spartan 2+ FPGA.
-- Implemented With BurchED B3 FPGA board,
-- B3-SRAM module and B3-FPGA-CPU-IO module
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
-- ieee.std_logic_arith
-- ieee.numeric_std
--
-- Uses :
-- cpu09 (cpu09.vhd) CPU core
-- mon_rom (sys09bug_rom2k_b4.vhd) Monitor ROM
-- dat_ram (datram.vhd) Dynamic Address Translation
-- acia_6850 (ACIA_6850.vhd) ACIA / MiniUART
-- (ACIA_RX.vhd)
-- (ACIA_TX.vhd)
-- ACIA_Clock (ACIA_Clock.vhd) ACIA Baud Clock Divider
-- keyboard (keyboard.vhd) PS/2 Keyboard Interface
-- vdu8 (vdu8.vhd) 80 x 25 Video Display
-- timer (timer.vhd) Timer module
-- trap (trap.vhd) Bus Trap interrupt
-- ioport (ioport.vhd) Parallel I/O port.
--
-- Author : John E. Kent
-- dilbert57@opencores.org
-- Memory Map :
--
-- $E000 - ACIA (SWTPc)
-- $E010 - Reserved for FD1771 FDC (SWTPc)
-- $E020 - Keyboard
-- $E030 - VDU
-- $E040 - Compact Flash
-- $E050 - Timer
-- $E060 - Bus trap
-- $E070 - Parallel I/O
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
-- $E0A0
-- $E0B0
-- $E0C0 - Trace logic
--
--===========================================================================----
--
-- Revision History:
--===========================================================================--
-- Version 0.1 - 20 March 2003
-- Version 0.2 - 30 March 2003
-- Version 0.3 - 29 April 2003
-- Version 0.4 - 29 June 2003
--
-- Version 0.5 - 19 July 2003
-- prints out "Hello World"
--
-- Version 0.6 - 5 September 2003
-- Runs SBUG
--
-- Version 1.0- 6 Sep 2003 - John Kent
-- Inverted SysClk
-- Initial release to Open Cores
--
-- Version 1.1 - 17 Jan 2004 - John Kent
-- Updated miniUart.
--
-- Version 1.2 - 25 Jan 2004 - John Kent
-- removed signals "test_alu" and "test_cc"
-- Trap hardware re-instated.
--
-- Version 1.3 - 11 Feb 2004 - John Kent
-- Designed forked off to produce System09_VDU
-- Added VDU component
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
-- UART Runs at 57.6 Kbps
--
-- Version 1.4 - 21 Nov 2004 - John Kent
-- Changes to make compatible with Spartan3 starter kit version
-- Designed to run with a 50MHz clock input.
-- the VDU divides 50 MHz to generate a
-- 25 MHz VDU Pixel Clock and a 12.5 MHz CPU clock
-- Changed Monitor ROM signals to make it look like
-- a standard 2K memory block
-- Re-assigned I/O port assignments so it is possible to run KBUG9
-- $E000 - ACIA
-- $E010 - Keyboard
-- $E020 - VDU
-- $E030 - Compact Flash
-- $E040 - Timer
-- $E050 - Bus trap
-- $E060 - Parallel I/O
--
-- Version 1.5 - 3rd February 2007 - John Kent
-- Changed VDU8 to use external clock divider
-- renamed miniUART to ACIA_6850
-- Memory decoding of ROM & IO now uses DAT
--
-- Version 1.6 - 7th Februaury 2007 - John Kent
-- Made ACIA Clock generator an external component
-- Added Generics to VDU and Keyboard
-- Changed decoding
--
-- Version 1.7 - 20th May 2007 - John Kent
-- Added 4 wait states to CF access
-- Removed DAT memory map control of ROM & IO
-- to allow for full use of RAM as a RAM disk.
-- Mapped in all 16 bits of the CF data bus.
--
-- Version 1.8 - 1st July 2007 - John Kent
-- Copied B5-X300 top level to B3 version.
--
--===========================================================================
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
 
component flasher
entity System09 is
port(
SysClk : in Std_Logic; -- System Clock input
Reset_n : in Std_logic; -- Master Reset input (active low)
LED : out std_logic; -- Diagnostic LED Flasher
 
-- Memory Interface signals
ram_csn : out Std_Logic;
ram_wrln : out Std_Logic;
ram_wrun : out Std_Logic;
ram_addr : out Std_Logic_Vector(16 downto 0);
ram_data : inout Std_Logic_Vector(15 downto 0);
 
-- Stuff on the peripheral board
 
-- PS/2 Keyboard
kb_clock : inout Std_logic;
kb_data : inout Std_Logic;
 
-- PS/2 Mouse interface
-- mouse_clock : in Std_Logic;
-- mouse_data : in Std_Logic;
 
-- Uart Interface
rxbit : in Std_Logic;
txbit : out Std_Logic;
rts_n : out Std_Logic;
cts_n : in Std_Logic;
 
-- CRTC output signals
v_drive : out Std_Logic;
h_drive : out Std_Logic;
blue_lo : out std_logic;
blue_hi : out std_logic;
green_lo : out std_logic;
green_hi : out std_logic;
red_lo : out std_logic;
red_hi : out std_logic;
-- buzzer : out std_logic;
 
-- Compact Flash
-- cf_rst_n : out std_logic;
-- cf_cs0_n : out std_logic;
-- cf_cs1_n : out std_logic;
-- cf_rd_n : out std_logic;
-- cf_wr_n : out std_logic;
-- cf_cs16_n : out std_logic;
-- cf_a : out std_logic_vector(2 downto 0);
-- cf_d : inout std_logic_vector(15 downto 0);
-- cf_d : inout std_logic_vector(7 downto 0);
 
-- Parallel I/O port
porta : inout std_logic_vector(7 downto 0);
portb : inout std_logic_vector(7 downto 0);
 
-- CPU bus
bus_clk : out std_logic;
bus_reset : out std_logic;
bus_rw : out std_logic;
bus_csn : out std_logic;
bus_addr : out std_logic_vector(19 downto 0);
bus_data : inout std_logic_vector(7 downto 0);
 
-- timer
timer_out : out std_logic
);
end System09;
 
-------------------------------------------------------------------------------
-- Architecture for System09
-------------------------------------------------------------------------------
architecture rtl of System09 is
-----------------------------------------------------------------------------
-- constants
-----------------------------------------------------------------------------
constant SYS_Clock_Frequency : integer := 50000000; -- FPGA System Clock
constant PIX_Clock_Frequency : integer := 25000000; -- VGA Pixel Clock
constant CPU_Clock_Frequency : integer := 12500000; -- CPU Clock
constant BAUD_Rate : integer := 57600; -- Baud Rate
constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16;
 
type hold_state_type is ( hold_release_state, hold_request_state );
 
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- Monitor ROM
signal rom_data_out : Std_Logic_Vector(7 downto 0);
signal rom_cs : std_logic;
 
-- UART Interface signals
signal uart_data_out : Std_Logic_Vector(7 downto 0);
signal uart_cs : Std_Logic;
signal uart_irq : Std_Logic;
signal uart_clk : Std_Logic;
signal DCD_n : Std_Logic;
 
-- timer
signal timer_data_out : std_logic_vector(7 downto 0);
signal timer_cs : std_logic;
signal timer_irq : std_logic;
 
-- trap
signal trap_cs : std_logic;
signal trap_data_out : std_logic_vector(7 downto 0);
signal trap_irq : std_logic;
 
 
-- trace
-- signal trace_cs : std_logic;
-- signal trace_data_out : std_logic_vector(7 downto 0);
-- signal trace_irq : std_logic;
-- signal bank_cs : std_logic;
-- signal bank_data_out : std_logic_vector(7 downto 0);
 
-- Parallel I/O port
signal ioport_data_out : std_logic_vector(7 downto 0);
signal ioport_cs : std_logic;
 
-- compact flash port
-- signal cf_data_out : std_logic_vector(7 downto 0);
-- signal cf_cs : std_logic;
-- signal cf_rd : std_logic;
-- signal cf_wr : std_logic;
-- signal cf_hold : std_logic;
-- signal cf_release : std_logic;
-- signal cf_count : std_logic_vector(3 downto 0);
-- signal cf_hold_state : hold_state_type;
 
-- keyboard port
signal keyboard_data_out : std_logic_vector(7 downto 0);
signal keyboard_cs : std_logic;
signal keyboard_irq : std_logic;
 
-- RAM
signal ram_cs : std_logic; -- memory chip select
signal ram_wrl : std_logic; -- memory write lower
signal ram_wru : std_logic; -- memory write upper
signal ram_data_out : std_logic_vector(7 downto 0);
 
-- CPU Interface signals
signal cpu_reset : Std_Logic;
signal cpu_clk : Std_Logic;
signal cpu_rw : std_logic;
signal cpu_vma : std_logic;
signal cpu_halt : std_logic;
signal cpu_hold : std_logic;
signal cpu_firq : std_logic;
signal cpu_irq : std_logic;
signal cpu_nmi : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_data_in : std_logic_vector(7 downto 0);
signal cpu_data_out : std_logic_vector(7 downto 0);
 
-- Dynamic address translation
signal dat_cs : std_logic;
signal dat_addr : std_logic_vector(7 downto 0);
 
-- Video Display Unit
signal pix_clk : std_logic;
signal vdu_cs : std_logic;
signal vdu_data_out : std_logic_vector(7 downto 0);
signal vga_red : std_logic;
signal vga_green : std_logic;
signal vga_blue : std_logic;
 
-- external bus I/O
signal bus_cs : std_logic;
 
-- Flashing Led test signals
signal countL : std_logic_vector(23 downto 0);
signal clock_div : std_logic_vector(1 downto 0);
 
-----------------------------------------------------------------
--
-- CPU09 CPU core
--
-----------------------------------------------------------------
 
component cpu09
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
halt: in std_logic;
hold: in std_logic;
irq: in std_logic;
nmi: in std_logic;
firq: in std_logic
);
end component;
 
 
----------------------------------------
--
-- SBUG Block RAM Monitor ROM
--
----------------------------------------
component mon_rom
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (10 downto 0);
wdata : in std_logic_vector (7 downto 0);
rdata : out std_logic_vector (7 downto 0)
);
end component;
 
 
----------------------------------------
--
-- Dynamic Address Translation Registers
--
----------------------------------------
component dat_ram
port (
clk : in std_logic; -- Clock input
rst : in std_logic; -- Reset input (active high)
LED : out Std_Logic -- LED output
clk: in std_logic;
rst: in std_logic;
cs: in std_logic;
rw: in std_logic;
addr_lo: in std_logic_vector(3 downto 0);
addr_hi: in std_logic_vector(3 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0)
);
end component;
 
-----------------------------------------------------------------
--
-- 6850 ACIA/UART
--
-----------------------------------------------------------------
 
component ACIA_6850
port (
clk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input (active high)
cs : in Std_Logic; -- miniUART Chip Select
rw : in Std_Logic; -- Read / Not Write
irq : out Std_Logic; -- Interrupt
Addr : in Std_Logic; -- Register Select
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
RxC : in Std_Logic; -- Receive Baud Clock
TxC : in Std_Logic; -- Transmit Baud Clock
RxD : in Std_Logic; -- Receive Data
TxD : out Std_Logic; -- Transmit Data
DCD_n : in Std_Logic; -- Data Carrier Detect
CTS_n : in Std_Logic; -- Clear To Send
RTS_n : out Std_Logic ); -- Request To send
end component;
 
-----------------------------------------------------------------
--
-- ACIA Clock divider
--
-----------------------------------------------------------------
 
component ACIA_Clock
generic (
SYS_Clock_Frequency : integer := SYS_Clock_Frequency;
ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
);
port (
clk : in Std_Logic; -- System Clock Input
ACIA_clk : out Std_logic -- ACIA Clock output
);
end component;
 
 
-----------------------------------------------------------------
--
-- 6809 Compatible CPU core
--
-----------------------------------------------------------------
 
component cpu09
port (
clk : in std_logic;
rst : in std_logic;
rw : out std_logic;
vma : out std_logic;
addr : out std_logic_vector(15 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
halt : in std_logic;
hold : in std_logic;
irq : in std_logic;
nmi : in std_logic;
firq : in std_logic
);
end component;
end component;
 
-----------------------------------------------------------------
--
-- Dynamic Address Translation Registers ($FFF0 - $FFFF)
--
-----------------------------------------------------------------
component dat_ram
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr_lo : in std_logic_vector(3 downto 0);
addr_hi : in std_logic_vector(3 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end component;
 
-------------------------------------------------
--
-- Sys09Bug Block RAM Monitor ROM ($F800-$FFFF)
--
-------------------------------------------------
component sys09bug_F800
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector (10 downto 0);
rw : in std_logic;
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0)
);
end component;
 
-----------------------------------------------------------------
--
-- 6850 ACIA RS232 Interface ($E000 - $E00F)
--
-----------------------------------------------------------------
 
component acia6850
port (
clk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input (active high)
cs : in Std_Logic; -- miniUART Chip Select
rw : in Std_Logic; -- Read / Not Write
irq : out Std_Logic; -- Interrupt
addr : in Std_Logic; -- Register Select
data_in : in Std_Logic_Vector(7 downto 0); -- Data Bus In
data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
RxC : in Std_Logic; -- Receive Baud Clock
TxC : in Std_Logic; -- Transmit Baud Clock
RxD : in Std_Logic; -- Receive Data
TxD : out Std_Logic; -- Transmit Data
DCD_n : in Std_Logic; -- Data Carrier Detect
CTS_n : in Std_Logic; -- Clear To Send
RTS_n : out Std_Logic ); -- Request To send
end component;
 
-----------------------------------------------------------------
--
-- ACIA Clock divider
--
-----------------------------------------------------------------
 
component ACIA_Clock
generic (
SYS_CLK_FREQ : integer := SYS_CLK_FREQ;
ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
);
port (
clk : in Std_Logic; -- System Clock Input
acia_clk : out Std_logic -- ACIA Clock output
);
end component;
 
----------------------------------------
--
-- PS/2 Keyboard ($E020 - $E02F)
--
----------------------------------------
 
component keyboard
generic(
KBD_CLK_FREQ : integer := CPU_CLK_FREQ
);
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic;
kbd_clk : inout std_logic;
kbd_data : inout std_logic
);
end component;
 
----------------------------------------
--
-- Video Display Unit. ($E030 - $E03F)
--
----------------------------------------
component vdu8_mono
generic(
VGA_CLK_FREQ : integer := VGA_CLK_FREQ; -- HZ
VGA_HOR_CHARS : integer := 80; -- CHARACTERS 25.6us
VGA_HOR_CHAR_PIXELS : integer := 8; -- PIXELS 0.32us
VGA_HOR_FRONT_PORCH : integer := 16; -- PIXELS 0.64us
VGA_HOR_SYNC : integer := 96; -- PIXELS 3.84us
VGA_HOR_BACK_PORCH : integer := 48; -- PIXELS 1.92us
VGA_VER_CHARS : integer := 25; -- CHARACTERS 12.8ms
VGA_VER_CHAR_LINES : integer := 16; -- LINES 0.512ms
VGA_VER_FRONT_PORCH : integer := 10; -- LINES 0.320ms
VGA_VER_SYNC : integer := 2; -- LINES 0.064ms
VGA_VER_BACK_PORCH : integer := 34 -- LINES 1.088ms
);
port(
-- control register interface
vdu_clk : in std_logic; -- CPU Clock - 12.5MHz
vdu_rst : in std_logic;
vdu_cs : in std_logic;
vdu_addr : in std_logic_vector(2 downto 0);
vdu_rw : in std_logic;
vdu_data_in : in std_logic_vector(7 downto 0);
vdu_data_out : out std_logic_vector(7 downto 0);
 
-- vga port connections
vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
vga_red_o : out std_logic;
vga_green_o : out std_logic;
vga_blue_o : out std_logic;
vga_hsync_o : out std_logic;
vga_vsync_o : out std_logic
);
end component;
 
----------------------------------------
--
-- Timer module ($E050 - $E05F)
--
----------------------------------------
 
component timer
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic;
rw : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic
);
end component;
 
------------------------------------------------------------
--
-- Bus Trap / Hardware Breakpoint ($E060 - $E06F)
--
------------------------------------------------------------
 
component trap
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
vma : in std_logic;
addr : in std_logic_vector(15 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic
);
end component;
 
------------------------------------------------------------
--
-- Bus Trace logic ($E070 - $E07F)
--
------------------------------------------------------------
--component trace is
-- port (
-- clk : in std_logic;
-- rst : in std_logic;
-- rs : in std_logic; -- register select
-- bs : in std_logic; -- bank select
-- rw : in std_logic;
-- vma : in std_logic;
-- addr : in std_logic_vector(15 downto 0);
-- data_in : in std_logic_vector(7 downto 0);
-- reg_data_out : out std_logic_vector(7 downto 0);
-- buff_data_out : out std_logic_vector(7 downto 0);
-- cpu_data_in : in std_logic_vector(7 downto 0);
-- irq : out std_logic
-- );
--end component;
 
----------------------------------------
--
-- Simple Parallel Port ($E0A0 - $E0AF)
--
----------------------------------------
component spp
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic_vector(2 downto 0);
rw : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic;
hold : out std_logic;
spp_data : out std_logic_vector(7 downto 0);
spp_stat : in std_logic_vector(7 downto 3);
spp_ctrl : out std_logic_vector(3 downto 0)
);
end component;
 
------------------------------------------------------------
--
-- Peripheral Bus interface (IDE CF) ($E100 - $E1FF)
--
------------------------------------------------------------
----------------------------------------
--
-- Timer module
--
----------------------------------------
 
component peripheral_bus is
component timer
port (
--
-- CPU Interface signals
--
clk : in std_logic; -- System Clock
rst : in std_logic; -- Reset input (active high)
cs : in std_logic; -- Peripheral Bus Chip Select
addr : in std_logic_vector(7 downto 0); -- Register Select
rw : in std_logic; -- Read / Not Write
data_in : in std_logic_vector(7 downto 0); -- Data Bus In
data_out : out std_logic_vector(7 downto 0); -- Data Bus Out
hold : out std_logic; -- Hold bus cycle output
--
-- Peripheral Bus Interface Signals
-- IO + ($00 - $FF)
-- (for compatibility with XSA-3S1000 / XST 3.0)
--
pb_rd_n : out std_logic; -- ide pin 25
pb_wr_n : out std_logic; -- ide pin 23
pb_addr : out std_logic_vector( 4 downto 0);
pb_data : inout std_logic_vector(15 downto 0);
 
-- Peripheral chip selects on Peripheral Bus
ide_cs : out std_logic; -- IDE / CF interface ($00 - $3F)
eth_cs : out std_logic; -- Ethernet interface ($40 - $7F)
sl1_cs : out std_logic; -- Expansion slot 1 ($80 - $BF)
sl2_cs : out std_logic -- Expansion slot 2 ($C0 - $FF)
);
end component;
 
------------------------------------------------------------
--
-- External Bus interface Dual port RAM ($E200 - $EFFF)
--
------------------------------------------------------------
 
component RAMB4_S8_S8
port (
RSTA: IN std_logic;
CLKA: IN std_logic;
ENA: IN std_logic;
WEA: IN std_logic;
ADDRA: IN std_logic_vector(8 downto 0);
DIA: IN std_logic_vector(7 downto 0);
DOA: OUT std_logic_vector(7 downto 0);
RSTB: IN std_logic;
CLKB: IN std_logic;
ENB: IN std_logic;
WEB: IN std_logic;
ADDRB: IN std_logic_vector(8 downto 0);
DIB: IN std_logic_vector(7 downto 0);
DOB: OUT std_logic_vector(7 downto 0)
);
end component;
 
component IBUF
port (
I : IN std_logic;
O : OUT std_logic
);
end component;
 
component BUFG
port (
I : IN std_logic;
O : OUT std_logic
);
end component;
 
------------------------------------------------------------
--
-- BED SRAM interface ($0000 - $DFFF)
--
------------------------------------------------------------
component BED_SRAM
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic;
timer_in : in std_logic;
timer_out : out std_logic
);
end component;
 
------------------------------------------------------------
--
-- Bus Trap logic
--
------------------------------------------------------------
 
component trap
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
vma : in std_logic;
addr : in std_logic_vector(15 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic
);
end component;
 
------------------------------------------------------------
--
-- Bus Trace logic
--
------------------------------------------------------------
--component trace is
-- port (
-- clk : in std_logic;
-- rst : in std_logic;
-- rs : in std_logic; -- register select
-- bs : in std_logic; -- bank select
-- rw : in std_logic;
-- vma : in std_logic;
-- addr : in std_logic_vector(15 downto 0);
-- data_in : in std_logic_vector(7 downto 0);
-- reg_data_out : out std_logic_vector(7 downto 0);
-- buff_data_out : out std_logic_vector(7 downto 0);
-- cpu_data_in : in std_logic_vector(7 downto 0);
-- irq : out std_logic
-- );
--end component;
 
----------------------------------------
--
-- Dual 8 bit Parallel I/O module
--
----------------------------------------
component ioport
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(1 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
porta_io : inout std_logic_vector(7 downto 0);
portb_io : inout std_logic_vector(7 downto 0)
);
end component;
 
----------------------------------------
--
-- PS/2 Keyboard
--
----------------------------------------
 
component keyboard
generic(
KBD_Clock_Frequency : integer := CPU_Clock_Frequency
);
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic;
kbd_clk : inout std_logic;
kbd_data : inout std_logic
);
end component;
 
----------------------------------------
--
-- Video Display Unit.
--
----------------------------------------
component vdu8_mono
generic(
VDU_CLOCK_FREQUENCY : integer := CPU_Clock_Frequency; -- HZ
VGA_CLOCK_FREQUENCY : integer := PIX_Clock_Frequency; -- HZ
VGA_HOR_CHARS : integer := 80; -- CHARACTERS
VGA_VER_CHARS : integer := 25; -- CHARACTERS
VGA_PIXELS_PER_CHAR : integer := 8; -- PIXELS
VGA_LINES_PER_CHAR : integer := 16; -- LINES
VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS
VGA_HOR_SYNC : integer := 96; -- PIXELS
VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS
VGA_VER_BACK_PORCH : integer := 13; -- LINES
VGA_VER_SYNC : integer := 1; -- LINES
VGA_VER_FRONT_PORCH : integer := 36 -- LINES
);
port(
-- control register interface
vdu_clk : in std_logic; -- CPU Clock - 12.5MHz
vdu_rst : in std_logic;
vdu_cs : in std_logic;
vdu_rw : in std_logic;
vdu_addr : in std_logic_vector(2 downto 0);
vdu_data_in : in std_logic_vector(7 downto 0);
vdu_data_out : out std_logic_vector(7 downto 0);
 
-- vga port connections
vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
vga_red_o : out std_logic;
vga_green_o : out std_logic;
vga_blue_o : out std_logic;
vga_hsync_o : out std_logic;
vga_vsync_o : out std_logic
);
end component;
 
 
component BUFG
port (
--
-- CPU Interface signals
--
clk : in std_logic; -- System Clock (twice the CPU clock)
rst : in std_logic; -- Reset input (active high)
cs : in std_logic; -- RAM Chip Select
addr : in std_logic_vector(17 downto 0); -- RAM address bus
rw : in std_logic; -- Read / Not Write
data_in : in std_logic_vector(7 downto 0); -- Data Bus In
data_out : out std_logic_vector(7 downto 0); -- Data Bus Out
--
-- B3_SRAM Interface Signals
--
ram_csn : out Std_Logic;
ram_wrln : out Std_Logic;
ram_wrun : out Std_Logic;
ram_addr : out Std_Logic_Vector(16 downto 0);
ram_data : inout Std_Logic_Vector(15 downto 0)
 
);
end component;
 
begin
-----------------------------------------------------------------------------
-- Instantiation of internal components
-----------------------------------------------------------------------------
----------------------------------------
--
-- Clock generator
--
----------------------------------------
my_clock_div: clock_div port map (
clk_in => clk_in, -- Clock input
sys_clk => sys_clk, -- System Clock Out (1/1)
vga_clk => vga_clk, -- VGA Pixel Clock Out (1/2)
cpu_clk => cpu_clk -- CPU Clock Out (1/4)
);
 
-----------------------------------------
--
-- LED Flasher
--
-----------------------------------------
i: in std_logic;
o: out std_logic
);
end component;
 
my_LED_flasher : flasher port map (
clk => cpu_clk,
rst => cpu_rst,
LED => LED
begin
-----------------------------------------------------------------------------
-- Instantiation of internal components
-----------------------------------------------------------------------------
 
----------------------------------------
--
-- CPU09 CPU Core
--
----------------------------------------
my_cpu : cpu09 port map (
clk => cpu_clk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
halt => cpu_halt,
hold => cpu_hold,
irq => cpu_irq,
nmi => cpu_nmi,
firq => cpu_firq
);
 
----------------------------------------
--
-- CPU09 CPU Core
--
----------------------------------------
my_cpu : cpu09 port map (
clk => cpu_clk,
rst => cpu_rst,
rw => cpu_rw,
vma => cpu_vma,
addr => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
halt => cpu_halt,
hold => cpu_hold,
irq => cpu_irq,
nmi => cpu_nmi,
firq => cpu_firq
);
 
----------------------------------------
--
-- Dynamic Address Translation ($FFF0-$FFFF)
--
----------------------------------------
my_dat : dat_ram port map (
clk => cpu_clk,
rst => cpu_rst,
cs => dat_cs,
rw => cpu_rw,
addr_hi => cpu_addr(15 downto 12),
addr_lo => cpu_addr(3 downto 0),
data_in => cpu_data_out,
data_out => dat_addr(7 downto 0)
);
 
----------------------------------------
--
-- SYS09BUG Monitor ROM ($F800-$FFFF)
--
----------------------------------------
my_rom : SYS09BUG_F800 port map (
clk => cpu_clk,
rst => cpu_rst,
cs => rom_cs,
rw => '1',
addr => cpu_addr(10 downto 0),
data_in => cpu_data_out,
data_out => rom_data_out
);
 
----------------------------------------
--
-- ACIA RS232 Serial interface ($E000-$E00F)
--
----------------------------------------
my_ACIA : acia6850 port map (
--
-- CPU Interface
--
clk => cpu_clk,
rst => cpu_rst,
cs => acia_cs,
rw => cpu_rw,
irq => acia_irq,
addr => cpu_addr(0),
data_in => cpu_data_out,
data_out => acia_data_out,
--
-- RS232 Interface
--
RxC => acia_clk,
TxC => acia_clk,
RxD => acia_rxd,
TxD => acia_txd,
DCD_n => '0',
CTS_n => acia_cts_n,
RTS_n => acia_rts_n
);
 
----------------------------------------
--
-- ACIA Baud Clock
--
----------------------------------------
my_ACIA_Clock : ACIA_Clock
generic map(
SYS_CLK_FREQ => SYS_CLK_FREQ,
ACIA_CLK_FREQ => ACIA_CLK_FREQ
)
port map(
clk => sys_clk,
acia_clk => acia_clk
);
 
----------------------------------------
--
-- PS/2 Keyboard Interface ($E020-$E02F)
--
----------------------------------------
my_keyboard : keyboard
generic map (
KBD_CLK_FREQ => CPU_CLK_FREQ
)
port map(
clk => cpu_clk,
rst => cpu_rst,
cs => kbd_cs,
rw => cpu_rw,
addr => cpu_addr(0),
data_in => cpu_data_out(7 downto 0),
data_out => kbd_data_out(7 downto 0),
irq => kbd_irq,
kbd_clk => kb_clock,
kbd_data => kb_data
);
 
------------------------------------------------
--
-- Video Display Unit instantiation ($E030-$E03F)
--
-------------------------------------------------
my_vdu : vdu8_mono
generic map(
VGA_CLK_FREQ => VGA_CLK_FREQ, -- 25MHZ
VGA_HOR_CHARS => 80, -- CHARACTERS 25.6us
VGA_HOR_CHAR_PIXELS => 8, -- PIXELS 0.32us
VGA_HOR_FRONT_PORCH => 16, -- PIXELS 0.64us
VGA_HOR_SYNC => 96, -- PIXELS 3.84us
VGA_HOR_BACK_PORCH => 48, -- PIXELS 1.92us
VGA_VER_CHARS => 25, -- CHARACTERS 12.8ms
VGA_VER_CHAR_LINES => 16, -- LINES 0.512ms
VGA_VER_FRONT_PORCH => 10, -- LINES 0.320ms
VGA_VER_SYNC => 2, -- LINES 0.064ms
VGA_VER_BACK_PORCH => 34 -- LINES 1.088ms
)
port map(
 
-- CPU Control Registers interface
vdu_clk => cpu_clk, -- 12.5 MHz System Clock in
vdu_rst => cpu_rst,
vdu_cs => vdu_cs,
vdu_rw => cpu_rw,
vdu_addr => cpu_addr(2 downto 0),
vdu_data_in => cpu_data_out,
vdu_data_out => vdu_data_out,
 
-- vga port connections
vga_clk => vga_clk, -- 25 MHz VDU pixel clock
vga_red_o => vga_red_o,
vga_green_o => vga_green_o,
vga_blue_o => vga_blue_o,
vga_hsync_o => vga_hsync,
vga_vsync_o => vga_vsync
);
 
----------------------------------------
--
-- Timer Module
--
----------------------------------------
my_timer : timer port map (
clk => cpu_clk,
rst => cpu_rst,
cs => timer_cs,
rw => cpu_rw,
addr => cpu_addr(0),
data_in => cpu_data_out,
data_out => timer_data_out,
irq => timer_irq
);
 
----------------------------------------
--
-- Bus Trap Interrupt logic
--
----------------------------------------
my_trap : trap port map (
clk => cpu_clk,
rst => cpu_rst,
cs => trap_cs,
rw => cpu_rw,
vma => cpu_vma,
addr => cpu_addr,
data_in => cpu_data_out,
data_out => trap_data_out,
irq => trap_irq
);
 
----------------------------------------
--
-- Bus Trace logic
--
----------------------------------------
--my_trace : trace port map (
-- clk => sys_clk,
-- rst => cpu_rst,
-- rs => trace_cs,
-- bs => bank_cs,
-- rw => cpu_rw,
-- vma => cpu_vma,
-- addr => cpu_addr,
-- data_in => cpu_data_out,
-- reg_data_out => trace_data_out,
-- buff_data_out => bank_data_out,
-- cpu_data_in => cpu_data_in,
-- irq => trace_irq
-- );
 
----------------------------------------
--
-- Simple Parallel Port
--
----------------------------------------
my_spp : spp port map (
clk => cpu_clk,
rst => cpu_rst,
cs => spp_cs,
rw => cpu_rw,
addr => cpu_addr(2 downto 0),
data_in => cpu_data_out,
data_out => spp_data_out,
spp_data => pp_data,
spp_stat => pp_stat,
spp_ctrl => pp_ctrl,
hold => open,
irq => open
);
 
------------------------------------------------
--
-- 16 bit Peripheral Bus interface ($E100-$E1FF)
--
------------------------------------------------
my_pb : peripheral_bus port map (
--
-- CPU Interface signals
--
----------------------------------------
--
-- SBUG / KBUG / SYS09BUG Monitor ROM
--
----------------------------------------
my_rom : mon_rom port map (
clk => cpu_clk,
rst => cpu_reset,
cs => rom_cs,
rw => '1',
addr => cpu_addr(10 downto 0),
wdata => cpu_data_out,
rdata => rom_data_out
);
 
----------------------------------------
--
-- Dynamic Address Translation Registers
--
----------------------------------------
my_dat : dat_ram port map (
clk => cpu_clk,
rst => cpu_reset,
cs => dat_cs,
rw => cpu_rw,
addr_hi => cpu_addr(15 downto 12),
addr_lo => cpu_addr(3 downto 0),
data_in => cpu_data_out,
data_out => dat_addr(7 downto 0)
);
 
----------------------------------------
--
-- ACIA/UART Serial interface
--
----------------------------------------
my_ACIA : ACIA_6850 port map (
clk => cpu_clk,
rst => cpu_reset,
cs => uart_cs,
rw => cpu_rw,
irq => uart_irq,
Addr => cpu_addr(0),
Datain => cpu_data_out,
DataOut => uart_data_out,
RxC => uart_clk,
TxC => uart_clk,
RxD => rxbit,
TxD => txbit,
DCD_n => dcd_n,
CTS_n => cts_n,
RTS_n => rts_n
);
 
----------------------------------------
--
-- ACIA Clock
--
----------------------------------------
my_ACIA_Clock : ACIA_Clock
generic map(
SYS_Clock_Frequency => SYS_Clock_Frequency,
ACIA_Clock_Frequency => ACIA_Clock_Frequency
)
port map(
clk => SysClk,
acia_clk => uart_clk
);
 
----------------------------------------
--
-- PS/2 Keyboard Interface
--
----------------------------------------
my_keyboard : keyboard
generic map (
KBD_Clock_Frequency => CPU_Clock_frequency
)
port map(
clk => cpu_clk,
rst => cpu_reset,
cs => keyboard_cs,
rw => cpu_rw,
addr => cpu_addr(0),
data_in => cpu_data_out(7 downto 0),
data_out => keyboard_data_out(7 downto 0),
irq => keyboard_irq,
kbd_clk => kb_clock,
kbd_data => kb_data
);
 
----------------------------------------
--
-- Video Display Unit instantiation
--
----------------------------------------
my_vdu : vdu8_mono
generic map(
VDU_CLOCK_FREQUENCY => CPU_Clock_Frequency, -- HZ
VGA_CLOCK_FREQUENCY => PIX_Clock_Frequency, -- HZ
VGA_HOR_CHARS => 80, -- CHARACTERS
VGA_VER_CHARS => 25, -- CHARACTERS
VGA_PIXELS_PER_CHAR => 8, -- PIXELS
VGA_LINES_PER_CHAR => 16, -- LINES
VGA_HOR_BACK_PORCH => 40, -- PIXELS
VGA_HOR_SYNC => 96, -- PIXELS
VGA_HOR_FRONT_PORCH => 24, -- PIXELS
VGA_VER_BACK_PORCH => 13, -- LINES
VGA_VER_SYNC => 1, -- LINES
VGA_VER_FRONT_PORCH => 36 -- LINES
)
port map(
 
-- Control Registers
vdu_clk => cpu_clk, -- 12.5 MHz System Clock in
vdu_rst => cpu_reset,
vdu_cs => vdu_cs,
vdu_rw => cpu_rw,
vdu_addr => cpu_addr(2 downto 0),
vdu_data_in => cpu_data_out,
vdu_data_out => vdu_data_out,
 
-- vga port connections
vga_clk => pix_clk, -- 25 MHz VDU pixel clock
vga_red_o => vga_red,
vga_green_o => vga_green,
vga_blue_o => vga_blue,
vga_hsync_o => h_drive,
vga_vsync_o => v_drive
);
 
----------------------------------------
--
-- Timer Module
--
----------------------------------------
my_timer : timer port map (
clk => cpu_clk,
rst => cpu_rst,
cs => pb_cs,
addr => cpu_addr(7 downto 0),
rst => cpu_reset,
cs => timer_cs,
rw => cpu_rw,
addr => cpu_addr(0),
data_in => cpu_data_out,
data_out => timer_data_out,
irq => timer_irq,
timer_in => CountL(5),
timer_out => timer_out
);
 
----------------------------------------
--
-- Bus Trap Interrupt logic
--
----------------------------------------
my_trap : trap port map (
clk => cpu_clk,
rst => cpu_reset,
cs => trap_cs,
rw => cpu_rw,
vma => cpu_vma,
addr => cpu_addr,
data_in => cpu_data_out,
data_out => trap_data_out,
irq => trap_irq
);
 
----------------------------------------
--
-- Bus Trace logic
--
----------------------------------------
--my_trace : trace port map (
-- clk => SysClk,
-- rst => cpu_reset,
-- rs => trace_cs,
-- bs => bank_cs,
-- rw => cpu_rw,
-- vma => cpu_vma,
-- addr => cpu_addr,
-- data_in => cpu_data_out,
-- reg_data_out => trace_data_out,
-- buff_data_out => bank_data_out,
-- cpu_data_in => cpu_data_in,
-- irq => trace_irq
-- );
 
 
----------------------------------------
--
-- Parallel I/O Port
--
----------------------------------------
my_ioport : ioport port map (
clk => cpu_clk,
rst => cpu_reset,
cs => ioport_cs,
rw => cpu_rw,
data_in => cpu_data_out,
data_out => pb_data_out,
hold => pb_hold,
--
-- Peripheral Bus Interface Signals
-- IO + ($00 - $FF)
--
pb_rd_n => pb_iord_n,
pb_wr_n => pb_iowr_n,
pb_addr(2 downto 0) => pb_addr,
pb_addr(4 downto 3) => open,
pb_data => pb_data,
 
-- Peripheral chip selects on Peripheral Bus
ide_cs => ide_cs,
eth_cs => ether_cs,
sl1_cs => slot1_cs,
sl2_cs => slot2_cs
addr => cpu_addr(1 downto 0),
data_in => cpu_data_out,
data_out => ioport_data_out,
porta_io => porta,
portb_io => portb
);
 
--
-- 12.5 MHz CPU clock
--
cpu_clk_buffer : BUFG port map(
i => clock_div(1),
o => cpu_clk
);
 
------------------------------------------------------
--
-- External Bus interface Dual port RAM ($E200 - $EFFF)
--
-------------------------------------------------------
my_dpr : RAMB4_S8_S8 port map (
RSTA => cpu_rst,
CLKA => cpu_clk,
ENA => dpr_cs,
WEA => dpr_wr,
ADDRA => cpu_addr(8 downto 0),
DIA => cpu_data_out,
DOA => dpr_data_out,
RSTB => cpu_rst,
CLKB => bus_gclk,
ENB => bus_cs,
WEB => bus_wr,
ADDRB => bus_addr(8 downto 0),
DIB => bus_data_in,
DOB => bus_data_out
);
 
my_dpr_ibuf : IBUF port map (
I => bus_clk,
O => bus_iclk
);
 
my_dpr_bufg : BUFG port map (
I => bus_iclk,
O => bus_gclk
);
 
-----------------------------------------------
--
-- BED SRAM interface (256KBytes) ($0000-$DFFF)
--
-----------------------------------------------
my_bed_sram : BED_SRAM port map (
--
-- CPU Interface signals
--
clk => vga_clk, -- VGA Clock (twice the CPU clock)
rst => cpu_rst, -- Reset input (active high)
cs => ram_cs, -- RAM Chip Select
addr(17 downto 12) => dat_addr( 5 downto 0), -- High RAM address goes to the DAT
addr(11 downto 0) => cpu_addr(11 downto 0), -- Low RAM address goes to the CPU
rw => cpu_rw, -- Read / Not Write
data_in => cpu_data_out, -- Data Bus In
data_out => ram_data_out, -- Data Bus Out
--
-- B3_SRAM Interface Signals
--
ram_csn => ram_csn,
ram_wrln => ram_wrln,
ram_wrun => ram_wrun,
ram_addr => ram_addr,
ram_data => ram_data
);
----------------------------------------------------------------------
--
-- Process to decode memory map
--
----------------------------------------------------------------------
 
my_decoder: process( cpu_addr, cpu_rw, cpu_vma,
dat_addr,
rom_data_out,
acia_data_out,
kbd_data_out,
vdu_data_out,
timer_data_out,
trap_data_out,
spp_data_out,
dpr_data_out,
pb_data_out,
ram_data_out )
begin
cpu_data_in <= (others=>'0');
dat_cs <= '0';
rom_cs <= '0';
acia_cs <= '0';
kbd_cs <= '0';
vdu_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
spp_cs <= '0';
dpr_cs <= '0';
pb_cs <= '0';
ram_cs <= '0';
 
if cpu_addr( 15 downto 8 ) = "11111111" then
--
-- Dynamic Address Translation $FFF0 - $FFFF
--
cpu_data_in <= rom_data_out;
dat_cs <= cpu_vma; -- write DAT
rom_cs <= cpu_vma; -- read ROM
 
elsif (dat_addr(3 downto 0) = "1111") and (cpu_addr(11) = '1') then -- $XF800 - $XFFFF
--
-- Sys09Bug Monitor ROM $F000 - $FFFF
--
cpu_data_in <= rom_data_out;
rom_cs <= cpu_vma;
 
elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
--
-- IO Devices $E000 - $E7FF
--
case cpu_addr(11 downto 8) is
 
--
-- SWTPC peripherals from $E000 to $E0FF
--
when "0000" =>
case cpu_addr(7 downto 4) is
--
-- ACIA RS232 Console Port $E000 - $E00F
--
when "0000" => -- $E000
cpu_data_in <= acia_data_out;
acia_cs <= cpu_vma;
 
--
-- Reserved
-- Floppy Disk Controller port $E010 - $E01F
--
when "0001" => -- $E010
null;
 
--
-- Keyboard port $E020 - $E02F
--
when "0010" => -- $E020
cpu_data_in <= kbd_data_out;
kbd_cs <= cpu_vma;
 
--
-- VDU port $E030 - $E03F
--
when "0011" => -- $E030
cpu_data_in <= vdu_data_out;
vdu_cs <= cpu_vma;
 
--
-- Reserved SWTPc MP-T Timer $E040 - $E04F
--
when "0100" => -- $E040
cpu_data_in <= (others=> '0');
 
--
-- Timer $E050 - $E05F
--
when "0101" => -- $E050
cpu_data_in <= timer_data_out;
timer_cs <= cpu_vma;
 
--
-- Bus Trap Logic $E060 - $E06F
--
when "0110" => -- $E060
cpu_data_in <= trap_data_out;
trap_cs <= cpu_vma;
--
-- Bus Trace Logic $E070 - $E07F
--
-- when "0111" => -- $E070
-- cpu_data_in <= trace_data_out;
-- trace_cs <= cpu_vma;
 
--
-- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
--
when "1000" => -- $E080
null;
 
--
-- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
--
 
--
-- Simple Parallel Port $E0A0 - $E0AF
--
when "1010" => -- $E0A0
cpu_data_in <= spp_data_out;
spp_cs <= cpu_vma;
 
--
-- Remaining 5 slots reserved for non SWTPc Peripherals
--
when others => -- $E0B0 to $E0FF
cpu_data_in <= (others=> '0');
 
end case;
--
-- XST-3.0 Peripheral Bus goes here
-- $E100 to $E1FF
-- Four devices
-- IDE, Ethernet, Slot1, Slot2
--
when "0001" =>
cpu_data_in <= pb_data_out;
pb_cs <= cpu_vma;
 
--
-- $E200 to $EFFF reserved for future use
--
when others =>
cpu_data_in <= dpr_data_out;
dpr_cs <= cpu_vma;
 
end case;
 
--
-- Flex RAM $0C000 - $0DFFF
--
-- elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
-- cpu_data_in <= flex_data_out;
-- flex_cs <= cpu_vma;
 
--
-- Everything else is RAM
--
else
cpu_data_in <= ram_data_out;
ram_cs <= cpu_vma;
end if;
 
end process;
 
--
-- IDE drive / CF card signals ($E100 - $E13F)
-- Located on peripheral bus
--
ide_bus: process( cpu_rst, cpu_addr, ide_cs )
begin
ide_cs0_n <= not( ide_cs ) or cpu_addr(4);
ide_cs1_n <= not( ide_cs and cpu_addr(4));
ide_dmack_n <= '1';
ide_rst_n <= not cpu_rst;
ide_con_csel <= '0';
ide_dasp_n <= not ide_cs;
 
end process;
 
--
-- Assign CPU interface signals
--
cpu_controls : process( rst_n, pb_hold,
acia_irq, kbd_irq, trap_irq, timer_irq )
begin
cpu_rst <= not rst_n; -- CPU reset is active high
cpu_irq <= acia_irq or kbd_irq;
cpu_nmi <= trap_irq;
cpu_firq <= timer_irq;
cpu_halt <= '0';
cpu_hold <= pb_hold;
end process;
 
--
-- Assign DPR bus interface signals
--
my_dpr_bus : process( bus_cs_n, bus_rw, cpu_rw )
begin
bus_cs <= not bus_cs_n;
bus_wr <= not bus_rw;
dpr_wr <= not cpu_rw;
-- trace_data_out <= (others=>'0');
end process;
 
--
-- Assign VDU VGA output signals
-- only 8 colours are handled.
--
my_vga_out: process( vga_red_o, vga_green_o, vga_blue_o )
begin
vga_red(0) <= vga_red_o;
vga_red(1) <= vga_red_o;
vga_green(0) <= vga_green_o;
vga_green(1) <= vga_green_o;
vga_blue(0) <= vga_blue_o;
vga_blue(1) <= vga_blue_o;
end process;
 
end rtl; --===================== End of architecture =======================--
--
-- 25 MHz VGA Pixel clock
--
vga_clk_buffer : BUFG port map(
i => clock_div(0),
o => pix_clk
);
----------------------------------------------------------------------
--
-- Process to decode memory map
--
----------------------------------------------------------------------
 
mem_decode: process( cpu_clk, Reset_n, dat_addr,
cpu_addr, cpu_rw, cpu_vma,
rom_data_out,
ram_data_out,
-- cf_data_out,
timer_data_out,
trap_data_out,
ioport_data_out,
uart_data_out,
keyboard_data_out,
vdu_data_out,
-- trace_data_out,
bus_data )
variable decode_addr : std_logic_vector(4 downto 0);
begin
decode_addr := dat_addr(3 downto 0) & cpu_addr(11);
-- decode_addr := cpu_addr(15 downto 11);
 
if cpu_addr( 15 downto 8 ) = "11111111" then
cpu_data_in <= rom_data_out;
rom_cs <= cpu_vma; -- read ROM
dat_cs <= cpu_vma; -- write DAT
ram_cs <= '0';
uart_cs <= '0';
-- cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
-- trace_cs <= '0';
else
case decode_addr is
--
-- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF
--
when "11111" => -- $F800 - $FFFF
cpu_data_in <= rom_data_out;
rom_cs <= cpu_vma; -- read ROM
dat_cs <= '0';
ram_cs <= '0';
uart_cs <= '0';
-- cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
-- trace_cs <= '0';
 
--
-- IO Devices $E000 - $E7FF
--
when "11100" => -- $E000 - $E7FF
rom_cs <= '0';
dat_cs <= '0';
ram_cs <= '0';
case cpu_addr(7 downto 4) is
--
-- UART / ACIA $E000
--
when "0000" => -- $E000
cpu_data_in <= uart_data_out;
uart_cs <= cpu_vma;
-- cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
-- trace_cs <= '0';
 
--
-- WD1771 FDC sites at $E010-$E01F
--
 
--
-- Keyboard port $E020 - $E02F
--
when "0010" => -- $E020
cpu_data_in <= keyboard_data_out;
uart_cs <= '0';
-- cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= cpu_vma;
vdu_cs <= '0';
bus_cs <= '0';
-- trace_cs <= '0';
 
--
-- VDU port $E030 - $E03F
--
when "0011" => -- $E030
cpu_data_in <= vdu_data_out;
uart_cs <= '0';
-- cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= cpu_vma;
bus_cs <= '0';
-- trace_cs <= '0';
 
 
--
-- Compact Flash $E040 - $E04F
--
-- when "0100" => -- $E040
-- cpu_data_in <= cf_data_out;
-- uart_cs <= '0';
-- cf_cs <= cpu_vma;
-- timer_cs <= '0';
-- trap_cs <= '0';
-- ioport_cs <= '0';
-- keyboard_cs <= '0';
-- vdu_cs <= '0';
-- bus_cs <= '0';
-- trace_cs <= '0';
 
--
-- Timer $E050 - $E05F
--
when "0101" => -- $E050
cpu_data_in <= timer_data_out;
uart_cs <= '0';
-- cf_cs <= '0';
timer_cs <= cpu_vma;
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
-- trace_cs <= '0';
 
--
-- Bus Trap Logic $E060 - $E06F
--
-- when "0110" => -- $E060
-- cpu_data_in <= trap_data_out;
-- uart_cs <= '0';
-- cf_cs <= '0';
-- timer_cs <= '0';
-- trap_cs <= cpu_vma;
-- ioport_cs <= '0';
-- keyboard_cs <= '0';
-- vdu_cs <= '0';
-- bus_cs <= '0';
-- trace_cs <= '0';
 
--
-- I/O port $E070 - $E07F
--
when "0111" => -- $E070
cpu_data_in <= ioport_data_out;
uart_cs <= '0';
-- cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= cpu_vma;
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
-- trace_cs <= '0';
 
--
-- Bus Trace Logic $E0C00 - $E0CF
--
-- when "1100" => -- $E0C0
-- cpu_data_in <= trace_data_out;
-- uart_cs <= '0';
-- keyboard_cs <= '0';
-- timer_cs <= '0';
-- vdu_cs <= '0';
-- ioport_cs <= '0';
-- cf_cs <= '0';
-- trap_cs <= '0';
-- trace_cs <= cpu_vma;
 
 
when others => -- $E080 to $E7FF
cpu_data_in <= bus_data;
uart_cs <= '0';
-- cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= cpu_vma;
-- trace_cs <= '0';
end case;
--
-- Everything else is RAM
--
when others =>
cpu_data_in <= ram_data_out;
rom_cs <= '0';
dat_cs <= '0';
ram_cs <= cpu_vma;
uart_cs <= '0';
-- cf_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ioport_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
bus_cs <= '0';
-- trace_cs <= '0';
end case;
end if;
end process;
 
 
--
-- B5-SRAM Control
-- Processes to read and write memory based on bus signals
--
ram_process: process( cpu_clk, Reset_n,
cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
dat_addr,
ram_cs, ram_wrl, ram_wru, ram_data_out )
begin
ram_csn <= not( ram_cs and Reset_n );
ram_wrl <= (not cpu_addr(0)) and (not cpu_rw) and cpu_clk;
ram_wrln <= not (ram_wrl);
ram_wru <= cpu_addr(0) and (not cpu_rw) and cpu_clk;
ram_wrun <= not (ram_wru);
ram_addr(16 downto 11) <= dat_addr(5 downto 0);
ram_addr(10 downto 0) <= cpu_addr(11 downto 1);
 
if ram_wrl = '1' then
ram_data(7 downto 0) <= cpu_data_out;
else
ram_data(7 downto 0) <= "ZZZZZZZZ";
end if;
 
if ram_wru = '1' then
ram_data(15 downto 8) <= cpu_data_out;
else
ram_data(15 downto 8) <= "ZZZZZZZZ";
end if;
 
if cpu_addr(0) = '1' then
ram_data_out <= ram_data(15 downto 8);
else
ram_data_out <= ram_data(7 downto 0);
end if;
end process;
 
--
-- Compact Flash Control
--
--compact_flash: process( Reset_n,
-- cpu_addr, cpu_rw, cpu_vma, cpu_data_out,
-- cf_cs, cf_rd, cf_wr, cf_d )
--begin
-- cf_rst_n <= Reset_n;
-- cf_cs0_n <= not( cf_cs ) or cpu_addr(3);
-- cf_cs1_n <= not( cf_cs and cpu_addr(3));
-- cf_cs16_n <= '1';
-- cf_wr <= cf_cs and (not cpu_rw);
-- cf_rd <= cf_cs and cpu_rw;
-- cf_wr_n <= not cf_wr;
-- cf_rd_n <= not cf_rd;
-- cf_a <= cpu_addr(2 downto 0);
-- if cf_wr = '1' then
-- cf_d(7 downto 0) <= cpu_data_out;
-- else
-- cf_d(7 downto 0) <= "ZZZZZZZZ";
-- end if;
-- cf_data_out <= cf_d(7 downto 0);
-- cf_d(15 downto 8) <= "ZZZZZZZZ";
--end process;
 
--
-- Hold CF access for a few cycles
--
--cf_hold_proc: process( cpu_clk, Reset_n )
--begin
-- if Reset_n = '0' then
-- cf_release <= '0';
-- cf_count <= "0000";
-- cf_hold_state <= hold_release_state;
-- elsif cpu_clk'event and cpu_clk='0' then
-- case cf_hold_state is
-- when hold_release_state =>
-- cf_release <= '0';
-- if cf_cs = '1' then
-- cf_count <= "0011";
-- cf_hold_state <= hold_request_state;
-- end if;
--
-- when hold_request_state =>
-- cf_count <= cf_count - "0001";
-- if cf_count = "0000" then
-- cf_release <= '1';
-- cf_hold_state <= hold_release_state;
-- end if;
-- when others =>
-- null;
-- end case;
-- end if;
--end process;
 
--
-- Interrupts and other bus control signals
--
interrupts : process( Reset_n,
-- cf_cs, cf_hold, cf_release,
uart_irq,
trap_irq,
timer_irq, keyboard_irq
)
begin
-- cf_hold <= cf_cs and (not cf_release);
cpu_reset <= not Reset_n; -- CPU reset is active high
cpu_irq <= uart_irq or keyboard_irq;
cpu_nmi <= trap_irq;
cpu_firq <= timer_irq;
cpu_halt <= '0';
-- cpu_hold <= cf_hold;
cpu_hold <= '0';
end process;
 
--
-- CPU bus signals
--
my_bus : process( cpu_clk, cpu_reset, cpu_rw, cpu_addr, cpu_data_out, bus_cs )
begin
bus_clk <= cpu_clk;
bus_reset <= cpu_reset;
bus_rw <= cpu_rw;
bus_csn <= not bus_cs;
bus_addr <= dat_addr(7 downto 0) & cpu_addr(11 downto 0);
if( cpu_rw = '1' ) then
bus_data <= "ZZZZZZZZ";
else
bus_data <= cpu_data_out;
end if;
end process;
 
--
-- flash led to indicate code is working
--
my_LED_Flasher: process (cpu_clk, CountL )
begin
if(cpu_clk'event and cpu_clk = '0') then
countL <= countL + 1;
end if;
LED <= countL(23);
dcd_n <= '0';
end process;
 
--
-- Clock divider
--
my_clock_divider: process( SysClk )
begin
if SysClk'event and SysClk='0' then
clock_div <= clock_div + "01";
end if;
end process;
--
-- Assign VDU VGA colour output
-- only 8 colours are handled.
--
my_vga_out: process( vga_red, vga_green, vga_blue )
begin
red_lo <= vga_red;
red_hi <= vga_red;
green_lo <= vga_green;
green_hi <= vga_green;
blue_lo <= vga_blue;
blue_hi <= vga_blue;
end process;
 
end rtl; --===================== End of architecture =======================--

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