URL
https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
Compare Revisions
- This comparison shows the changes necessary to convert path
/System09/trunk/rtl/System09_Digilent_Atlys
- from Rev 189 to Rev 192
- ↔ Reverse comparison
Rev 189 → Rev 192
/system09.prj
8,7 → 8,6
vhdl work "../VHDL/ACIA_Clock.vhd" |
vhdl work "../VHDL/acia6850.vhd" |
vhdl work "common.vhd" |
vhdl work "btn_debounce.vhd" |
vhdl work "../Spartan3/ram32k_b16.vhd" |
vhdl work "../Spartan3/ram16k_b16.vhd" |
vhdl work "system09.vhd" |
/system09.ucf
67,21 → 67,21
# SYSTEM09: Push button switches |
# |
# NET "btn<0>" LOC = "T15"; # Bank = 2, Pin name = IO_L1N_M0_CMPMISO_2, Sch name = M0/RESET |
NET "btn<0>" LOC = "N4"; # Bank = 3, Pin name = IO_L1P, Sch name = BTNU |
NET "btn<1>" LOC = "P4"; # Bank = 3, Pin name = IO_L2P, Sch name = BTNL |
NET "btn<2>" LOC = "P3"; # Bank = 3, Pin name = IO_L2N, Sch name = BTND |
NET "btn<3>" LOC = "F6"; # Bank = 3, Pin name = IO_L55P_M3A13, Sch name = BTNR |
NET "btn<4>" LOC = "F5"; # Bank = 3, Pin name = IO_L55N_M3A14, Sch name = BTNC |
# NET "btn<0>" LOC = "N4"; # Bank = 3, Pin name = IO_L1P, Sch name = BTNU |
# NET "btn<1>" LOC = "P4"; # Bank = 3, Pin name = IO_L2P, Sch name = BTNL |
# NET "btn<2>" LOC = "P3"; # Bank = 3, Pin name = IO_L2N, Sch name = BTND |
NET "RESET" LOC = "T15"; # Bank = 3, Pin name = IO_L55P_M3A13, Sch name = BTNR |
NET "NMI" LOC = "F5"; # Bank = 3, Pin name = IO_L55N_M3A14, Sch name = BTNC |
|
# onBoard SWITCHES |
NET "sw<0>" LOC = "A10"; # Bank = 0, Pin name = IO_L37N_GCLK12, Sch name = SW0 |
NET "sw<1>" LOC = "D14"; # Bank = 0, Pin name = IO_L65P_SCP3, Sch name = SW1 |
NET "sw<2>" LOC = "C14"; # Bank = 0, Pin name = IO_L65N_SCP2, Sch name = SW2 |
NET "sw<3>" LOC = "P15"; # Bank = 1, Pin name = IO_L74P_AWAKE_1, Sch name = SW3 |
NET "sw<4>" LOC = "P12"; # Bank = 2, Pin name = IO_L13N_D10, Sch name = SW4 |
NET "sw<5>" LOC = "R5"; # Bank = 2, Pin name = IO_L48P_D7, Sch name = SW5 |
NET "sw<6>" LOC = "T5"; # Bank = 2, Pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW6 |
NET "sw<7>" LOC = "E4"; # Bank = 3, Pin name = IO_L54P_M3RESET, Sch name = SW7 |
# NET "sw<3>" LOC = "P15"; # Bank = 1, Pin name = IO_L74P_AWAKE_1, Sch name = SW3 |
# NET "sw<4>" LOC = "P12"; # Bank = 2, Pin name = IO_L13N_D10, Sch name = SW4 |
# NET "sw<5>" LOC = "R5"; # Bank = 2, Pin name = IO_L48P_D7, Sch name = SW5 |
# NET "sw<6>" LOC = "T5"; # Bank = 2, Pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW6 |
# NET "sw<7>" LOC = "E4"; # Bank = 3, Pin name = IO_L54P_M3RESET, Sch name = SW7 |
|
# TEMAC Ethernet MAC |
# NET "phyrst" LOC = "G13"; # Bank = 1, Pin name = IO_L32N_A16_M1A9, Sch name = E-RESET |
/system09.vhd
129,23 → 129,20
entity system09 is |
port( |
CLKA : in Std_Logic; -- 100MHz Clock input |
--RESET_N : in Std_logic; -- Master Reset input (active low) |
--NMI_N : in Std_logic; -- Non Maskable Interrupt input (active low) |
RESET : in Std_logic; -- Master Reset input (active high) -- red "RESET" PB |
NMI : in Std_logic; -- Non Maskable Interrupt input (active high) -- Center PB |
|
-- RS232 Port |
RS232_RTS : out std_logic; |
RS232_CTS : in std_logic; |
-- RS232 Port - via Pmod RS232 |
RS232_CTS : in Std_Logic; |
RS232_RTS : out Std_Logic; |
RS232_RXD : in Std_Logic; |
RS232_TXD : out Std_Logic; |
|
-- slide switches |
sw : in std_logic_vector(7 downto 0); |
-- push buttons (Right=SS, Center=NMI, Left=RESET) |
btn : in std_logic_vector(4 downto 0); |
sw : in std_logic_vector(2 downto 0); |
-- Status 7 segment LED |
S : out std_logic_vector(7 downto 0) |
S : out std_logic_vector(7 downto 0) |
|
|
-- CPU Debug Interface signals |
-- cpu_reset_o : out Std_Logic; |
-- cpu_clk_o : out Std_Logic; |
173,26 → 170,16
----------------------------------------------------------------------------- |
constant CLOCK_MODE : natural := 0; -- 0 means normal, 1 means single-step |
|
constant MEM_CLK_FREQ : natural := 100_000; -- operating frequency of Memory in KHz |
constant SYS_CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0) |
|
constant SYS_CLK_FREQ : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000; -- FPGA System Clock (in Hz) |
constant SYS_CLK_FREQ : natural := 100_000_000; -- FPGA System Clock (in Hz) |
constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz) |
constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ); |
constant BAUD_RATE : integer := 57600; -- Baud Rate |
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16; |
|
constant TRESET : natural := 300; -- min initialization interval (us) |
constant RST_CYCLES : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000)); -- SDRAM power-on initialization interval |
|
----------------------------------------------------------------------------- |
-- Signals |
----------------------------------------------------------------------------- |
signal pbtn : std_logic_vector(4 downto 0); |
signal NMI_N : std_logic; |
signal RESET_N : std_logic; |
signal SINGLE_STEP : std_logic; |
|
|
-- BOOT ROM |
signal rom_cs : Std_logic; |
signal rom_data_out : Std_Logic_Vector(7 downto 0); |
206,8 → 193,8
signal acia_cs : Std_Logic; |
signal acia_irq : Std_Logic; |
signal acia_clk : Std_Logic; |
signal rxd : Std_Logic; |
signal txd : Std_Logic; |
signal RXD : Std_Logic; |
signal TXD : Std_Logic; |
signal DCD_n : Std_Logic; |
signal RTS_n : Std_Logic; |
signal CTS_n : Std_Logic; |
253,14 → 240,6
signal CountL : std_logic_vector(23 downto 0); |
signal clk_count : natural range 0 to CPU_CLK_DIV; |
signal Clk25 : std_logic; |
|
|
component btn_debounce |
Port ( BTN_I : in STD_LOGIC_VECTOR (4 downto 0); |
CLK : in STD_LOGIC; |
BTN_O : out STD_LOGIC_VECTOR (4 downto 0)); |
end component; |
|
|
----------------------------------------------------------------- |
-- |
475,47 → 454,33
end component; |
|
begin |
|
-- |
-- pushbutton debounce |
-- |
my_singlestep: btn_debounce |
port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn); |
|
RESET_N <= pbtn(3); -- Right PB |
NMI_N <= pbtn(4); -- Center PB |
SINGLE_STEP <= pbtn(1); -- Left PB |
|
-- |
-- Generate CPU & Pixel Clock from Memory Clock |
-- |
NORMAL: if CLOCK_MODE = 0 generate |
my_prescaler : process( clk_i, clk_count ) |
begin |
if rising_edge( clk_i ) then |
if clk_count = 0 then |
clk_count <= CPU_CLK_DIV-1; |
else |
clk_count <= clk_count - 1; |
end if; |
if clk_count = 0 then |
clk25 <= '0'; |
elsif clk_count = (CPU_CLK_DIV/2) then |
clk25 <= '1'; |
end if; |
|
my_prescaler : process( clk_i, clk_count ) |
begin |
if rising_edge( clk_i ) then |
if clk_count = 0 then |
clk_count <= CPU_CLK_DIV-1; |
else |
clk_count <= clk_count - 1; |
end if; |
end process; |
end generate; |
SS: if CLOCK_MODE = 1 generate |
clk25 <= SINGLE_STEP; |
end generate; |
if clk_count = 0 then |
clk25 <= '0'; |
elsif clk_count = (CPU_CLK_DIV/2) then |
clk25 <= '1'; |
end if; |
end if; |
end process; |
|
-- |
-- Reset button and reset timer |
-- |
my_switch_assignments : process( rst_i, RESET_N) |
my_switch_assignments : process( rst_i, RESET) |
begin |
rst_i <= RESET_N; |
rst_i <= RESET; |
cpu_reset <= rst_i; |
end process; |
|
543,13 → 508,13
|
my_rom : mon_rom |
port map ( |
clk => cpu_clk, |
rst => cpu_reset, |
cs => rom_cs, |
rw => '1', |
addr => cpu_addr(11 downto 0), |
data_in => cpu_data_out, |
data_out => rom_data_out |
clk => cpu_clk, |
rst => cpu_reset, |
cs => rom_cs, |
rw => '1', |
addr => cpu_addr(11 downto 0), |
data_in => cpu_data_out, |
data_out => rom_data_out |
); |
|
my_flex : flex_ram |
559,8 → 524,8
cs => flex_cs, |
rw => cpu_rw, |
addr => cpu_addr(12 downto 0), |
data_out => flex_data_out, |
data_in => cpu_data_out |
data_out => flex_data_out, |
data_in => cpu_data_out |
); |
|
my_32k : ram_32k |
570,8 → 535,8
cs => ram1_cs, |
rw => cpu_rw, |
addr => cpu_addr(14 downto 0), |
data_out => ram1_data_out, |
data_in => cpu_data_out |
data_out => ram1_data_out, |
data_in => cpu_data_out |
); |
|
my_16k : ram_16k |
581,8 → 546,8
cs => ram2_cs, |
rw => cpu_rw, |
addr => cpu_addr(13 downto 0), |
data_out => ram2_data_out, |
data_in => cpu_data_out |
data_out => ram2_data_out, |
data_in => cpu_data_out |
); |
|
my_acia : acia6850 |
597,13 → 562,24
irq => acia_irq, |
RxC => acia_clk, |
TxC => acia_clk, |
RxD => RS232_RXD, |
TxD => RS232_TXD, |
DCD_n => dcd_n, |
CTS_n => RS232_CTS, |
RTS_n => RS232_RTS |
); |
dcd_n <= '0'; |
RxD => RXD, |
TxD => TXD, |
DCD_n => DCD_n, |
CTS_n => CTS_n, |
RTS_n => RTS_n |
); |
|
-- |
-- RS232 signals: |
-- |
my_acia_assignments : process( RS232_RXD, RS232_CTS, TXD, RTS_n ) |
begin |
RXD <= RS232_RXD; |
CTS_n <= RS232_CTS; |
DCD_n <= '0'; |
RS232_TXD <= TXD; |
RS232_RTS <= RTS_n; |
end process; |
|
my_ACIA_Clock : ACIA_Clock |
generic map( |
611,7 → 587,7
ACIA_CLK_FREQ => ACIA_CLK_FREQ |
) |
port map( |
clk => Clk_i, |
clk => clk_i, |
acia_clk => acia_clk |
); |
|
691,8 → 667,9
acia_cs <= '0'; |
timer_cs <= '0'; |
trap_cs <= '0'; |
ram1_cs <= '0'; |
ram2_cs <= '0'; |
ram1_cs <= '0'; |
ram2_cs <= '0'; |
ram3_cs <= '0'; |
|
if cpu_addr( 15 downto 8 ) = "11111111" then -- $FFxx |
cpu_data_in <= rom_data_out; |
769,29 → 746,29
when others => |
null; |
end case; |
|
-- |
-- Flex RAM $0C000 - $0DFFF |
-- |
elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF |
cpu_data_in <= flex_data_out; |
flex_cs <= cpu_vma; |
|
-- |
-- 32k RAM $00000 - $07FFF |
-- Block RAM (32k) $00000 - $07FFF |
-- |
elsif dat_addr(7 downto 1) = "0000000" then -- $00000 - $07FFF |
elsif dat_addr(7 downto 3) = "00000" then -- $00000 - $07FFF |
cpu_data_in <= ram1_data_out; |
ram1_cs <= cpu_vma; |
|
-- |
-- 16k RAM $08000 - $0BFFF |
-- Block RAM (16k) $08000 - $0BFFF |
-- |
elsif dat_addr(7 downto 1) = "0000100" then -- $08000 - $0BFFF |
elsif dat_addr(7 downto 2) = "000010" then -- $08000 - $0BFFF |
cpu_data_in <= ram2_data_out; |
ram2_cs <= cpu_vma; |
|
-- |
-- Flex RAM (8k) $0C000 - $0DFFF |
-- |
elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF |
cpu_data_in <= flex_data_out; |
flex_cs <= cpu_vma; |
|
-- |
-- Everything else is RAM |
-- |
else |
804,7 → 781,7
-- |
-- Interrupts and other bus control signals |
-- |
interrupts : process( NMI_N, |
interrupts : process( NMI, |
acia_irq, |
trap_irq, |
timer_irq |
811,12 → 788,12
) |
begin |
cpu_irq <= acia_irq; |
cpu_nmi <= trap_irq or not( NMI_N ); |
cpu_nmi <= trap_irq or NMI; |
cpu_firq <= timer_irq; |
cpu_halt <= '0'; |
cpu_hold <= '0'; -- pb_hold or ram_hold; |
end process; |
|
|
-- |
-- Flash 7 segment LEDS |
-- |
827,30 → 804,26
elsif rising_edge(clk_i) then |
CountL <= CountL + 1; |
end if; |
--S(7 downto 0) <= CountL(23 downto 16); |
end process; |
end process; |
|
|
|
|
status_leds : process( rst_i, cpu_reset,cpu_addr, cpu_rw, sw) |
status_leds : process( rst_i, cpu_reset, cpu_addr, NMI, cpu_data_in, cpu_rw, CountL, sw) |
begin |
S(7) <= '0'; |
S(6) <= cpu_rw; |
S(5) <= cpu_vma; |
S(4) <= '0'; |
S(6) <= CountL(23); |
S(5) <= cpu_rw; |
S(4) <= NMI; |
case sw is |
when "00000000" => |
when "000" => |
S(3 downto 0) <= cpu_addr(3 downto 0); |
when "00000001" => |
when "001" => |
S(3 downto 0) <= cpu_addr(7 downto 4); |
when "00000010" => |
when "010" => |
S(3 downto 0) <= cpu_addr(11 downto 8); |
when "00000011" => |
when "011" => |
S(3 downto 0) <= cpu_addr(15 downto 12); |
when "00000100" => |
when "100" => |
S(3 downto 0) <= cpu_data_in(3 downto 0); |
when "00000101" => |
when "101" => |
S(3 downto 0) <= cpu_data_in(7 downto 4); |
when others => S(3 downto 0) <= (others => '0'); |
end case; |
/system09.xise
56,15 → 56,15
</file> |
<file xil_pn:name="system09.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="14"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="13"/> |
</file> |
<file xil_pn:name="../Spartan3/ram32k_b16.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="12"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> |
</file> |
<file xil_pn:name="../Spartan3/ram16k_b16.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="13"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="12"/> |
</file> |
<file xil_pn:name="../../src/sys09bug/sys09swt.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/> |
72,7 → 72,7
</file> |
<file xil_pn:name="btn_debounce.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
</files> |
|