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URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

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  • This comparison shows the changes necessary to convert path 
    /System09/trunk/rtl/System09_Digilent_Atlys
    from Rev 217 to Rev 222
    ↔ Reverse comparison
  •

Rev 217 → Rev 222

/Makefile
54,7 → 54,7
roms:
@$(MAKE) -C ../../Tools/as09
@$(MAKE) -C ../../Tools/s19tovhd
@$(MAKE) -C ../../src/sys09bug sys09swt.vhd
@$(MAKE) -C ../../src/sys09bug sys09atl.vhd
@$(MAKE) -C ../../src/Flex9 flex9ram.vhd
 
#===================================================================
/system09.prj
4,11 → 4,12
vhdl work "../VHDL/bit_funcs.vhd"
verilog work "../Verilog/rgb2hdmi_encode.v"
vhdl work "../Spartan3/char_rom2k_b16.vhd"
vhdl work "../../src/sys09bug/sys09xes.vhd"
vhdl work "../../src/sys09bug/sys09atl.vhd"
vhdl work "../../src/Flex9/flex9ram.vhd"
vhdl work "../VHDL/vdu8_hdmi.vhd"
vhdl work "../VHDL/trap.vhd"
vhdl work "../VHDL/timer.vhd"
vhdl work "../VHDL/spi-master.vhd"
vhdl work "../VHDL/keyboard.vhd"
vhdl work "../VHDL/datram.vhd"
vhdl work "../VHDL/cpu09.vhd"
/system09.ucf
80,7 → 80,7
NET "sw<0>" LOC = "A10"; # Bank = 0, Pin name = IO_L37N_GCLK12, Sch name = SW0
NET "sw<1>" LOC = "D14"; # Bank = 0, Pin name = IO_L65P_SCP3, Sch name = SW1
NET "sw<2>" LOC = "C14"; # Bank = 0, Pin name = IO_L65N_SCP2, Sch name = SW2
# NET "sw<3>" LOC = "P15"; # Bank = 1, Pin name = IO_L74P_AWAKE_1, Sch name = SW3
NET "sw<3>" LOC = "P15"; # Bank = 1, Pin name = IO_L74P_AWAKE_1, Sch name = SW3
# NET "sw<4>" LOC = "P12"; # Bank = 2, Pin name = IO_L13N_D10, Sch name = SW4
# NET "sw<5>" LOC = "R5"; # Bank = 2, Pin name = IO_L48P_D7, Sch name = SW5
# NET "sw<6>" LOC = "T5"; # Bank = 2, Pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW6
241,10 → 241,10
# NET "JB<7>" LOC = "T4"; # Bank = 2, Pin name = IO_L63P, Sch name = JA-D1_P
 
# Pmod Connector to Pmod-SDCard
# NET "SD_CS_n" LOC = "T3"; # Bank = 2, Pin name = IO_L62N_D6, Sch name = JA-D0_N
# NET "SD_MOSI" LOC = "R3"; # Bank = 2, Pin name = IO_L62P_D5, Sch name = JA-D0_P
# NET "SD_MISO" LOC = "P6"; # Bank = 2, Pin name = IO_L64N_D9, Sch name = JA-D2_N
# NET "SD_SCK" LOC = "N5"; # Bank = 2, Pin name = IO_L64P_D8, Sch name = JA-D2_P
NET "spi_cs_n<0>" LOC = "T3"; # Bank = 2, Pin name = IO_L62N_D6, Sch name = JA-D0_N
NET "spi_mosi" LOC = "R3"; # Bank = 2, Pin name = IO_L62P_D5, Sch name = JA-D0_P
NET "spi_miso" LOC = "P6"; # Bank = 2, Pin name = IO_L64N_D9, Sch name = JA-D2_N
NET "spi_clk" LOC = "N5"; # Bank = 2, Pin name = IO_L64P_D8, Sch name = JA-D2_P
# NET "SD_DAT1" LOC = "V9"; # Bank = 2, Pin name = IO_L32N_GCLK28, Sch name = JA-CLK_N
# NET "SD_DAT2" LOC = "T9"; # Bank = 2, Pin name = IO_L32P_GCLK29, Sch name = JA-CLK_P
# NET "SD_CD" LOC = "V4"; # Bank = 2, Pin name = IO_L63N, Sch name = JA-D1_N
/system09.vhd
147,9 → 147,15
-- RS232_RTS : out Std_Logic;
RS232_RXD : in Std_Logic;
RS232_TXD : out Std_Logic;
 
 
-- SPI Interface Signals (Pmod-SDCard)
spi_miso : in std_logic;
spi_mosi : out std_logic;
spi_clk : out std_logic;
spi_cs_n : out std_logic_vector(7 downto 0);
-- slide switches
sw : in std_logic_vector(2 downto 0);
sw : in std_logic_vector(3 downto 0);
-- Status 7 segment LED
S : out std_logic_vector(7 downto 0)
 
245,7 → 251,12
signal vdu_clk : std_logic;
signal vdu_cs : std_logic;
signal vdu_data_out : std_logic_vector(7 downto 0);
 
 
-- SPI-master to SDcard
signal spi_data_out : std_logic_vector(7 downto 0);
signal spi_cs : std_logic;
signal spi_irq : std_logic;
-- timer
signal timer_data_out : std_logic_vector(7 downto 0);
signal timer_cs : std_logic;
468,6 → 479,35
TMDSn : out std_logic_vector(2 downto 0)
);
end component;
 
----------------------------------------
--
-- SPI master module
--
----------------------------------------
 
component spi_master
port (
--
-- CPU Interface Signals
--
clk : in std_logic;
reset : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(1 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic;
--
-- SPI Interface Signals
--
spi_miso : in std_logic;
spi_mosi : out std_logic;
spi_clk : out std_logic;
spi_cs_n : out std_logic_vector(7 downto 0)
);
end component;
 
----------------------------------------
--
742,6 → 782,26
TMDSn_clock => TMDSn_clock
);
 
----------------------------------------
--
-- SPI-Master to SDcard
--
----------------------------------------
my_spi_master : spi_master
port map (
clk => cpu_clk,
reset => cpu_reset,
cs => spi_cs,
rw => cpu_rw,
addr => cpu_addr(1 downto 0),
data_in => cpu_data_out,
data_out => spi_data_out,
irq => spi_irq,
spi_miso => spi_miso,
spi_mosi => spi_mosi,
spi_clk => spi_clk,
spi_cs_n => spi_cs_n
);
 
----------------------------------------
--
808,7 → 868,8
flex_data_out,
acia_data_out,
keyboard_data_out,
vdu_data_out,
vdu_data_out,
spi_data_out,
timer_data_out,
trap_data_out,
ram1_data_out, ram2_data_out
820,7 → 881,8
flex_cs <= '0';
acia_cs <= '0';
keyboard_cs <= '0';
vdu_cs <= '0';
vdu_cs <= '0';
spi_cs <= '0';
timer_cs <= '0';
trap_cs <= '0';
ram1_cs <= '0';
901,7 → 963,14
 
--
-- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
--
--
-- SPI-master $E0A0 - $E0AF
--
when "1010" => -- $E0A0
cpu_data_in <= spi_data_out;
spi_cs <= cpu_vma;
 
--
-- Remaining 6 slots reserved for non SWTPc Peripherals
953,12 → 1022,13
--
interrupts : process( NMI,
acia_irq,
keyboard_irq,
keyboard_irq,
spi_irq,
trap_irq,
timer_irq
)
begin
cpu_irq <= acia_irq or keyboard_irq;
cpu_irq <= acia_irq or keyboard_irq or spi_irq;
cpu_nmi <= trap_irq or NMI;
cpu_firq <= timer_irq;
cpu_halt <= '0';
984,22 → 1054,26
S(5) <= cpu_reset;
S(4) <= NMI;
case sw is
when "000" =>
when "0000" =>
S(3 downto 0) <= cpu_addr(3 downto 0);
when "001" =>
when "0001" =>
S(3 downto 0) <= cpu_addr(7 downto 4);
when "010" =>
when "0010" =>
S(3 downto 0) <= cpu_addr(11 downto 8);
when "011" =>
when "0011" =>
S(3 downto 0) <= cpu_addr(15 downto 12);
when "100" =>
when "0100" =>
S(3 downto 0) <= cpu_data_in(3 downto 0);
when "101" =>
when "0101" =>
S(3 downto 0) <= cpu_data_in(7 downto 4);
when "110" =>
when "0110" =>
S(3 downto 0) <= keyboard_data_out(3 downto 0);
when "111" =>
S(3 downto 0) <= keyboard_data_out(7 downto 4);
when "0111" =>
S(3 downto 0) <= keyboard_data_out(7 downto 4);
when "1000" =>
S(3 downto 0) <= spi_data_out(3 downto 0);
when "1001" =>
S(3 downto 0) <= spi_data_out(7 downto 4);
when others => S(3 downto 0) <= (others => '0');
end case;
end process;
/system09.xise
17,7 → 17,7
<files>
<file xil_pn:name="common.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../VHDL/timer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
29,15 → 29,15
</file>
<file xil_pn:name="../VHDL/ACIA_Clock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../VHDL/acia6850.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../VHDL/datram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../VHDL/trap.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
45,7 → 45,7
</file>
<file xil_pn:name="../VHDL/cpu09.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../VHDL/bit_funcs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
56,15 → 56,15
</file>
<file xil_pn:name="system09.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../Spartan3/ram32k_b16.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../Spartan3/ram16k_b16.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../VHDL/ps2_keyboard.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
72,16 → 72,12
</file>
<file xil_pn:name="../VHDL/keyboard.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../Spartan6/keymap_rom512_b4.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../src/sys09bug/sys09xes.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../Spartan3/char_rom2k_b16.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
98,6 → 94,14
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../VHDL/spi-master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../src/sys09bug/sys09atl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
</files>
 
<properties>

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