URL
https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
Compare Revisions
- This comparison shows the changes necessary to convert path
/System09/trunk/rtl/Testbench
- from Rev 66 to Rev 122
- ↔ Reverse comparison
Rev 66 → Rev 122
/testbench1.vhd
1,10 → 1,9
--===========================================================================---- |
--===========================================================================-- |
-- -- |
-- TESTBENCH testbench1 - CPU09 Testbench. -- |
-- -- |
--===========================================================================-- |
-- |
-- T E S T B E N C H tesetbench1 - CPU09 Testbench. |
-- |
-- www.OpenCores.Org - September 2003 |
-- This core adheres to the GNU public license |
-- |
-- File name : Testbench1.vhd |
-- |
-- Purpose : cpu09 Microprocessor Test Bench 1 |
20,22 → 19,35
-- |
-- Author : John E. Kent |
-- dilbert57@opencores.org |
-- |
-- Copyright (C) 2003 - 2010 John Kent |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
--===========================================================================-- |
-- -- |
-- Revision History -- |
-- -- |
--===========================================================================-- |
-- |
--===========================================================================---- |
-- Rev Date Author Changes |
-- 0.1 2003-04-12 John Kent First version |
-- 1.0 2003-09-06 John Kent Initial release to Opencores.org |
-- 1.1 2004-01-25 John Kent removed "test_alu" and "test_cc" from CPU component |
-- 1.2 2011-10-09 John Kent updated for acia6850 |
-- |
-- Revision History: |
--===========================================================================-- |
-- |
-- Version 0.1 - 12st April 2003 - John Kent |
-- First version |
-- |
-- Version 1.0- 6 Sep 2003 - John Kent |
-- Initial release to Open Cores |
-- |
-- Version 1.1 - 25th Jan 2004 - John Kent |
-- removed "test_alu" and "test_cc" |
-- |
--===========================================================================-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
42,18 → 54,18
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
use ieee.numeric_std.all; |
-- library work; |
--library work; |
-- use work.UART_Def.all; |
-- use work.typedefines.all; |
-- use work.memory.all; |
|
entity my_testbench is |
end my_testbench; |
entity my_testbench1 is |
end my_testbench1; |
|
------------------------------------------------------------------------------- |
-- Architecture for memio Controller Unit |
------------------------------------------------------------------------------- |
architecture behavior of my_testbench is |
architecture behavior of my_testbench1 is |
----------------------------------------------------------------------------- |
-- Signals |
----------------------------------------------------------------------------- |
110,9 → 122,9
port ( |
clk: in std_logic; |
rst: in std_logic; |
rw: out std_logic; -- Asynchronous memory interface |
vma: out std_logic; |
address: out std_logic_vector(15 downto 0); |
rw: out std_logic; -- Asynchronous memory interface |
addr: out std_logic_vector(15 downto 0); |
data_in: in std_logic_vector(7 downto 0); |
data_out: out std_logic_vector(7 downto 0); |
halt: in std_logic; |
126,11 → 138,11
|
begin |
cpu : cpu09 port map ( |
clk => SysClk, |
rst => cpu_reset, |
rw => cpu_rw, |
clk => SysClk, |
rst => cpu_reset, |
vma => cpu_vma, |
address => cpu_addr(15 downto 0), |
rw => cpu_rw, |
addr => cpu_addr(15 downto 0), |
data_in => cpu_data_in, |
data_out => cpu_data_out, |
halt => '0', |
/testbench2.vhd
1,10 → 1,9
--===========================================================================---- |
--===========================================================================-- |
-- -- |
-- TESTBENCH testbench2 - CPU09 Testbench. -- |
-- -- |
--===========================================================================-- |
-- |
-- T E S T B E N C H tesetbench2 - CPU09 Testbench. |
-- |
-- www.OpenCores.Org - September 2003 |
-- This core adheres to the GNU public license |
-- |
-- File name : Testbench2.vhd |
-- |
-- Purpose : cpu09 Microprocessor Test Bench 2 |
20,22 → 19,35
-- |
-- Author : John E. Kent |
-- dilbert57@opencores.org |
-- |
-- Copyright (C) 2003 - 2010 John Kent |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
--===========================================================================-- |
-- -- |
-- Revision History -- |
-- -- |
--===========================================================================-- |
-- |
--===========================================================================---- |
-- Rev Date Author Changes |
-- 0.1 2003-04-12 John Kent First version |
-- 1.0 2003-09-06 John Kent Initial release to Opencores.org |
-- 1.1 2004-01-25 John Kent removed "test_alu" and "test_cc" from CPU component |
-- 1.2 2011-10-09 John Kent renamed address to addr on CPU component, updated header |
-- |
-- Revision History: |
--===========================================================================-- |
-- |
-- Version 0.1 - 12st April 2003 - John Kent |
-- First version |
-- |
-- Version 1.0- 6 Sep 2003 - John Kent |
-- Initial release to Open Cores |
-- |
-- Version 1.1 - 25th Jan 2004 - John Kent |
-- removed "test_alu" and "test_cc" |
-- |
--===========================================================================-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
236,7 → 248,7
rst: in std_logic; |
rw: out std_logic; -- Asynchronous memory interface |
vma: out std_logic; |
address: out std_logic_vector(15 downto 0); |
addr: out std_logic_vector(15 downto 0); |
data_in: in std_logic_vector(7 downto 0); |
data_out: out std_logic_vector(7 downto 0); |
halt: in std_logic; |
254,7 → 266,7
rst => cpu_reset, |
rw => cpu_rw, |
vma => cpu_vma, |
address => cpu_addr(15 downto 0), |
addr => cpu_addr(15 downto 0), |
data_in => cpu_data_in, |
data_out => cpu_data_out, |
halt => '0', |
/ACIA_tb.vhd
1,11 → 1,52
--===========================================================================-- |
-- -- |
-- VHDL 6850 ACIA TestBench -- |
-- -- |
--===========================================================================-- |
-- |
-- |
-- File name : ACIA_tb.vhd |
-- |
-- Entity name : ACIA6850_testbench |
-- |
-- Purpose : VHDL testbench for acia6850 |
-- |
-- Dependencies : ieee.std_logic_1164 |
-- ieee.std_logic_unsigned |
-- ieee.std_logic_arith |
-- ieee.numeric_std |
-- |
-- Author : John E. Kent |
-- |
-- Email : dilbert57@opencores.org |
-- |
-- Web : http://opencores.org/project,system09 |
-- |
-- ACIA 6850 Test Bench |
-- Copyright (C) 2007 - 2011 John Kent |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
--===========================================================================-- |
-- -- |
-- Revision History -- |
-- -- |
--===========================================================================-- |
-- |
-- Rev Date Author Notes |
-- 0.1 2007-02-06 John Kent Initial Version |
-- 0.2 2011-10-09 John Kent Renamed acia_6850 to acia6850 |
-- |
-- |
-- John Kent 6th February 2007 |
-- |
-- |
------------------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
13,13 → 54,13
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
use ieee.numeric_std.all; |
|
entity ACIA_6850_testbench is |
end ACIA_6850_testbench; |
entity ACIA6850_testbench is |
end ACIA6850_testbench; |
|
------------------------------------------------------------------------------- |
-- Architecture for ACIA 6850 Unit |
------------------------------------------------------------------------------- |
architecture behavior of ACIA_6850_testbench is |
architecture behavior of ACIA6850_testbench is |
----------------------------------------------------------------------------- |
-- Signals |
----------------------------------------------------------------------------- |
45,29 → 86,29
-- ACIA 6850 UART |
-- |
----------------------------------------------------------------- |
component ACIA_6850 |
component ACIA6850 |
port ( |
-- |
-- CPU signals |
-- |
clk : in Std_Logic; -- System Clock |
rst : in Std_Logic; -- Reset input (active high) |
cs : in Std_Logic; -- miniUART Chip Select |
rw : in Std_Logic; -- Read / Not Write |
irq : out Std_Logic; -- Interrupt |
Addr : in Std_Logic; -- Register Select |
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In |
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out |
clk : in std_logic; -- System Clock |
rst : in std_logic; -- Reset input (active high) |
cs : in std_logic; -- miniUART Chip Select |
rw : in std_logic; -- Read / Not Write |
addr : in std_logic; -- Register Select |
data_in : in std_logic_vector(7 downto 0); -- Data Bus In |
data_out : out std_logic_vector(7 downto 0); -- Data Bus Out |
irq : out std_logic; -- Interrupt |
-- |
-- Uart Signals |
-- |
RxC : in Std_Logic; -- Receive Baud Clock |
TxC : in Std_Logic; -- Transmit Baud Clock |
RxD : in Std_Logic; -- Receive Data |
TxD : out Std_Logic; -- Transmit Data |
DCD_n : in Std_Logic; -- Data Carrier Detect |
CTS_n : in Std_Logic; -- Clear To Send |
RTS_n : out Std_Logic ); -- Request To send |
RxC : in std_logic; -- Receive Baud Clock |
TxC : in std_logic; -- Transmit Baud Clock |
RxD : in std_logic; -- Receive Data |
TxD : out std_logic; -- Transmit Data |
DCD_n : in std_logic; -- Data Carrier Detect |
CTS_n : in std_logic; -- Clear To Send |
RTS_n : out std_logic ); -- Request To send |
end component; --================== End of entity ==============================-- |
|
begin |
76,15 → 117,15
-- Instantiation of internal components |
----------------------------------------------------------------------------- |
|
my_acia : ACIA_6850 port map ( |
my_acia : ACIA6850 port map ( |
clk => SysClk, |
rst => uart_reset, |
cs => uart_cs, |
rw => uart_rw, |
Irq => uart_irq, |
Addr => uart_addr, |
Datain => uart_data_in, |
DataOut => uart_data_out, |
addr => uart_addr, |
data_in => uart_data_in, |
data_out => uart_data_out, |
irq => uart_irq, |
RxC => rxclk, |
TxC => txclk, |
RxD => rxbit, |
/testbench3.vhd
1,10 → 1,9
--===========================================================================---- |
--===========================================================================-- |
-- -- |
-- TESTBENCH testbench3 - CPU09 Testbench. -- |
-- -- |
--===========================================================================-- |
-- |
-- T E S T B E N C H tesetbench3 - CPU09 Testbench. |
-- |
-- www.OpenCores.Org - September 2003 |
-- This core adheres to the GNU public license |
-- |
-- File name : Testbench3.vhd |
-- |
-- Purpose : cpu09 Microprocessor Test Bench 3 |
19,22 → 18,35
-- |
-- Author : John E. Kent |
-- dilbert57@opencores.org |
-- |
-- Copyright (C) 2003 - 2010 John Kent |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
--===========================================================================-- |
-- -- |
-- Revision History -- |
-- -- |
--===========================================================================-- |
-- |
--===========================================================================---- |
-- Rev Date Author Changes |
-- 0.1 2003-04-12 John Kent First version |
-- 1.0 2003-09-06 John Kent Initial release to Opencores.org |
-- 1.1 2004-02-26 John kent removed test_alu and test_cc signals from CPU component. |
-- 1.2 2011-10-09 John Kent renamed address to addr on CPU component, updated header |
-- |
-- Revision History: |
--===========================================================================-- |
-- |
-- Version 0.1 - 12 Apr 2003 - John Kent |
-- First version |
-- |
-- Version 1.0 - 6 Sep 2003 - John Kent |
-- Initial release to Open Cores |
-- |
-- Version 1.1 - 26 Feb 2004 - John kent |
-- removed test_alu and test_cc signals from |
-- CPU component. |
--===========================================================================-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
122,7 → 134,7
rst: in std_logic; |
rw: out std_logic; -- Asynchronous memory interface |
vma: out std_logic; |
address: out std_logic_vector(15 downto 0); |
addr: out std_logic_vector(15 downto 0); |
data_in: in std_logic_vector(7 downto 0); |
data_out: out std_logic_vector(7 downto 0); |
halt: in std_logic; |
140,7 → 152,7
rst => cpu_reset, |
rw => cpu_rw, |
vma => cpu_vma, |
address => cpu_addr(15 downto 0), |
addr => cpu_addr(15 downto 0), |
data_in => cpu_data_in, |
data_out => cpu_data_out, |
halt => '0', |
/testbench4.vhd
1,28 → 1,67
--===========================================================================-- |
-- -- |
-- TESTBENCH testbench4 - CPU09 Testbench. -- |
-- -- |
--===========================================================================-- |
-- |
-- MC6809 Microprocessor Test Bench 4 |
-- Test Software - SBUG ROM |
-- File name : Testbench4.vhd |
-- |
-- Purpose : cpu09 Microprocessor Test Bench 4 |
-- Contains SBUG ROM |
-- |
-- John Kent 12st April 2003 |
-- Dependencies : ieee.Std_Logic_1164 |
-- ieee.std_logic_unsigned |
-- ieee.std_logic_arith |
-- ieee.numeric_std |
-- |
-- Version 1.1 - 25th Jan 2004 - John Kent |
-- removed "test_alu" and "test_cc" |
-- Uses : cpu09 (..\VHDL\cpu09.vhd) CPU core |
-- ram_2k (..\Spartan3\ram2k_b16.vhd) 2KB block RAM |
-- mon_rom (..\Spartan3\sbug_rom2k_b16.vhd) 2KB SBUG block ROM |
-- |
-- Author : John E. Kent |
-- dilbert57@opencores.org |
-- |
-- Copyright (C) 2003 - 2011 John Kent |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
--===========================================================================-- |
-- -- |
-- Revision History -- |
-- -- |
--===========================================================================-- |
-- |
-- Rev Date Author Changes |
-- 0.1 2003-04-12 John Kent First version |
-- 1.0 2003-09-06 John Kent Initial release to Opencores.org |
-- 1.1 2004-02-25 John kent removed test_alu and test_cc signals from CPU component. |
-- 1.2 2011-10-09 John Kent renamed address to addr on CPU component, updated header |
-- |
------------------------------------------------------------------------------- |
--===========================================================================-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use ieee.numeric_std.all; |
|
entity my_testbench is |
end my_testbench; |
entity my_testbench4 is |
end my_testbench4; |
|
------------------------------------------------------------------------------- |
-- Architecture for memio Controller Unit |
------------------------------------------------------------------------------- |
architecture behavior of my_testbench is |
architecture behavior of my_testbench4 is |
----------------------------------------------------------------------------- |
-- Signals |
----------------------------------------------------------------------------- |
50,7 → 89,7
rst: in std_logic; |
rw: out std_logic; -- Asynchronous memory interface |
vma: out std_logic; |
address: out std_logic_vector(15 downto 0); |
addr: out std_logic_vector(15 downto 0); |
data_in: in std_logic_vector(7 downto 0); |
data_out: out std_logic_vector(7 downto 0); |
halt: in std_logic; |
62,22 → 101,27
end component; |
|
|
component sbug_rom |
component mon_rom |
Port ( |
MEMclk : in std_logic; |
MEMaddr : in std_logic_vector (10 downto 0); |
MEMrdata : out std_logic_vector (7 downto 0) |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
rw : in std_logic; |
addr : in std_logic_vector (10 downto 0); |
data_in : in std_logic_vector (7 downto 0); |
data_out : out std_logic_vector (7 downto 0) |
); |
end component; |
|
component block_ram |
|
component ram_2k |
Port ( |
MEMclk : in std_logic; |
MEMcs : in std_logic; |
MEMrw : in std_logic; |
MEMaddr : in std_logic_vector (10 downto 0); |
MEMrdata : out std_logic_vector (7 downto 0); |
MEMwdata : in std_logic_vector (7 downto 0) |
clk : in std_logic; |
rst : in std_logic; |
cs : in std_logic; |
addr : in std_logic_vector (10 downto 0); |
rw : in std_logic; |
data_in : in std_logic_vector (7 downto 0); |
data_out : out std_logic_vector (7 downto 0) |
); |
end component; |
|
87,7 → 131,7
rst => cpu_reset, |
rw => cpu_rw, |
vma => cpu_vma, |
address => cpu_addr(15 downto 0), |
addr => cpu_addr(15 downto 0), |
data_in => cpu_data_in, |
data_out => cpu_data_out, |
halt => cpu_halt, |
98,21 → 142,27
); |
|
|
my_ram : block_ram port map ( |
MEMclk => SysClk, |
MEMcs => ram_cs, |
MEMrw => cpu_rw, |
MEMaddr => cpu_addr(10 downto 0), |
MEMrdata => ram_data_out, |
MEMwdata => cpu_data_out |
my_rom : mon_rom port map ( |
clk => SysClk, |
rst => cpu_reset, |
cs => ram_cs, |
rw => cpu_rw, |
addr => cpu_addr(10 downto 0), |
data_in => cpu_data_out, |
data_out => rom_data_out |
); |
|
my_rom : sbug_rom port map ( |
MEMclk => SysClk, |
MEMaddr => cpu_addr(10 downto 0), |
MEMrdata => rom_data_out |
|
my_ram : ram_2k port map ( |
clk => SysClk, |
rst => cpu_reset, |
cs => ram_cs, |
rw => cpu_rw, |
addr => cpu_addr(10 downto 0), |
data_in => cpu_data_out, |
data_out => ram_data_out |
); |
|
|
-- *** Test Bench - User Defined Section *** |
tb : PROCESS |
variable count : integer; |
/testbench5.vhd
1,13 → 1,12
--===========================================================================---- |
--===========================================================================-- |
-- -- |
-- TESTBENCH testbench5 - CPU09 Testbench. -- |
-- -- |
--===========================================================================-- |
-- |
-- T E S T B E N C H tesetbench3 - CPU09 Testbench. |
-- |
-- www.OpenCores.Org - September 2003 |
-- This core adheres to the GNU public license |
-- |
-- File name : Testbench5.vhd |
-- |
-- Purpose : cpu09 Microprocessor Test Bench 3 |
-- Purpose : cpu09 Microprocessor Test Bench 5 |
-- Contains ROM to test interrupts |
-- |
-- Dependencies : ieee.Std_Logic_1164 |
15,26 → 14,39
-- ieee.std_logic_arith |
-- ieee.numeric_std |
-- |
-- Uses : cpu09 (cpu09.vhd) CPU core |
-- Uses : cpu09 (..\VHDL\cpu09.vhd) CPU core |
-- |
-- Author : John E. Kent |
-- dilbert57@opencores.org |
-- |
-- Copyright (C) 2003 - 2011 John Kent |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
--===========================================================================-- |
-- -- |
-- Revision History -- |
-- -- |
--===========================================================================-- |
-- |
--===========================================================================---- |
-- Rev Date Author Changes |
-- 0.1 2003-04-12 John Kent First version |
-- 1.0 2003-09-06 John Kent Initial release to Opencores.org |
-- 1.1 2004-02-25 John kent removed test_alu and test_cc signals from CPU component. |
-- 1.2 2011-10-09 John Kent renamed address to addr on CPU component, updated header |
-- |
-- Revision History: |
--===========================================================================-- |
-- |
-- Version 0.1 - 12st April 2003 - John Kent |
-- First version |
-- |
-- Version 1.0 - 6 Sep 2003 - John Kent |
-- Initial release to Open Cores |
-- |
-- Version 1.1 - 25th Jan 2004 - John Kent |
-- removed "test_alu" and "test_cc" |
-- |
--===========================================================================-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
126,7 → 138,7
rst: in std_logic; |
rw: out std_logic; -- Asynchronous memory interface |
vma: out std_logic; |
address: out std_logic_vector(15 downto 0); |
addr: out std_logic_vector(15 downto 0); |
data_in: in std_logic_vector(7 downto 0); |
data_out: out std_logic_vector(7 downto 0); |
halt: in std_logic; |
144,7 → 156,7
rst => cpu_reset, |
rw => cpu_rw, |
vma => cpu_vma, |
address => cpu_addr(15 downto 0), |
addr => cpu_addr(15 downto 0), |
data_in => cpu_data_in, |
data_out => cpu_data_out, |
halt => '0', |
/testbench6.vhd
1,10 → 1,9
--===========================================================================---- |
--===========================================================================-- |
-- -- |
-- TESTBENCH testbench6 - CPU09 Testbench. -- |
-- -- |
--===========================================================================-- |
-- |
-- T E S T B E N C H tesetbench3 - CPU09 Testbench. |
-- |
-- www.OpenCores.Org - September 2003 |
-- This core adheres to the GNU public license |
-- |
-- File name : Testbench6.vhd |
-- |
-- Purpose : cpu09 Microprocessor Test Bench 6 |
15,26 → 14,39
-- ieee.std_logic_arith |
-- ieee.numeric_std |
-- |
-- Uses : cpu09 (cpu09.vhd) CPU core |
-- Uses : cpu09 (..\VHDL\cpu09.vhd) CPU core |
-- |
-- Author : John E. Kent |
-- dilbert57@opencores.org |
-- |
-- Copyright (C) 2003 - 2011 John Kent |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
--===========================================================================-- |
-- -- |
-- Revision History -- |
-- -- |
--===========================================================================-- |
-- |
--===========================================================================---- |
-- Rev Date Author Changes |
-- 0.1 2003-04-12 John Kent First version |
-- 1.0 2003-09-06 John Kent Initial release to Opencores.org |
-- 1.1 2004-02-25 John kent removed test_alu and test_cc signals from CPU component. |
-- 1.2 2011-10-09 John Kent renamed address to addr on CPU component, updated header |
-- |
-- Revision History: |
--===========================================================================-- |
-- |
-- Version 0.1 - 12st April 2003 - John Kent |
-- First version |
-- |
-- Version 1.0 - 6 Sep 2003 - John Kent |
-- Initial release to Open Cores |
-- |
-- Version 1.1 - 25th Jan 2004 - John Kent |
-- removed "test_alu" and "test_cc" |
-- |
--===========================================================================-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
118,7 → 130,7
rst: in std_logic; |
rw: out std_logic; -- Asynchronous memory interface |
vma: out std_logic; |
address: out std_logic_vector(15 downto 0); |
addr: out std_logic_vector(15 downto 0); |
data_in: in std_logic_vector(7 downto 0); |
data_out: out std_logic_vector(7 downto 0); |
halt: in std_logic; |
136,7 → 148,7
rst => cpu_reset, |
rw => cpu_rw, |
vma => cpu_vma, |
address => cpu_addr(15 downto 0), |
addr => cpu_addr(15 downto 0), |
data_in => cpu_data_in, |
data_out => cpu_data_out, |
halt => '0', |
/vdu8_tb.vhd
0,0 → 1,258
--===========================================================================-- |
-- -- |
-- TESTBENCH vdu8_tb - VDU8 Testbench. -- |
-- -- |
--===========================================================================-- |
-- |
-- File name : vdu8_tb.vhd |
-- |
-- Purpose : Test system09 VDU8 component |
-- |
-- Dependencies : ieee.Std_Logic_1164 |
-- ieee.std_logic_unsigned |
-- ieee.std_logic_arith |
-- ieee.numeric_std |
-- |
-- Uses : vdu8 (..\VHDL\vdu8.vhd) CPU core |
-- ram_2k (..\Spartan3\ram2k_b16.vhd) 2KB block RAM |
-- char_rom (..\Spartan3\char_rom2k_b16.vhd) 2KB chracter block ROM |
-- |
-- Author : John E. Kent |
-- dilbert57@opencores.org |
-- |
-- Copyright (C) 2008 - 2011 John Kent |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
--===========================================================================-- |
-- -- |
-- Revision History -- |
-- -- |
--===========================================================================-- |
-- |
-- Rev Date Author Changes |
-- 0.1 2008-07-30 John Kent First version |
-- 0.2 2011-10-09 John Kent updated header & vdu component |
-- |
--===========================================================================-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
use ieee.numeric_std.all; |
library unisim; |
use unisim.vcomponents.all; |
|
entity my_vdu8_tb is |
end my_vdu8_tb; |
|
architecture behavior of my_vdu8_tb is |
|
constant CPU_FREQ : natural := 25_000_000; -- CPU Clock (Hz) |
constant PIX_FREQ : natural := 25_000_000; -- VGA Pixel Clock |
|
-- CRTC output signals |
signal vga_vsync_n : Std_Logic; |
signal vga_hsync_n : Std_Logic; |
signal vga_blue : std_logic; |
signal vga_green : std_logic; |
signal vga_red : std_logic; |
|
-- CPU Debug Interface signals |
signal cpu_reset : Std_Logic; |
signal cpu_clk : Std_Logic; |
signal cpu_rw : std_logic; |
signal cpu_addr : std_logic_vector(2 downto 0); |
signal vdu_data_out : std_logic_vector(7 downto 0); |
signal cpu_data_out : std_logic_vector(7 downto 0); |
signal pix_clk : std_logic; |
signal vdu_cs : std_logic; |
|
---------------------------------------- |
-- |
-- Video Display Unit. |
-- |
---------------------------------------- |
component vdu8 |
generic( |
VGA_CLK_FREQ : integer := PIX_FREQ; -- HZ |
VGA_HOR_CHARS : integer := 80; -- CHARACTERS 25.6us |
VGA_HOR_CHAR_PIXELS : integer := 8; -- PIXELS 0.32us |
VGA_HOR_FRONT_PORCH : integer := 16; -- PIXELS 0.64us |
VGA_HOR_SYNC : integer := 96; -- PIXELS 3.84us |
VGA_HOR_BACK_PORCH : integer := 48; -- PIXELS 1.92us |
VGA_VER_CHARS : integer := 25; -- CHARACTERS 12.8ms |
VGA_VER_CHAR_LINES : integer := 16; -- LINES 0.512ms |
VGA_VER_FRONT_PORCH : integer := 10; -- LINES 0.320ms |
VGA_VER_SYNC : integer := 2; -- LINES 0.064ms |
VGA_VER_BACK_PORCH : integer := 34 -- LINES 1.088ms |
); |
port( |
-- control register interface |
vdu_clk : in std_logic; -- 12.5/25 MHz CPU Clock |
vdu_rst : in std_logic; |
vdu_cs : in std_logic; |
vdu_rw : in std_logic; |
vdu_addr : in std_logic_vector(2 downto 0); |
vdu_data_in : in std_logic_vector(7 downto 0); |
vdu_data_out : out std_logic_vector(7 downto 0); |
|
-- vga port connections |
vga_clk : in std_logic; -- 25MHz clock |
vga_red_o : out std_logic; |
vga_green_o : out std_logic; |
vga_blue_o : out std_logic; |
vga_hsync_o : out std_logic; |
vga_vsync_o : out std_logic |
); |
end component; |
|
begin |
---------------------------------------- |
-- |
-- Video Display Unit instantiation |
-- |
---------------------------------------- |
my_vdu : vdu8 |
generic map( |
VGA_CLK_FREQ => PIX_FREQ, -- HZ |
VGA_HOR_CHARS => 80, -- CHARACTERS |
VGA_HOR_CHAR_PIXELS => 8, -- PIXELS |
VGA_HOR_FRONT_PORCH => 16, -- PIXELS |
VGA_HOR_SYNC => 96, -- PIXELS |
VGA_HOR_BACK_PORCH => 48, -- PIXELS |
VGA_VER_CHARS => 25, -- CHARACTERS |
VGA_VER_CHAR_LINES => 16, -- LINES |
VGA_VER_FRONT_PORCH => 10, -- LINES |
VGA_VER_SYNC => 2, -- LINES |
VGA_VER_BACK_PORCH => 34 -- LINES |
) |
port map( |
|
-- Control Registers |
vdu_clk => cpu_clk, -- 12.5 MHz System Clock in |
vdu_rst => cpu_reset, |
vdu_cs => vdu_cs, |
vdu_rw => cpu_rw, |
vdu_addr => cpu_addr(2 downto 0), |
vdu_data_in => cpu_data_out, |
vdu_data_out => vdu_data_out, |
|
-- vga port connections |
vga_clk => pix_clk, -- 25 MHz VDU pixel clock |
vga_red_o => vga_red, |
vga_green_o => vga_green, |
vga_blue_o => vga_blue, |
vga_hsync_o => vga_hsync_n, |
vga_vsync_o => vga_vsync_n |
); |
|
events : PROCESS(pix_clk) |
variable count : integer := 0; |
BEGIN |
if falling_edge(cpu_clk) then |
case count is |
-- |
-- reset VDU registers |
-- |
when 0 => |
cpu_reset <= '1'; |
vdu_cs <= '0'; |
cpu_rw <= '1'; |
cpu_addr <= "000"; |
cpu_data_out <= "00000000"; |
when 8 => |
cpu_reset <= '0'; |
-- |
-- write data register |
-- |
when 10 => |
vdu_cs <= '1'; |
cpu_rw <= '0'; |
cpu_addr <= "000"; |
cpu_data_out <= "01101001"; |
when 11 => |
vdu_cs <= '0'; |
cpu_rw <= '1'; |
-- |
-- write attribute register |
-- |
when 12 => |
vdu_cs <= '1'; |
cpu_rw <= '0'; |
cpu_addr <= "001"; |
cpu_data_out <= "00000111"; |
when 13 => |
vdu_cs <= '0'; |
cpu_rw <= '1'; |
-- |
-- write cursor column ? |
when 14 => |
vdu_cs <= '1'; |
cpu_rw <= '0'; |
cpu_addr <= "010"; |
cpu_data_out <= "00000001"; |
when 15 => |
vdu_cs <= '0'; |
cpu_rw <= '1'; |
-- |
-- write cursor row ? |
-- |
when 16 => |
vdu_cs <= '1'; |
cpu_rw <= '0'; |
cpu_addr <= "011"; |
cpu_data_out <= "00000011"; |
when 17 => |
vdu_cs <= '0'; |
cpu_rw <= '1'; |
-- |
-- write vertical offset |
-- |
when 18 => |
vdu_cs <= '1'; |
cpu_rw <= '0'; |
cpu_addr <= "100"; |
cpu_data_out <= "00001001"; |
when 19 => |
vdu_cs <= '0'; |
cpu_rw <= '1'; |
when others => |
null; |
end case; |
count := count + 1; |
end if; |
end process; |
|
-- |
-- Generate a master clock for the SDRAM controller |
-- |
tb : PROCESS |
variable i : integer; |
BEGIN |
for i in 0 to 360000 loop |
pix_clk <= '0'; |
cpu_clk <= '0'; |
wait for 20 ns; |
pix_clk <= '1'; |
cpu_clk <= '1'; |
wait for 20 ns; |
end loop; |
wait; -- will wait forever |
end process; |
|
-- *** End Test Bench - User Defined Section *** |
|
end architecture; |
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